mb/system76: Rename gaze16 to tgl-h

Change-Id: Icbf9348447b9e7acc0caa8082cf5dd00853da37a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>

31 files changed, 1323 insertions, 0 deletions

diff --git a/src/mainboard/system76/tgl-h/Kconfig b/src/mainboard/system76/tgl-h/Kconfig
new file mode 100644
index 000000000000..cceb1ed374ee
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/Kconfig
@@ -0,0 +1,70 @@
+if BOARD_SYSTEM76_GAZE16_3050 || BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DRIVERS_I2C_HID
+	select EC_SYSTEM76_EC
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_LPSS_UART_FOR_CONSOLE
+	select MEMORY_MAPPED_TPM
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_USES_IFD_GBE_REGION if BOARD_SYSTEM76_GAZE16_3060_B
+	select NO_UART_ON_SUPERIO
+	select SOC_INTEL_TIGERLAKE
+	select SOC_INTEL_TIGERLAKE_PCH_H
+	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+	select SPD_READ_BY_WORD
+	select SYSTEM_TYPE_LAPTOP
+	select TPM_MEASURED_BOOT
+	select TPM_RDRESP_NEED_DELAY
+
+config MAINBOARD_DIR
+	default "system76/tgl-h"
+
+config MAINBOARD_PART_NUMBER
+	default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
+	default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060
+	default "gaze16-3060-b" if BOARD_SYSTEM76_GAZE16_3060_B
+
+config MAINBOARD_SMBIOS_PRODUCT_NAME
+	default "Gazelle"
+
+config MAINBOARD_VERSION
+	default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
+	default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060
+	default "gaze16-3060-b" if BOARD_SYSTEM76_GAZE16_3060_B
+
+config VARIANT_DIR
+	default "gaze16-3050" if BOARD_SYSTEM76_GAZE16_3050
+	default "gaze16-3060" if BOARD_SYSTEM76_GAZE16_3060 || BOARD_SYSTEM76_GAZE16_3060_B
+
+config OVERRIDE_DEVICETREE
+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config CBFS_SIZE
+	default 0xA00000
+
+config CONSOLE_POST
+	default y
+
+config ONBOARD_VGA_IS_PRIMARY
+	default y
+
+config POST_DEVICE
+	default n
+
+config UART_FOR_CONSOLE
+	default 2
+
+# PM Timer Disabled, saves power
+config USE_PM_ACPI_TIMER
+	default n
+
+endif
diff --git a/src/mainboard/system76/tgl-h/Kconfig.name b/src/mainboard/system76/tgl-h/Kconfig.name
new file mode 100644
index 000000000000..1ea29aeb12e8
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/Kconfig.name
@@ -0,0 +1,8 @@
+config BOARD_SYSTEM76_GAZE16_3050
+	bool "gaze16 3050"
+
+config BOARD_SYSTEM76_GAZE16_3060
+	bool "gaze16 3060"
+
+config BOARD_SYSTEM76_GAZE16_3060_B
+	bool "gaze16 3060-b"
diff --git a/src/mainboard/system76/tgl-h/Makefile.inc b/src/mainboard/system76/tgl-h/Makefile.inc
new file mode 100644
index 000000000000..6ade517c34a2
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/Makefile.inc
@@ -0,0 +1,13 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
+
+bootblock-y += bootblock.c
+bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
+
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ramstage-y += ramstage.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-y += variants/$(VARIANT_DIR)/ramstage.c
diff --git a/src/mainboard/system76/tgl-h/acpi/mainboard.asl b/src/mainboard/system76/tgl-h/acpi/mainboard.asl
new file mode 100644
index 000000000000..4675bc94b85b
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/acpi/mainboard.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define EC_GPE_SCI 0x6E
+#define EC_GPE_SWI 0x6B
+#include <ec/system76/ec/acpi/ec.asl>
+
+Scope (\_SB) {
+	#include "sleep.asl"
+}
diff --git a/src/mainboard/system76/tgl-h/acpi/sleep.asl b/src/mainboard/system76/tgl-h/acpi/sleep.asl
new file mode 100644
index 000000000000..83888f3e59e9
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/acpi/sleep.asl
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <intelblocks/gpio.h>
+
+Method (PGPM, 1, Serialized)
+{
+	For (Local0 = 0, Local0 < 6, Local0++)
+	{
+		\_SB.PCI0.CGPM (Local0, Arg0)
+	}
+}
+
+/*
+ * Method called from _PTS prior to system sleep state entry
+ * Enables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MPTS, 1, Serialized)
+{
+	\_SB.PCI0.LPCB.EC0.PTS (Arg0)
+	PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+}
+
+/*
+ * Method called from _WAK prior to system sleep state wakeup
+ * Disables dynamic clock gating for all 5 GPIO communities
+ */
+Method (MWAK, 1, Serialized)
+{
+	PGPM (0)
+	\_SB.PCI0.LPCB.EC0.WAK (Arg0)
+}
+
+/*
+ * S0ix Entry/Exit Notifications
+ * Called from \_SB.PEPD._DSM
+ */
+Method (MS0X, 1, Serialized)
+{
+	If (Arg0 == 1) {
+		/* S0ix Entry */
+		PGPM (MISCCFG_GPIO_PM_CONFIG_BITS)
+	} Else {
+		/* S0ix Exit */
+		PGPM (0)
+	}
+}
diff --git a/src/mainboard/system76/tgl-h/board_info.txt b/src/mainboard/system76/tgl-h/board_info.txt
new file mode 100644
index 000000000000..badfb667068c
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: System76
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/system76/tgl-h/bootblock.c b/src/mainboard/system76/tgl-h/bootblock.c
new file mode 100644
index 000000000000..0dc25dd200b0
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/bootblock.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <variant/gpio.h>
+
+void bootblock_mainboard_init(void)
+{
+	variant_configure_early_gpios();
+}
diff --git a/src/mainboard/system76/tgl-h/cmos.default b/src/mainboard/system76/tgl-h/cmos.default
new file mode 100644
index 000000000000..0d376751c17d
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/cmos.default
@@ -0,0 +1,3 @@
+boot_option=Fallback
+debug_level=Debug
+me_state=Disable
diff --git a/src/mainboard/system76/tgl-h/cmos.layout b/src/mainboard/system76/tgl-h/cmos.layout
new file mode 100644
index 000000000000..a53c3f4bbabd
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/cmos.layout
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+entries
+
+0	384	r	0	reserved_memory
+
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	4	boot_option
+388	4	h	0	reboot_counter
+
+# RTC_CLK_ALTCENTURY
+400	8	r	0	century
+
+412	4	e	6	debug_level
+416	1	e	2	me_state
+417	3	h	0	me_state_counter
+984	16	h	0	check_sum
+
+enumerations
+
+2	0	Enable
+2	1	Disable
+
+4	0	Fallback
+4	1	Normal
+
+6	0	Emergency
+6	1	Alert
+6	2	Critical
+6	3	Error
+6	4	Warning
+6	5	Notice
+6	6	Info
+6	7	Debug
+6	8	Spew
+
+checksums
+
+checksum 408 983 984
diff --git a/src/mainboard/system76/tgl-h/devicetree.cb b/src/mainboard/system76/tgl-h/devicetree.cb
new file mode 100644
index 000000000000..e26fe629b4f7
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/devicetree.cb
@@ -0,0 +1,149 @@
+chip soc/intel/tigerlake
+	register "common_soc_config" = "{
+		// Touchpad I2C bus
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 80,
+			.fall_time_ns = 110,
+		},
+	}"
+
+# ACPI (soc/intel/tigerlake/acpi.c)
+	# Enable Enhanced Intel SpeedStep
+	register "eist_enable" = "1"
+
+# CPU (soc/intel/tigerlake/cpu.c)
+	# Power limits
+	register "power_limits_config[POWER_LIMITS_H_8_CORE]" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 109,
+	}"
+	register "power_limits_config[POWER_LIMITS_H_6_CORE]" = "{
+		.tdp_pl1_override = 45,
+		.tdp_pl2_override = 109,
+	}"
+
+# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c)
+	# Enable C6 DRAM
+	register "enable_c6dram" = "1"
+
+# FSP Silicon (soc/intel/tigerlake/fsp_params.c)
+	# Acoustic settings
+	register "AcousticNoiseMitigation" = "1"
+	register "SlowSlewRate" = "SLEW_FAST_8"
+	register "FastPkgCRampDisable" = "1"
+
+	# FIVR configuration
+	#   Read EXT_RAIL_CONFIG to determine bitmaps
+	#     sudo devmem2 0xfe0011b8
+	#     0x0
+	#   Read EXT_V1P05_VR_CONFIG
+	#     sudo devmem2 0xfe0011c0
+	#     0x1a42000
+	#   Read EXT_VNN_VR_CONFIG0
+	#     sudo devmem2 0xfe0011c4
+	#     0x1a42000
+	# TODO: v1p05 voltage and vnn icc max?
+	register "ext_fivr_settings" = "{
+		.configure_ext_fivr = 1,
+		.v1p05_enable_bitmap = 0,
+		.vnn_enable_bitmap = 0,
+		.v1p05_supported_voltage_bitmap = 0,
+		.vnn_supported_voltage_bitmap = 0,
+		.v1p05_icc_max_ma = 500,
+		.vnn_sx_voltage_mv = 1050,
+	}"
+
+	# Disable S0ix substates
+	register "LpmStateDisableMask" = "
+		LPM_S0i2_1 |
+		LPM_S0i2_2 |
+		LPM_S0i3_1 |
+		LPM_S0i3_2 |
+		LPM_S0i3_3 |
+		LPM_S0i3_4
+	"
+
+	# Thermal
+	# rdmsr --bitfield 31:24 --decimal 0x1A2
+	register "tcc_offset" = "8"
+
+	# Enable CNVi BT
+	register "CnviBtCore" = "true"
+
+# PM Util (soc/intel/tigerlake/pmutil.c)
+	# GPE configuration
+	register "pmc_gpe0_dw0" = "PMC_GPP_R"
+	register "pmc_gpe0_dw1" = "PMC_GPP_B"
+	register "pmc_gpe0_dw2" = "PMC_GPP_D"
+
+# Actual device tree
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	device domain 0 on
+		#From CPU EDS(575683)
+		device ref system_agent on end
+		device ref igpu on
+			# DDIA is eDP
+			register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
+			register "DdiPortAHpd" = "1"
+			register "DdiPortADdc" = "0"
+
+			# DDIB is HDMI
+			register "DdiPortBConfig" = "DDI_PORT_CFG_NO_LFP"
+			register "DdiPortBHpd" = "1"
+			register "DdiPortBDdc" = "1"
+
+			register "gfx" = "GMA_DEFAULT_PANEL(0)"
+		end
+		device ref dptf on end
+		device ref gna on end
+		device ref north_xhci on
+			# TODO: No TBT, but needed for USB 2.0 on Type-C port?
+			register "TcssXhciEn" = "1"
+		end
+
+		# From PCH EDS(615985)
+		device ref shared_ram on end
+		device ref cnvi_wifi on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end
+		device ref i2c0 on
+			# Touchpad I2C bus
+			register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN0412""
+				register "generic.desc" = ""ELAN Touchpad""
+				register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_R12)"
+				register "generic.detect" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 15 on end
+			end
+		end
+		device ref heci1 on end
+		device ref uart2 on
+			# Debug console
+			register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
+		end
+		device ref pch_espi on
+			register "gen1_dec" = "0x00040069" # EC PM channel
+			register "gen2_dec" = "0x00fc0E01" # AP/EC command
+			register "gen3_dec" = "0x00fc0F01" # AP/EC debug
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end
+		device ref p2sb on end
+		device ref pmc hidden end
+		device ref hda on
+			register "PchHdaAudioLinkHdaEnable" = "1"
+		end
+		device ref smbus on end
+		device ref fast_spi on end
+	end
+end
diff --git a/src/mainboard/system76/tgl-h/dsdt.asl b/src/mainboard/system76/tgl-h/dsdt.asl
new file mode 100644
index 000000000000..a86fe9c6de53
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/dsdt.asl
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include <soc/intel/common/block/acpi/acpi/platform.asl>
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+		#include <soc/intel/tigerlake/acpi/southbridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Scope (\_SB.PCI0.LPCB)
+	{
+		#include <drivers/pc80/pc/ps2_controller.asl>
+	}
+
+	#include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/system76/tgl-h/include/variant/gpio.h b/src/mainboard/system76/tgl-h/include/variant/gpio.h
new file mode 100644
index 000000000000..95d576294f6d
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/include/variant/gpio.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+void variant_configure_early_gpios(void);
+void variant_configure_gpios(void);
+
+#endif
diff --git a/src/mainboard/system76/tgl-h/include/variant/romstage.h b/src/mainboard/system76/tgl-h/include/variant/romstage.h
new file mode 100644
index 000000000000..9008cb95f2a0
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/include/variant/romstage.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_ROMSTAGE_H
+#define VARIANT_ROMSTAGE_H
+
+#include <fsp/soc_binding.h>
+
+void variant_memory_init_params(FSPM_UPD *mupd);
+
+#endif
diff --git a/src/mainboard/system76/tgl-h/ramstage.c b/src/mainboard/system76/tgl-h/ramstage.c
new file mode 100644
index 000000000000..49b9934aed2c
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/ramstage.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+#include <smbios.h>
+
+smbios_wakeup_type smbios_system_wakeup_type(void)
+{
+	return SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
+}
+
+static void mainboard_init(void *chip_info)
+{
+	variant_configure_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+};
diff --git a/src/mainboard/system76/tgl-h/romstage.c b/src/mainboard/system76/tgl-h/romstage.c
new file mode 100644
index 000000000000..f69bae98eb16
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/romstage.c
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <variant/romstage.h>
+
+static const struct mb_cfg board_cfg = {
+	.type = MEM_TYPE_DDR4,
+	.ddr4_config = {
+		.dq_pins_interleaved = true,
+	},
+};
+
+static const struct mem_spd spd_info = {
+	.topo = MEM_TOPO_DIMM_MODULE,
+	.smbus = {
+		[0] = { .addr_dimm[0] = 0x50, },
+		[1] = { .addr_dimm[0] = 0x52, },
+	},
+};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	variant_memory_init_params(mupd);
+
+	const bool half_populated = false;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/board_info.txt b/src/mainboard/system76/tgl-h/variants/gaze16-3050/board_info.txt
new file mode 100644
index 000000000000..6555d4d96054
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/board_info.txt
@@ -0,0 +1,2 @@
+Board name: gaze16
+Release year: 2021
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt b/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt
new file mode 100644
index 000000000000..297522723cbb
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/data.vbt
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c
new file mode 100644
index 000000000000..60b82de86fc1
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio.c
@@ -0,0 +1,281 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKE#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE), // PCH_SLP_WLAN# (100k pull-down)
+	PAD_NC(GPD10, NONE), // SLP_S5# (100k pull-down)
+	PAD_NC(GPD11, NONE),
+	PAD_NC(GPD12, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_AD0
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_AD1
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_AD2
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_AD3
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_FRAME#
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_KBC
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_NC(GPP_A9, NONE),
+	PAD_CFG_GPI(GPP_A10, UP_20K, DEEP), // SERIRQ
+	PAD_NC(GPP_A11, NONE),
+	PAD_NC(GPP_A12, NONE),
+	PAD_NC(GPP_A13, NONE),
+	PAD_NC(GPP_A14, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ#
+	PAD_NC(GPP_B1, NONE),
+	PAD_NC(GPP_B2, NONE),
+	PAD_CFG_GPO(GPP_B3, 1, DEEP), // EC_BT_EN
+	PAD_NC(GPP_B4, NONE),
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GFX_CLKREQ0#
+	PAD_NC(GPP_B6, NONE),
+	PAD_NC(GPP_B7, NONE),
+	PAD_NC(GPP_B8, NONE),
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), // SSD2_CLKREQ4#
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), // LAN_CLKREQ5#
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_CFG_GPO(GPP_B15, 1, DEEP), // SSD_PWR_EN#
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // GSPI0_MOSI
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_NC(GPP_B22, NONE),
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // SML1_ALERT#
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT
+	PAD_CFG_GPI(GPP_C2, NONE, DEEP), // CNVI_WAKE#
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_CFG_GPI(GPP_C5, NONE, DEEP), // SML0_ALERT#
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP), // BOARD_ID3
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_CFG_GPI(GPP_C14, NONE, DEEP), // GPC14_RTD3
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, PWROK, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_C17, NONE, PWROK, NF1), // I2C_SCL_TP
+	PAD_CFG_GPI(GPP_C18, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_C19, NONE, DEEP), // SWI#
+	//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, NONE),
+	PAD_CFG_GPI(GPP_C23, NONE, DEEP), // SMI#
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), // SML1_CLK
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), // CNVI_RF_RST#
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // XTAL_CLKREQ
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), // SML0_CLK
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // SML0_DATA
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), // SML1_DATA
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_NC(GPP_D23, NONE),
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI#
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP), // DEVSLP0
+	PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), // DEVSLP1
+	PAD_NC(GPP_E6, NONE),
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
+	PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
+	PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3#
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),
+	PAD_NC(GPP_F1, NONE),
+	PAD_CFG_GPO(GPP_F2, 1, PLTRST), // LAN_RTD3#
+	PAD_CFG_GPO(GPP_F3, 1, DEEP), // GPP_LAN_RST#
+	PAD_CFG_GPO(GPP_F4, 1, DEEP), // SATA_PWR_EN
+	PAD_CFG_GPO(GPP_F5, 1, DEEP), // 1P05_CTRL
+	PAD_NC(GPP_F6, NONE),
+	PAD_NC(GPP_F7, NONE),
+	//PAD_CFG_GPO(GPP_F8, 1, DEEP), // DGPU_RST#_PCH
+	//PAD_CFG_GPO(GPP_F9, 1, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC
+	PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD
+	PAD_CFG_GPO(GPP_F12, 1, DEEP), // PCH_WLAN_EN
+	PAD_NC(GPP_F13, NONE),
+	PAD_NC(GPP_F14, NONE),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // SKTOCC#
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPO(GPP_F17, 1, DEEP), // SB_BLON
+	PAD_NC(GPP_F18, NONE),
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+	PAD_NC(GPP_F22, NONE), // VNN_CTRL
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP), // CNVI_DET#
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, NONE),
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, NONE),
+	PAD_NC(GPP_G8, NONE),
+	PAD_CFG_GPI(GPP_G9, NONE, DEEP), // GPP_G9
+	PAD_NC(GPP_G10, NONE),
+	PAD_CFG_GPI(GPP_G11, NONE, DEEP), // GPP_G11
+	PAD_NC(GPP_G12, NONE),
+	_PAD_CFG_STRUCT(GPP_G13, 0x44001300, 0x3c00), // GPP_G13
+	PAD_NC(GPP_G14, NONE),
+	PAD_NC(GPP_G15, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // CARD_CLKREQ7#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // WLAN_CLKREQ8#
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // SSD1_CLKREQ9#
+	PAD_NC(GPP_H4, NONE),
+	PAD_NC(GPP_H5, NONE),
+	PAD_CFG_GPI(GPP_H6, NONE, DEEP), // SB_KBCRST#
+	PAD_NC(GPP_H7, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_CFG_GPI(GPP_H10, NONE, DEEP), // SML_2CLK
+	PAD_CFG_GPI(GPP_H11, NONE, DEEP), // SML_2DATA
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP), // SML_2ALERT#
+	PAD_CFG_GPI(GPP_H13, NONE, DEEP), // SML_3CLK
+	PAD_CFG_GPI(GPP_H14, NONE, DEEP), // SML_3DATA
+	PAD_CFG_GPI(GPP_H15, NONE, PLTRST), // SML_3ALERT#
+	PAD_CFG_GPI(GPP_H16, NONE, DEEP), // SML_4CLK
+	PAD_CFG_GPO(GPP_H17, 1, DEEP), // SSD2_PWR_EN#
+	PAD_CFG_GPI(GPP_H18, NONE, DEEP), // SML_4ALERT#
+	PAD_CFG_GPI(GPP_H19, NONE, DEEP), // PCH_FLASH_I2C_SDA
+	PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PCH_FLASH_I2C_SCL
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_CFG_GPO(GPP_H23, 1, DEEP), // M2_SSD_RST#
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_CFG_NF(GPP_I0, NONE, PWROK, NF1), // PMC_ALERT#
+	PAD_CFG_GPI(GPP_I1, NONE, DEEP), // GPU_EVENT#
+	PAD_NC(GPP_I2, NONE),
+	PAD_NC(GPP_I3, NONE),
+	PAD_NC(GPP_I4, NONE),
+	PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_NC(GPP_I7, NONE),
+	PAD_NC(GPP_I8, NONE),
+	PAD_CFG_GPO(GPP_I9, 1, DEEP), // M2_SSD2_RST#
+	PAD_NC(GPP_I10, NONE),
+	PAD_CFG_GPI(GPP_I11, NONE, PLTRST), // USB_OC4#
+	PAD_CFG_GPI(GPP_I12, NONE, PLTRST), // USB_OC5#
+	PAD_CFG_GPI(GPP_I13, NONE, PLTRST), // USB_OC6#
+	PAD_CFG_GPI(GPP_I14, NONE, PLTRST), // USB_OC7#
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_CFG_GPI(GPP_J8, NONE, PLTRST), // GPIO4_GC6_NVDD_EN_R
+	PAD_NC(GPP_J9, NONE),
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_GPO(GPP_K0, 0, DEEP), // DGPU_OVRM
+	PAD_NC(GPP_K1, NONE),
+	PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R
+	PAD_NC(GPP_K3, NONE),
+	PAD_NC(GPP_K4, NONE),
+	PAD_NC(GPP_K5, NONE),
+	PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1), // EDP_HPD
+	PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1
+	_PAD_CFG_STRUCT(GPP_K10, 0x46880100, 0x0000), // DGPU_MDP_HPD
+	PAD_CFG_GPI(GPP_K11, DN_20K, DEEP), // GC6_FB_EN_PCH
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE), // 100k pull-down
+	PAD_NC(GPP_R8, NONE),
+	PAD_NC(GPP_R9, NONE),
+	PAD_NC(GPP_R10, NONE),
+	PAD_NC(GPP_R11, NONE),
+	PAD_CFG_GPI_INT(GPP_R12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_NC(GPP_R13, NONE),
+	PAD_NC(GPP_R14, NONE),
+	PAD_NC(GPP_R15, NONE),
+	PAD_NC(GPP_R16, NONE),
+	PAD_NC(GPP_R17, NONE),
+	PAD_NC(GPP_R18, NONE),
+	PAD_NC(GPP_R19, NONE),
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE),
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_CFG_GPI(GPP_S6, NONE, DEEP), // DMIC_CLK_PCH
+	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // DMIC_DAT_PCH
+};
+
+void variant_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c
new file mode 100644
index 000000000000..8c97e7f45eab
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
+};
+
+void variant_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c
new file mode 100644
index 000000000000..35c27a150f70
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/hda_verb.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x15585017, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15585017),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {
+	// Adjust mic coefficient
+	0x02050007,
+	0x02040202,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
new file mode 100644
index 000000000000..32f0805ac0df
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/overridetree.cb
@@ -0,0 +1,75 @@
+chip soc/intel/tigerlake
+	device domain 0 on
+		subsystemid 0x1558 0x5015 inherit
+
+		device ref peg1 on
+			# PCIe PEG2 (remapped to PEG1 by FSP) x8, Clock 0 (DGPU)
+			register "PcieClkSrcUsage[0]" = "0x42"
+			register "PcieClkSrcClkReq[0]" = "0"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				register "enable_delay_ms" = "16"
+				register "enable_off_delay_ms" = "4"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "4"
+				register "srcclk_pin" = "0" # GFX_CLKREQ0#
+				device generic 0 on end
+			end
+		end
+		device ref peg0 on
+			# PCIe PEG0 x4, Clock 4 (SSD2)
+			register "PcieClkSrcUsage[4]" = "0x40"
+			register "PcieClkSrcClkReq[4]" = "4"
+		end
+		device ref south_xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Right)
+			register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
+			register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
+			register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left)
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right)
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Right)
+			register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
+		end
+		device ref sata on
+			register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
+			register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A)
+		end
+		device ref pcie_rp5 on
+			# PCIe root port #5 x1, Clock 5 (GLAN)
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			register "PcieClkSrcUsage[5]" = "4"
+			register "PcieClkSrcClkReq[5]" = "5"
+		end
+		device ref pcie_rp7 on
+			# PCIe root port #7 x1, Clock 7 (CARD)
+			register "PcieRpEnable[6]" = "1"
+			register "PcieRpLtrEnable[6]" = "1"
+			register "PcieClkSrcUsage[7]" = "6"
+			register "PcieClkSrcClkReq[7]" = "7"
+		end
+		device ref pcie_rp8 on
+			# PCIe root port #8 x1, Clock 8 (WLAN)
+			register "PcieRpEnable[7]" = "1"
+			register "PcieRpLtrEnable[7]" = "1"
+			register "PcieClkSrcUsage[8]" = "7"
+			register "PcieClkSrcClkReq[8]" = "8"
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
+		device ref pcie_rp9 on
+			# PCIe root port #9 x4, Clock 9 (SSD1)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[9]" = "8"
+			register "PcieClkSrcClkReq[9]" = "9"
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
+	end
+end
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
new file mode 100644
index 000000000000..9d985630d0f8
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/ramstage.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	params->PchLegacyIoLowLatency = 1;
+
+	// PEG0 Config
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// PEG2 Config
+	params->CpuPcieRpAdvancedErrorReporting[2] = 0;
+	params->CpuPcieRpLtrEnable[2] = 1;
+	params->CpuPcieRpPtmEnabled[2] = 0;
+
+	// Remap PEG2 as PEG1
+	params->CpuPcieRpFunctionSwap = 1;
+}
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3050/romstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3050/romstage.c
new file mode 100644
index 000000000000..f28c0c23d36c
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3050/romstage.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variant/romstage.h>
+
+void variant_memory_init_params(FSPM_UPD *mupd)
+{
+	// Enable M.2 PCIE 4.0 and PEG2
+	mupd->FspmConfig.CpuPcieRpEnableMask = 0x5;
+}
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/board_info.txt b/src/mainboard/system76/tgl-h/variants/gaze16-3060/board_info.txt
new file mode 100644
index 000000000000..6555d4d96054
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/board_info.txt
@@ -0,0 +1,2 @@
+Board name: gaze16
+Release year: 2021
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/data.vbt b/src/mainboard/system76/tgl-h/variants/gaze16-3060/data.vbt
new file mode 100644
index 000000000000..2531c7aed7a1
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/data.vbt
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio.c
new file mode 100644
index 000000000000..ac14b64bf30d
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio.c
@@ -0,0 +1,281 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Group GPD ------- */
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
+	PAD_CFG_GPI(GPD2, NATIVE, PWROK), // LAN_WAKEUP#
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
+	PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
+	PAD_NC(GPD9, NONE), // SLP_WLAN# (test point)
+	PAD_NC(GPD10, NONE), // SLP_S5# (test point)
+	PAD_CFG_GPI(GPD11, NONE, PWROK), // LAN_DISABLE#
+	PAD_NC(GPD12, NONE),
+
+	/* ------- GPIO Group GPP_A ------- */
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS#
+	PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N
+	PAD_NC(GPP_A7, NONE),
+	PAD_NC(GPP_A8, NONE),
+	PAD_NC(GPP_A9, NONE),
+	PAD_CFG_GPI(GPP_A10, UP_20K, DEEP), // ESPI_ALRT#
+	_PAD_CFG_STRUCT(GPP_A11, 0x80100100, 0x0000), // INTP_OUT
+	PAD_NC(GPP_A12, NONE),
+	PAD_NC(GPP_A13, NONE),
+	PAD_NC(GPP_A14, NONE),
+
+	/* ------- GPIO Group GPP_B ------- */
+	_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x0000), // TPM_PIRQ#
+	PAD_NC(GPP_B1, NONE),
+	PAD_CFG_GPI(GPP_B2, NONE, DEEP), // VRALERT#_PD
+	PAD_CFG_GPO(GPP_B3, 1, DEEP), // BT_EN
+	PAD_NC(GPP_B4, NONE), // 10k pull-up
+	PAD_NC(GPP_B5, NONE),
+	PAD_NC(GPP_B6, NONE),
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // WLAN_CLKREQ#
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // CARD_CLKREQ#
+	PAD_NC(GPP_B9, NONE),
+	PAD_NC(GPP_B10, NONE),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
+	PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR
+	PAD_CFG_GPO(GPP_B15, 1, DEEP), // SATA_M2_PWR_EN1
+	PAD_NC(GPP_B16, NONE),
+	PAD_NC(GPP_B17, NONE),
+	PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
+	PAD_NC(GPP_B19, NONE),
+	PAD_NC(GPP_B20, NONE),
+	PAD_NC(GPP_B21, NONE),
+	PAD_CFG_GPI(GPP_B22, NONE, DEEP), // BOOT strap
+	PAD_CFG_GPI(GPP_B23, NONE, DEEP), // CPUNSSC clock
+
+	/* ------- GPIO Group GPP_C ------- */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DAT
+	PAD_CFG_GPI(GPP_C2, NONE, DEEP), // SKIN_THRM_SNSR_ALERT_N
+	PAD_NC(GPP_C3, NONE),
+	PAD_NC(GPP_C4, NONE),
+	PAD_CFG_NF(GPP_C5, NONE, DEEP, NF1), // eSPI/LPC select strap
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
+	PAD_CFG_GPI(GPP_C9, NONE, DEEP), // BOARD_ID1
+	PAD_CFG_GPI(GPP_C10, NONE, DEEP), // BOARD_ID2
+	PAD_CFG_GPI(GPP_C11, NONE, DEEP), // BOARD_ID3
+	PAD_CFG_GPI(GPP_C12, NONE, DEEP), // PERKB_ID2#_R
+	PAD_CFG_GPI(GPP_C13, NONE, DEEP), // PERKB_ID1#_R
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
+	PAD_CFG_GPI(GPP_C18, NONE, DEEP), // SCI#
+	PAD_CFG_GPI(GPP_C19, NONE, DEEP), // SWI#
+	//PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	//PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_NC(GPP_C22, NONE),
+	PAD_CFG_GPI(GPP_C23, NONE, DEEP), // SMI#
+
+	/* ------- GPIO Group GPP_D ------- */
+	PAD_NC(GPP_D0, NONE),
+	PAD_NC(GPP_D1, NONE),
+	PAD_NC(GPP_D2, NONE),
+	PAD_NC(GPP_D3, NONE),
+	PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), // SML1CLK
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF2), // CNVI_RF_RST#
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF3), // CNVI_CLKREQ
+	PAD_NC(GPP_D7, NONE),
+	PAD_NC(GPP_D8, NONE),
+	PAD_CFG_NF(GPP_D9, NONE, DEEP, NF1), // SML0_DATA
+	PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), // SML0_CLK
+	PAD_NC(GPP_D11, NONE),
+	PAD_NC(GPP_D12, NONE),
+	PAD_NC(GPP_D13, NONE),
+	PAD_NC(GPP_D14, NONE),
+	PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), // SML1DATA
+	PAD_NC(GPP_D16, NONE),
+	PAD_NC(GPP_D17, NONE),
+	PAD_NC(GPP_D18, NONE),
+	PAD_NC(GPP_D19, NONE),
+	PAD_NC(GPP_D20, NONE),
+	PAD_NC(GPP_D21, NONE),
+	PAD_NC(GPP_D22, NONE),
+	PAD_CFG_GPO(GPP_D23, 1, DEEP), // GPU_EVENT#
+
+	/* ------- GPIO Group GPP_E ------- */
+	PAD_NC(GPP_E0, NONE),
+	PAD_CFG_NF(GPP_E1, UP_20K, DEEP, NF1), // SATAGP1
+	PAD_NC(GPP_E2, NONE),
+	PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI#
+	PAD_CFG_NF(GPP_E4, NONE, PWROK, NF1), // DEVSLP0
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), // DEVSLP1
+	PAD_NC(GPP_E6, NONE),
+	PAD_NC(GPP_E7, NONE),
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
+	PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
+	PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
+	PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3#
+
+	/* ------- GPIO Group GPP_F ------- */
+	PAD_NC(GPP_F0, NONE),
+	PAD_NC(GPP_F1, NONE),
+	PAD_CFG_GPO(GPP_F2, 1, PLTRST), // GPIO_LANRTD3
+	PAD_CFG_GPO(GPP_F3, 1, DEEP), // LAN_PLT_RST#
+	PAD_CFG_GPO(GPP_F4, 1, DEEP), // SATA_PWR_EN
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // 1P05_CTRL
+	PAD_NC(GPP_F6, NONE),
+	PAD_CFG_GPI(GPP_F7, NONE, DEEP), // GPIO4_GC6_NVDD_EN_R
+	//PAD_CFG_GPO(GPP_F8, 1, DEEP), // DGPU_RST#_PCH
+	//PAD_CFG_GPO(GPP_F9, 1, DEEP), // DGPU_PWR_EN
+	PAD_CFG_GPI(GPP_F10, NONE, DEEP), // BIOS_REC
+	PAD_CFG_GPI(GPP_F11, NONE, DEEP), // PCH_RSVD
+	PAD_CFG_GPI(GPP_F12, NONE, DEEP), // WLAN_EN
+	PAD_CFG_GPI(GPP_F13, NONE, DEEP), // GP39_GFX_CRB_DETECT
+	PAD_NC(GPP_F14, NONE),
+	PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
+	PAD_NC(GPP_F16, NONE),
+	PAD_CFG_GPO(GPP_F17, 1, DEEP), // SB_BLON
+	PAD_NC(GPP_F18, NONE),
+	//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
+	PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
+	PAD_NC(GPP_F22, NONE), // VNN_CTRL
+	PAD_NC(GPP_F23, NONE),
+
+	/* ------- GPIO Group GPP_G ------- */
+	PAD_NC(GPP_G0, NONE),
+	PAD_CFG_GPI(GPP_G1, NONE, DEEP), // CNVI_DET#
+	PAD_NC(GPP_G2, NONE),
+	PAD_NC(GPP_G3, NONE),
+	PAD_NC(GPP_G4, NONE),
+	PAD_NC(GPP_G5, NONE),
+	PAD_NC(GPP_G6, NONE),
+	PAD_NC(GPP_G7, NONE),
+	PAD_NC(GPP_G8, NONE),
+	PAD_CFG_GPI(GPP_G9, NONE, DEEP), // GPP_G9
+	PAD_NC(GPP_G10, NONE),
+	PAD_CFG_GPI(GPP_G11, NONE, DEEP), // GPP_G11
+	PAD_NC(GPP_G12, NATIVE),
+	PAD_CFG_GPI(GPP_G13, NONE, DEEP), // GPP_G13
+	PAD_NC(GPP_G14, NONE),
+	PAD_NC(GPP_G15, NONE),
+
+	/* ------- GPIO Group GPP_H ------- */
+	PAD_NC(GPP_H0, NONE),
+	PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), // SDD_CLKREQ#
+	PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), // LAN_CLKREQ#
+	PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), // PEG_CLKREQ#
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SDD2_CLKREQ#
+	PAD_NC(GPP_H5, NONE),
+	PAD_CFG_GPI(GPP_H6, NONE, DEEP), // SB_KBCRST#
+	PAD_NC(GPP_H7, NONE),
+	PAD_NC(GPP_H8, NONE),
+	PAD_NC(GPP_H9, NONE),
+	PAD_NC(GPP_H10, NONE),
+	PAD_NC(GPP_H11, NONE),
+	PAD_NC(GPP_H12, NONE),
+	PAD_NC(GPP_H13, NONE),
+	PAD_NC(GPP_H14, NONE),
+	PAD_NC(GPP_H15, NONE),
+	PAD_NC(GPP_H16, NONE),
+	PAD_CFG_GPO(GPP_H17, 1, DEEP), // SATA_M2_PWR_EN2
+	PAD_NC(GPP_H18, NONE),
+	PAD_NC(GPP_H19, NONE), // GSYNC_DET
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_CFG_GPO(GPP_H23, 1, DEEP), // GPP_H23_SDD_RST#
+
+	/* ------- GPIO Group GPP_I ------- */
+	PAD_NC(GPP_I0, NONE),
+	_PAD_CFG_STRUCT(GPP_I1, 0x46880100, 0x0000), // MDP_E_HPD_PCH
+	_PAD_CFG_STRUCT(GPP_I2, 0x46880100, 0x0000), // DP_F_HPD
+	PAD_NC(GPP_I3, NONE),
+	PAD_NC(GPP_I4, NONE),
+	PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), // HDMI_CTRLCLK
+	PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), // HDMI_CTRLDATA
+	PAD_NC(GPP_I7, NONE),
+	PAD_NC(GPP_I8, NONE),
+	PAD_CFG_GPO(GPP_I9, 1, DEEP), // GGPP_I9_SDD2_RST#
+	PAD_CFG_TERM_GPO(GPP_I10, 0, DN_20K, DEEP), // GPP_I10_TEST_R
+	PAD_CFG_NF(GPP_I11, NONE, DEEP, NF2), // SMD_7411
+	PAD_CFG_NF(GPP_I12, NONE, DEEP, NF2), // SMC_7411
+	PAD_CFG_GPI(GPP_I13, NONE, PLTRST), // USB_OC6#
+	PAD_CFG_GPI(GPP_I14, NONE, PLTRST), // USB_OC7#
+
+	/* ------- GPIO Group GPP_J ------- */
+	PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
+	PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE#
+	PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT / crystal select
+	PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
+	PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT / M.2 CNVi strap
+	PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
+	PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
+	PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
+	PAD_CFG_GPI(GPP_J8, NONE, PLTRST), // GPIO4_GC6_NVDD_EN_R
+	PAD_NC(GPP_J9, NONE),
+
+	/* ------- GPIO Group GPP_K ------- */
+	PAD_CFG_GPO(GPP_K0, 0, DEEP), // DGPU_OVRM
+	PAD_NC(GPP_K1, NONE),
+	PAD_CFG_GPI(GPP_K2, NONE, DEEP), // DGPU_PWRGD_R
+	PAD_NC(GPP_K3, NONE),
+	PAD_NC(GPP_K4, NONE),
+	PAD_NC(GPP_K5, NONE),
+	PAD_CFG_NF(GPP_K6, NONE, DEEP, NF1), // EDP_HPD
+	PAD_CFG_NF(GPP_K7, NONE, DEEP, NF1), // HDMI_HPD
+	PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // CORE_VID0
+	PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // CORE_VID1
+	PAD_NC(GPP_K10, NONE),
+	PAD_CFG_GPI(GPP_K11, NONE, PLTRST), // GC6_FB_EN_PCH
+
+	/* ------- GPIO Group GPP_R ------- */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
+	PAD_NC(GPP_R5, NONE),
+	PAD_NC(GPP_R6, NONE),
+	PAD_NC(GPP_R7, NONE),
+	PAD_NC(GPP_R8, NONE),
+	PAD_NC(GPP_R9, NONE),
+	PAD_NC(GPP_R10, NONE),
+	PAD_NC(GPP_R11, NONE),
+	PAD_CFG_GPI_INT(GPP_R12, NONE, PLTRST, LEVEL), // TP_ATTN#
+	PAD_NC(GPP_R13, NONE),
+	PAD_NC(GPP_R14, NONE),
+	PAD_NC(GPP_R15, NONE),
+	PAD_NC(GPP_R16, NONE),
+	PAD_NC(GPP_R17, NONE),
+	PAD_NC(GPP_R18, NONE),
+	PAD_NC(GPP_R19, NONE),
+
+	/* ------- GPIO Group GPP_S ------- */
+	PAD_NC(GPP_S0, NONE),
+	PAD_NC(GPP_S1, NONE),
+	PAD_NC(GPP_S2, NONE),
+	PAD_NC(GPP_S3, NONE), // 100k pull-down
+	PAD_NC(GPP_S4, NONE),
+	PAD_NC(GPP_S5, NONE),
+	PAD_CFG_GPI(GPP_S6, NONE, DEEP), // MIC_CLK_PCH
+	PAD_CFG_GPI(GPP_S7, NONE, DEEP), // MIC_DATA_PCH
+};
+
+void variant_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio_early.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio_early.c
new file mode 100644
index 000000000000..8c97e7f45eab
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/gpio_early.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
+	PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
+	PAD_CFG_GPO(GPP_F8, 0, DEEP), // DGPU_RST#_PCH
+	PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
+};
+
+void variant_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c
new file mode 100644
index 000000000000..491e32b2b170
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x155850e2, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x155850e2),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41789c6d),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
new file mode 100644
index 000000000000..881b2c5caf77
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/overridetree.cb
@@ -0,0 +1,76 @@
+chip soc/intel/tigerlake
+	device domain 0 on
+		subsystemid 0x1558 0x50e1 inherit
+
+		device ref peg1 on
+			# PCIe PEG1 x16, Clock 9 (DGPU)
+			register "PcieClkSrcUsage[9]" = "0x41"
+			register "PcieClkSrcClkReq[9]" = "9"
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # DGPU_PWR_EN
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F8)" # DGPU_RST#_PCH
+				register "enable_delay_ms" = "16"
+				register "enable_off_delay_ms" = "4"
+				register "reset_delay_ms" = "10"
+				register "reset_off_delay_ms" = "4"
+				register "srcclk_pin" = "9" # PEG_CLKREQ#
+				device generic 0 on end
+			end
+		end
+		device ref peg0 on
+			# PCIe PEG0 x4, Clock 7 (SSD1)
+			register "PcieClkSrcUsage[7]" = "0x40"
+			register "PcieClkSrcClkReq[7]" = "7"
+		end
+		device ref south_xhci on
+			# USB2
+			register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 2 (Right)
+			register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.2 Gen 1 (Left)
+			register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back)
+			register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2.0 (Left)
+			register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
+			register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key
+			register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
+			register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+			# USB3
+			register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 (Right)
+			register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 1 (Left)
+			register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.2 Gen 2 Type C (Back)
+		end
+		device ref sata on
+			register "SataPortsEnable[0]" = "1" # HDD (SATA0B)
+			register "SataPortsEnable[1]" = "1" # SSD2 (SATA1A)
+		end
+		device ref pcie_rp5 on
+			# PCIe root port #5 x1, Clock 8 (GLAN)
+			register "PcieRpEnable[4]" = "1"
+			register "PcieRpLtrEnable[4]" = "1"
+			#register "PcieClkSrcUsage[8]" = "4"
+			register "PcieClkSrcClkReq[8]" = "8"
+		end
+		device ref pcie_rp7 on
+			# PCIe root port #7 x1, Clock 3 (CARD)
+			register "PcieRpEnable[6]" = "1"
+			register "PcieRpLtrEnable[6]" = "1"
+			register "PcieClkSrcUsage[3]" = "6"
+			register "PcieClkSrcClkReq[3]" = "3"
+		end
+		device ref pcie_rp8 on
+			# PCIe root port #8 x1, Clock 2 (WLAN)
+			register "PcieRpEnable[7]" = "1"
+			register "PcieRpLtrEnable[7]" = "1"
+			register "PcieClkSrcUsage[2]" = "7"
+			register "PcieClkSrcClkReq[2]" = "2"
+			register "PcieRpSlotImplemented[7]" = "1"
+		end
+		device ref pcie_rp9 on
+			# PCIe root port #9 x4, Clock 10 (SSD2)
+			register "PcieRpEnable[8]" = "1"
+			register "PcieRpLtrEnable[8]" = "1"
+			register "PcieClkSrcUsage[10]" = "8"
+			register "PcieClkSrcClkReq[10]" = "10"
+			register "PcieRpSlotImplemented[8]" = "1"
+		end
+		device ref gbe on end
+	end
+end
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
new file mode 100644
index 000000000000..0f83461ae402
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/ramstage.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+	params->PchLegacyIoLowLatency = 1;
+
+	// PEG0 Config
+	params->CpuPcieRpAdvancedErrorReporting[0] = 0;
+	params->CpuPcieRpLtrEnable[0] = 1;
+	params->CpuPcieRpPtmEnabled[0] = 0;
+
+	// PEG1 Config
+	params->CpuPcieRpAdvancedErrorReporting[1] = 0;
+	params->CpuPcieRpLtrEnable[1] = 1;
+	params->CpuPcieRpPtmEnabled[1] = 0;
+}
diff --git a/src/mainboard/system76/tgl-h/variants/gaze16-3060/romstage.c b/src/mainboard/system76/tgl-h/variants/gaze16-3060/romstage.c
new file mode 100644
index 000000000000..ed8397caf86c
--- /dev/null
+++ b/src/mainboard/system76/tgl-h/variants/gaze16-3060/romstage.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/pch.h>
+#include <variant/romstage.h>
+
+void variant_memory_init_params(FSPM_UPD *mupd)
+{
+	// Enable M.2 PCIE 4.0 and PEG1
+	mupd->FspmConfig.CpuPcieRpEnableMask = 0x3;
+
+	// B variant uses Intel GbE
+	if (CONFIG(BOARD_SYSTEM76_GAZE16_3060_B))
+		mupd->FspmConfig.PcieClkSrcUsage[8] = PCIE_CLK_LAN;
+	else
+		mupd->FspmConfig.PcieClkSrcUsage[8] = 4;
+}