diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-13 19:36:53 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-04-14 18:46:23 +0000 |
| commit | bbb8c042e4ee01cf55d9e19ecedc1bb0d65bf4b7 (patch) | |
| tree | 9c9ef019d083d6bf258e6142f5853a01c62947ca /src/soc/amd/picasso/include/soc/southbridge.h | |
| parent | 43cd1c0bbedd852a9d5e53a32c75826e8bdcc8b2 (diff) | |
| download | coreboot-bbb8c042e4ee01cf55d9e19ecedc1bb0d65bf4b7.tar.gz coreboot-bbb8c042e4ee01cf55d9e19ecedc1bb0d65bf4b7.tar.bz2 coreboot-bbb8c042e4ee01cf55d9e19ecedc1bb0d65bf4b7.zip | |
soc/amd/piasso/fch: use common pm_set_power_failure_state functionality
The functionality to restore the previous power state after power was
lost that could previously be enabled by selecting
MAINBOARD_POWER_RESTORE in the mainboard's Kconfig can now be achieved
by selecting POWER_STATE_PREVIOUS_AFTER_FAILURE in the mainboard's
Kconfig instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab9578ebea89651dc2389bf6ca93ca3f3507eb47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/amd/picasso/include/soc/southbridge.h')
| -rw-r--r-- | src/soc/amd/picasso/include/soc/southbridge.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index ede210852c48..e2a069baff76 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -32,10 +32,6 @@ #define PM_SERIRQ_MODE BIT(6) #define PM_SERIRQ_ENABLE BIT(7) -#define PM_RTC_SHADOW 0x5b /* state when power resumes */ -#define PM_S5_AT_POWER_RECOVERY 0x04 /* S5 */ -#define PM_RESTORE_S0_IF_PREV_S0 0x07 /* S0 if previously at S0 */ - #define PM_EVT_BLK 0x60 #define WAK_STS BIT(15) /*AcpiPmEvtBlkx00 Pm1Status */ #define PCIEXPWAK_STS BIT(14) |