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-rw-r--r--src/northbridge/intel/gm45/Kconfig1
-rw-r--r--src/northbridge/intel/gm45/Makefile.inc1
-rw-r--r--src/northbridge/intel/gm45/acpi.c1
-rw-r--r--src/northbridge/intel/gm45/acpi/gm45.asl1
-rw-r--r--src/northbridge/intel/gm45/acpi/hostbridge.asl1
-rw-r--r--src/northbridge/intel/gm45/acpi/peg.asl1
-rw-r--r--src/northbridge/intel/gm45/bootblock.c1
-rw-r--r--src/northbridge/intel/gm45/chip.h1
-rw-r--r--src/northbridge/intel/gm45/early_init.c1
-rw-r--r--src/northbridge/intel/gm45/early_reset.c1
-rw-r--r--src/northbridge/intel/gm45/gm45.h1
-rw-r--r--src/northbridge/intel/gm45/gma.c1
-rw-r--r--src/northbridge/intel/gm45/igd.c1
-rw-r--r--src/northbridge/intel/gm45/iommu.c1
-rw-r--r--src/northbridge/intel/gm45/memmap.c1
-rw-r--r--src/northbridge/intel/gm45/northbridge.c1
-rw-r--r--src/northbridge/intel/gm45/pcie.c1
-rw-r--r--src/northbridge/intel/gm45/pm.c1
-rw-r--r--src/northbridge/intel/gm45/raminit.c1
-rw-r--r--src/northbridge/intel/gm45/raminit_rcomp_calibration.c1
-rw-r--r--src/northbridge/intel/gm45/raminit_read_write_training.c1
-rw-r--r--src/northbridge/intel/gm45/raminit_receive_enable_calibration.c1
-rw-r--r--src/northbridge/intel/gm45/romstage.c1
-rw-r--r--src/northbridge/intel/gm45/thermal.c1
24 files changed, 0 insertions, 24 deletions
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 7edea51dfd90..f5d67123862a 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -1,4 +1,3 @@
-# This file is part of the coreboot project.
# SPDX-License-Identifier: GPL-2.0-only
config NORTHBRIDGE_INTEL_GM45
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index 9228a1f4e2d0..17e510822a34 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -1,5 +1,4 @@
#
-# This file is part of the coreboot project.
#
#
# SPDX-License-Identifier: GPL-2.0-only
diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c
index c81d21f0d0fd..7a5d0b1ce5dc 100644
--- a/src/northbridge/intel/gm45/acpi.c
+++ b/src/northbridge/intel/gm45/acpi.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <types.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index 270ad90c3284..7d64200ddbf9 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include "hostbridge.asl"
#include "../gm45.h"
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl
index d09d44dfb04f..bafedff2c836 100644
--- a/src/northbridge/intel/gm45/acpi/hostbridge.asl
+++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <arch/ioapic.h>
diff --git a/src/northbridge/intel/gm45/acpi/peg.asl b/src/northbridge/intel/gm45/acpi/peg.asl
index 7dc67183b2bf..f85a22c08be0 100644
--- a/src/northbridge/intel/gm45/acpi/peg.asl
+++ b/src/northbridge/intel/gm45/acpi/peg.asl
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
Device (PEGP)
{
diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index b10a75d454b6..e74354ebdba7 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <arch/bootblock.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/gm45/chip.h b/src/northbridge/intel/gm45/chip.h
index a8a549d72ef7..0d09bb40efc9 100644
--- a/src/northbridge/intel/gm45/chip.h
+++ b/src/northbridge/intel/gm45/chip.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H
#define NORTHBRIDGE_INTEL_GM45_CHIP_H
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 712932aad5da..1be351890be6 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <device/pci_ops.h>
diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index eff89bfd3d9c..44917465d61d 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <types.h>
#include <cf9_reset.h>
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 423a8f25eb5a..d9cfbf709068 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__
#define __NORTHBRIDGE_INTEL_GM45_GM45_H__
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 8a38bdf4ead7..0c97b64b39b6 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <device/mmio.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/gm45/igd.c b/src/northbridge/intel/gm45/igd.c
index 173af1bc5c0e..10a6f84875d0 100644
--- a/src/northbridge/intel/gm45/igd.c
+++ b/src/northbridge/intel/gm45/igd.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <stddef.h>
diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c
index 4d88e3609d2c..422655409a25 100644
--- a/src/northbridge/intel/gm45/iommu.c
+++ b/src/northbridge/intel/gm45/iommu.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <string.h>
diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c
index 0d03731d47c4..4fe3998beebf 100644
--- a/src/northbridge/intel/gm45/memmap.c
+++ b/src/northbridge/intel/gm45/memmap.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
// Use simple device model for this file even in ramstage
#define __SIMPLE_DEVICE__
diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index d566120827ff..cd64dfe3ddb2 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <cbmem.h>
#include <console/console.h>
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 0337c55e5817..2cab42f4bbe5 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <stddef.h>
diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c
index 5e03a3ca1214..6033c0aca2c4 100644
--- a/src/northbridge/intel/gm45/pm.c
+++ b/src/northbridge/intel/gm45/pm.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <stddef.h>
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index e6582ad53c81..fbf9f01cfa02 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <commonlib/helpers.h>
#include <stdint.h>
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
index ee6544b9d245..94da2dc5892e 100644
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <delay.h>
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index 38a48d96d324..e8d719fca688 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <device/mmio.h>
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index c6c092ba2a94..6d95b3401b1a 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <device/mmio.h>
diff --git a/src/northbridge/intel/gm45/romstage.c b/src/northbridge/intel/gm45/romstage.c
index 9bfb4e99bb6b..f7998c926a65 100644
--- a/src/northbridge/intel/gm45/romstage.c
+++ b/src/northbridge/intel/gm45/romstage.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <cbmem.h>
#include <romstage_handoff.h>
diff --git a/src/northbridge/intel/gm45/thermal.c b/src/northbridge/intel/gm45/thermal.c
index 73164946ad03..ed1ec959bddb 100644
--- a/src/northbridge/intel/gm45/thermal.c
+++ b/src/northbridge/intel/gm45/thermal.c
@@ -1,5 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
#include <stdint.h>
#include <stddef.h>