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* soc/intel/jasperlake: Send End-of-Post message to CSETim Wawrzynczak2021-06-302-5/+6
| | | | | | | | | | | | | This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#619830. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I36fe448ff279ba054ad5e79e71c995dc915db21e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55633 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/tigerlake: Send End-of-Post message to CSETim Wawrzynczak2021-06-302-6/+7
| | | | | | | | | | | | This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#612229 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Iae6b2eac11c065749e57c5337d81ed20044fc903 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/alderlake: Send End-of-Post message to CSETim Wawrzynczak2021-06-302-1/+16
| | | | | | | | | | | | | | | This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#627331. TEST=on brya, autotest firmware_CheckEOPState confirms ME is in post-boot state Change-Id: Iee8c29f81d5d04852ae3f16dc8a9ff0fa59f056a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* soc/intel/common/block/cse: Add BWG error recovery to EOP failureTim Wawrzynczak2021-06-303-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds functionality to attempt to allow booting in a secure configuration (albeit with potentially reduced functionality) when the CSE EOP message fails in any way. These steps come from the CSME BWG (13.5, 15.0, 16.), and tell the CSE to disable the MEI bus, which disables further communication from the host. This is followed by requesting the PMC to disable the MEI devices. If these steps are successful, then the boot firmware can continue to boot to the OS. Otherwise, die() is called, prefering not to boot over leaving the insecure MEI bus available. BUG=b:191362590 TEST=Set FSP UPD to disable sending EOP; called this function from a BS_PAYLOAD_LOAD, ON_ENTRY entry; observed that with just cse_mei_bus_disable() called, Linux can no longer communicate over MEI: [ 16.198759] mei_me 0000:00:16.0: wait hw ready failed [ 16.204488] mei_me 0000:00:16.0: hw_start failed ret = -62 [ 16.210804] mei_me 0000:00:16.0: H_RST is set = 0x80000031 [ 18.245909] mei_me 0000:00:16.0: wait hw ready failed [ 18.251601] mei_me 0000:00:16.0: hw_start failed ret = -62 [ 18.257785] mei_me 0000:00:16.0: reset: reached maximal consecutive.. [ 18.267622] mei_me 0000:00:16.0: reset failed ret = -19 [ 18.273580] mei_me 0000:00:16.0: link layer initialization failed. [ 18.280521] mei_me 0000:00:16.0: init hw failure. [ 18.285880] mei_me 0000:00:16.0: initialization failed. Calling both error recovery functions causes all of the slot 16 devices to fail to enumerate in the OS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I06abf36a9d9d8a5f2afba6002dd5695dd2107db1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55675 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/variants/gimble: init overridetree for gimbleMark Hsieh2021-06-304-4/+339
| | | | | | | | | | | | | | init overridetree.cb based on the schematic carbine_adl-p_proto_20210618_proto final.pdf BUG=b:191213263 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I3f6875ef438b147436605629445d346a56896a87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/variants/primus: update gpiosCasper Chang2021-06-301-0/+5
| | | | | | | | | | | | set GPP_C3 and GPP_C4 as NC since LAN function removal. BUG=b:190643562 Change-Id: I21214d0a2904ba4347fbbbc74237aca6db22c345 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55933 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Enable PCH GBELean Sheng Tan2021-06-306-3/+72
| | | | | | | | | | | | | | | | | | Enable PCH GBE with following changes: 1. Configure PCH GBE related FSP UPD flags 2. Use EHL own GBE ACPI instead of common code version due to different B:D.F from the usual GBE 3. Add kconfig PMC_EPOC to use the PMC XTAL read function Due to EHL GBE comes with time sensitive networking (TSN) capability integrated, EHL FSP is using 'PchTsn' instead of the usual 'PchLan' naming convention across the board. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common: Refine pmc_get_xtal_freq functionLean Sheng Tan2021-06-302-5/+20
| | | | | | | | | | | | | | | | 1. Remove 'PCH_EPOC_XTAL_FREQ(__epoc)' macro since it only be used in 1 place. 2. Transform macro into more readable C code. 3. Add additional case check to make sure the returned value is defined in the 'pch_pmc_xtal' enum. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If57a99bf8e837a6eb8f225297399b1f5363cfa85 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/common: Move PMC EPOC related code to Intel common codeLean Sheng Tan2021-06-3011-64/+41
| | | | | | | | | | | | | | | | | | Move PMC EPOC related code to intel/common/block because it is generic for most Intel platforms and ADL, TGL & EHL use it. Add a kconfig 'PMC_EPOC' to guard this common EPOC code. The PMC EPOC register indicates which external crystal oscillator is connected to the PCH. This frequency is important for determining the IP clock of internal PCH devices. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib5fd3c4a648964678ee40ed0f60ca10fe7953f56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google: Use EC_HOST_EVENT_NONERob Barnes2021-06-3013-30/+39
| | | | | | | | | | | | | | google_chromeec_get_event returns 0 for no event. Return EC_HOST_EVENT_NONE=0 to improve readability. BUG=b:184074997 TEST=Build and boot guybrush without error Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ec/google: Sync ec_commands.hRob Barnes2021-06-301-13/+173
| | | | | | | | | | | | | | | | | This change syncs the coreboot version of google ec_commands.h with the ec_commands.h from the google ec repository. This is a straight copy except for the the copyright header. BUG=b:184074997 TEST=Build and boot guybrush BRANCH=None Change-Id: I095c3316d720328cb7b8dd1b72ffc108208b14bd Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/dedede/var/storo: Add USB2 PHY parameters for LTE USB2.0Tao Xia2021-06-301-0/+9
| | | | | | | | | | | | | | This change adds fine-tuned USB2 PHY parameters for storo. BUG=191089827 TEST=Built and verified USB2 eye diagram test result Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I38dd8ad59b32f635e641765e0a1bd13651180d23 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* mb/google/dedede/var/storo: Enable Wifi SAR for storoTao Xia2021-06-301-0/+1
| | | | | | | | | | | | | | BUG=b:190027970,b:178175837 BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I7084f9b7be2b66adda2d9d5a83ce5dd9c31d01b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* src: Move `select ARCH_X86` to platformsAngel Pons2021-06-3036-10/+37
| | | | | | | | | | | | To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* soc/amd/common/fsp/dmi.c: Fix Type 17 DMI reportingNikolai Vyssotski2021-06-301-2/+20
| | | | | | | | | | | | | | | With two versions of *speed_mhz_to_reported_mts() we need to call the correct one based on the reported memory type. BUG=b:184124605 TEST="dmidecode --type 17" in OS on Guybrush Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/pci_device.c: Drop redundant guardAngel Pons2021-06-301-2/+0
| | | | | | | | | | | This guard is nested inside an identical guard already. Change-Id: I2b315ee6620865429097041035ad493ddcc51884 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/google/brya: Set GPP_B3 to APIC modeEric Lai2021-06-301-1/+1
| | | | | | | | | | | | | | Set GPP_B3 to APIC mode to avoid PCI IRQ conflict. BUG=b:181555900 TEST=check dmesg there are no IRQ request errors like below. genirq: Flags mismatch irq 27. 00002008 (sx932x_event) vs. 00000080 (idma64.1) Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Idf88fae9e244858445c45e66e26715cebe0c93ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/55777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* vc/mediatek/mt8195: Fix license headersRex-BC Chen2021-06-3041-984/+66
| | | | | | | | | | | | Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If5e72b36242e1aff7ce2609ea6bdbaea53683bd9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/intel/tigerlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-297-168/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows tigerlake boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=b:171580862 TEST=on delbin, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 6 0 0 0 IO-APIC 2-edge timer 1: 0 35 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 601 0 0 IO-APIC 9-fasteoi acpi 14: 1 0 0 0 IO-APIC 14-fasteoi INT34C5:00 20: 0 0 0 516 IO-APIC 20-fasteoi idma64.6, ttyS0 28: 0 395 0 0 IO-APIC 28-fasteoi idma64.0, i2c_design 29: 0 0 1654 0 IO-APIC 29-fasteoi idma64.1, i2c_design 30: 0 0 0 0 IO-APIC 30-fasteoi idma64.2, i2c_design 31: 0 0 0 0 IO-APIC 31-fasteoi idma64.3, i2c_design 32: 0 0 0 0 IO-APIC 32-fasteoi idma64.4, i2c_design 33: 0 0 14469 0 IO-APIC 33-fasteoi idma64.5, i2c_design 35: 0 18494 0 0 IO-APIC 35-edge cr50_spi 36: 95705 0 0 0 IO-APIC 36-fasteoi idma64.7, pxa2xx-spi 37: 0 0 1978 0 IO-APIC 37-fasteoi idma64.8, pxa2xx-spi 51: 1865 0 0 0 IO-APIC 51-fasteoi ELAN9008:00 59: 0 0 422 0 IO-APIC 59-fasteoi ELAN0000:00 116: 0 0 0 23 IO-APIC 116-fasteoi chromeos-ec abbreviated _PRT dump: Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table If (PICM) Package () {0x0002FFFF, 0x00, 0x00, 0x10}, Package () {0x0004FFFF, 0x00, 0x00, 0x11}, Package () {0x0005FFFF, 0x00, 0x00, 0x12}, Package () {0x0006FFFF, 0x00, 0x00, 0x13}, Package () {0x0007FFFF, 0x00, 0x00, 0x14}, Package () {0x0007FFFF, 0x01, 0x00, 0x15}, Package () {0x0007FFFF, 0x02, 0x00, 0x16}, Package () {0x0007FFFF, 0x03, 0x00, 0x17}, Package () {0x000DFFFF, 0x00, 0x00, 0x10}, Package () {0x000DFFFF, 0x01, 0x00, 0x11}, Package () {0x000DFFFF, 0x02, 0x00, 0x12}, Package () {0x0010FFFF, 0x00, 0x00, 0x13}, Package () {0x0010FFFF, 0x01, 0x00, 0x14}, Package () {0x0011FFFF, 0x00, 0x00, 0x18}, Package () {0x0012FFFF, 0x00, 0x00, 0x19}, Package () {0x0012FFFF, 0x01, 0x00, 0x1A}, Package () {0x0013FFFF, 0x00, 0x00, 0x1B}, Package () {0x0014FFFF, 0x00, 0x00, 0x15}, Package () {0x0015FFFF, 0x00, 0x00, 0x1C}, Package () {0x0015FFFF, 0x01, 0x00, 0x1D}, Package () {0x0015FFFF, 0x02, 0x00, 0x1E}, Package () {0x0015FFFF, 0x03, 0x00, 0x1F}, Package () {0x0016FFFF, 0x00, 0x00, 0x16}, Package () {0x0016FFFF, 0x01, 0x00, 0x17}, Package () {0x0016FFFF, 0x02, 0x00, 0x10}, Package () {0x0016FFFF, 0x03, 0x00, 0x11}, Package () {0x0017FFFF, 0x00, 0x00, 0x12}, Package () {0x0019FFFF, 0x00, 0x00, 0x20}, Package () {0x0019FFFF, 0x01, 0x00, 0x21}, Package () {0x0019FFFF, 0x02, 0x00, 0x22}, Package () {0x001CFFFF, 0x00, 0x00, 0x10}, Package () {0x001CFFFF, 0x01, 0x00, 0x11}, Package () {0x001CFFFF, 0x02, 0x00, 0x12}, Package () {0x001CFFFF, 0x03, 0x00, 0x13}, Package () {0x001DFFFF, 0x00, 0x00, 0x10}, Package () {0x001DFFFF, 0x01, 0x00, 0x11}, Package () {0x001DFFFF, 0x02, 0x00, 0x12}, Package () {0x001DFFFF, 0x03, 0x00, 0x13}, Package () {0x001EFFFF, 0x00, 0x00, 0x14}, Package () {0x001EFFFF, 0x01, 0x00, 0x15}, Package () {0x001EFFFF, 0x02, 0x00, 0x24}, Package () {0x001EFFFF, 0x03, 0x00, 0x25}, Package () {0x001FFFFF, 0x01, 0x00, 0x17}, Package () {0x001FFFFF, 0x02, 0x00, 0x14}, Package () {0x001FFFFF, 0x03, 0x00, 0x15}, Package () {0x001FFFFF, 0x00, 0x00, 0x16}, Else Package () {0x0002FFFF, 0x00, 0x00, 0x0B}, Package () {0x0004FFFF, 0x00, 0x00, 0x0A}, Package () {0x0005FFFF, 0x00, 0x00, 0x0B}, Package () {0x0006FFFF, 0x00, 0x00, 0x0B}, Package () {0x0007FFFF, 0x00, 0x00, 0x0B}, Package () {0x0007FFFF, 0x01, 0x00, 0x0B}, Package () {0x0007FFFF, 0x02, 0x00, 0x0B}, Package () {0x0007FFFF, 0x03, 0x00, 0x0B}, Package () {0x000DFFFF, 0x00, 0x00, 0x0B}, Package () {0x000DFFFF, 0x01, 0x00, 0x0A}, Package () {0x000DFFFF, 0x02, 0x00, 0x0B}, Package () {0x0010FFFF, 0x00, 0x00, 0x0B}, Package () {0x0010FFFF, 0x01, 0x00, 0x0B}, Package () {0x0014FFFF, 0x00, 0x00, 0x0B}, Package () {0x0016FFFF, 0x00, 0x00, 0x0B}, Package () {0x0016FFFF, 0x01, 0x00, 0x0B}, Package () {0x0016FFFF, 0x02, 0x00, 0x0B}, Package () {0x0016FFFF, 0x03, 0x00, 0x0A}, Package () {0x0017FFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x01, 0x00, 0x0A}, Package () {0x001CFFFF, 0x02, 0x00, 0x0B}, Package () {0x001CFFFF, 0x03, 0x00, 0x0B}, Package () {0x001DFFFF, 0x00, 0x00, 0x0B}, Package () {0x001DFFFF, 0x01, 0x00, 0x0A}, Package () {0x001DFFFF, 0x02, 0x00, 0x0B}, Package () {0x001DFFFF, 0x03, 0x00, 0x0B}, Package () {0x001EFFFF, 0x00, 0x00, 0x0B}, Package () {0x001EFFFF, 0x01, 0x00, 0x0B}, Package () {0x001FFFFF, 0x01, 0x00, 0x0B}, Package () {0x001FFFFF, 0x02, 0x00, 0x0B}, Package () {0x001FFFFF, 0x03, 0x00, 0x0B}, Package () {0x001FFFFF, 0x00, 0x00, 0x0B}, Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ieb241f2b91af52a7e2d0efe997d35732882ac463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49409 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Enable support for common IRQ blockTim Wawrzynczak2021-06-297-212/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows ADL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=b:176858827 TEST=brya0, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 36 0 0 0 0 0 0 0 IO-APIC 2-edge time 1: 0 0 9 0 0 0 0 0 IO-APIC 1-edge i804 8: 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 21705 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC 18: 0 0 0 0 0 0 0 0 IO-APIC 18-fasteoi inte 20: 0 0 0 0 0 0 0 394 IO-APIC 20-fasteoi idma 23: 2280 0 0 0 0 0 0 0 IO-APIC 23-fasteoi idma 26: 0 0 26 0 0 0 0 0 IO-APIC 26-fasteoi idma 27: 0 0 0 6 0 0 0 0 IO-APIC 27-fasteoi idma 28: 0 0 0 0 0 0 0 0 IO-APIC 28-fasteoi idma 29: 0 0 0 0 25784 0 0 0 IO-APIC 29-fasteoi idma 30: 0 0 0 0 0 0 0 0 IO-APIC 30-fasteoi idma 31: 0 0 0 0 0 0 226 0 IO-APIC 31-fasteoi idma 77: 0 0 0 0 0 2604 0 0 IO-APIC 77-edge cr50 100: 0 0 0 0 0 0 0 0 IO-APIC 100-fasteoi ELAN 103: 0 0 0 0 0 0 0 0 IO-APIC 103-fasteoi chro abbreviated _PRT dump: If (PICM) Package (){0x0002FFFF, 0, 0, 0x10}, Package (){0x0004FFFF, 0, 0, 0x11}, Package (){0x0005FFFF, 0, 0, 0x12}, Package (){0x0006FFFF, 0, 0, 0x13}, Package (){0x0006FFFF, 1, 0, 0x14}, Package (){0x0007FFFF, 0, 0, 0x15}, Package (){0x0007FFFF, 1, 0, 0x16}, Package (){0x0007FFFF, 2, 0, 0x17}, Package (){0x0007FFFF, 3, 0, 0x10}, Package (){0x000DFFFF, 0, 0, 0x11}, Package (){0x0012FFFF, 0, 0, 0x18}, Package (){0x0012FFFF, 1, 0, 0x19}, Package (){0x0014FFFF, 0, 0, 0x12}, Package (){0x0014FFFF, 1, 0, 0x13}, Package (){0x0015FFFF, 0, 0, 0x1A}, Package (){0x0015FFFF, 1, 0, 0x1B}, Package (){0x0015FFFF, 2, 0, 0x1C}, Package (){0x0015FFFF, 3, 0, 0x1D}, Package (){0x0016FFFF, 0, 0, 0x14}, Package (){0x0016FFFF, 1, 0, 0x15}, Package (){0x0016FFFF, 2, 0, 0x16}, Package (){0x0016FFFF, 3, 0, 0x17}, Package (){0x0017FFFF, 0, 0, 0x10}, Package (){0x0019FFFF, 0, 0, 0x1E}, Package (){0x0019FFFF, 1, 0, 0x1F}, Package (){0x0019FFFF, 2, 0, 0x20}, Package (){0x001CFFFF, 0, 0, 0x10}, Package (){0x001CFFFF, 1, 0, 0x11}, Package (){0x001CFFFF, 2, 0, 0x12}, Package (){0x001CFFFF, 3, 0, 0x13}, Package (){0x001DFFFF, 0, 0, 0x10}, Package (){0x001DFFFF, 1, 0, 0x11}, Package (){0x001DFFFF, 2, 0, 0x12}, Package (){0x001DFFFF, 3, 0, 0x13}, Package (){0x001EFFFF, 0, 0, 0x14}, Package (){0x001EFFFF, 1, 0, 0x15}, Package (){0x001EFFFF, 2, 0, 0x16}, Package (){0x001EFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 1, 0, 0x15}, Package (){0x001FFFFF, 2, 0, 0x16}, Package (){0x001FFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 0, 0, 0x14}, Else Package (){0x0002FFFF, 0, 0, 0x0B}, Package (){0x0004FFFF, 0, 0, 0x0A}, Package (){0x0005FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 0, 0, 0x0B}, Package (){0x0007FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 2, 0, 0x0B}, Package (){0x0007FFFF, 3, 0, 0x0B}, Package (){0x000DFFFF, 0, 0, 0x0A}, Package (){0x0014FFFF, 0, 0, 0x0B}, Package (){0x0014FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 0, 0, 0x0B}, Package (){0x0016FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 2, 0, 0x0B}, Package (){0x0016FFFF, 3, 0, 0x0B}, Package (){0x0017FFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 1, 0, 0x0A}, Package (){0x001CFFFF, 2, 0, 0x0B}, Package (){0x001CFFFF, 3, 0, 0x0B}, Package (){0x001DFFFF, 0, 0, 0x0B}, Package (){0x001DFFFF, 1, 0, 0x0A}, Package (){0x001DFFFF, 2, 0, 0x0B}, Package (){0x001DFFFF, 3, 0, 0x0B}, Package (){0x001EFFFF, 0, 0, 0x0B}, Package (){0x001EFFFF, 1, 0, 0x0B}, Package (){0x001EFFFF, 2, 0, 0x0B}, Package (){0x001EFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 1, 0, 0x0B}, Package (){0x001FFFFF, 2, 0, 0x0B}, Package (){0x001FFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 0, 0, 0x0B}, dmesg shows no GSI or PCI errors, TPM & touchpad IRQs still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1e7a708183ac4170b28da9565137fa2f5088a7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/54683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Use new IRQ moduleTim Wawrzynczak2021-06-298-254/+233
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows cannonlake boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. Also prodrive/hermes (intel/cannonlake) was the only user of uart_acpi_write_irq(), therefore use the allocated IRQ instead of the fixed IRQ number in that function to preserve behavior. BUG=b:130217151 TEST=on dratini, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 11 0 0 0 IO-APIC 2-edge timer 1: 0 661 0 0 IO-APIC 1-edge i8042 8: 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 874 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 1 0 IO-APIC 14-fasteoi INT34BB:00 17: 0 10633 0 0 IO-APIC 17-fasteoi mmc1 19: 0 0 0 0 IO-APIC 19-fasteoi mmc0 22: 0 0 0 0 IO-APIC 22-fasteoi i801_smbus 26: 153738 0 0 0 IO-APIC 26-fasteoi idma64.0, i2c_designwar 27: 0 8 0 0 IO-APIC 27-fasteoi idma64.1, i2c_designwar 30: 0 0 227 0 IO-APIC 30-fasteoi i2c_designware.2 33: 0 0 0 0 IO-APIC 33-fasteoi idma64.3 35: 43107 0 0 0 IO-APIC 35-fasteoi idma64.4, pxa2xx-spi.4 36: 0 0 2039 0 IO-APIC 36-fasteoi idma64.5, pxa2xx-spi.5 45: 0 0 9451 0 IO-APIC 45-edge ELAN0000:00 85: 0 0 0 0 IO-APIC 85-fasteoi chromeos-ec 93: 0 7741 0 0 IO-APIC 93-edge cr50_spi abbreviated _PRT dump: If (PICM) Package () {0x0001FFFF, 0x00, 0x00, 0x10}, Package () {0x0001FFFF, 0x01, 0x00, 0x11}, Package () {0x0001FFFF, 0x02, 0x00, 0x12}, Package () {0x0002FFFF, 0x00, 0x00, 0x13}, Package () {0x0004FFFF, 0x00, 0x00, 0x14}, Package () {0x0005FFFF, 0x00, 0x00, 0x15}, Package () {0x0008FFFF, 0x00, 0x00, 0x16}, Package () {0x0012FFFF, 0x01, 0x00, 0x17}, Package () {0x0012FFFF, 0x02, 0x00, 0x10}, Package () {0x0012FFFF, 0x00, 0x00, 0x18}, Package () {0x0013FFFF, 0x00, 0x00, 0x19}, Package () {0x0014FFFF, 0x00, 0x00, 0x11} Package () {0x0014FFFF, 0x01, 0x00, 0x12}, Package () {0x0014FFFF, 0x02, 0x00, 0x13}, Package () {0x0014FFFF, 0x03, 0x00, 0x14}, Package () {0x0015FFFF, 0x00, 0x00, 0x1A}, Package () {0x0015FFFF, 0x01, 0x00, 0x1B}, Package () {0x0015FFFF, 0x02, 0x00, 0x1C}, Package () {0x0015FFFF, 0x03, 0x00, 0x1D}, Package () {0x0016FFFF, 0x00, 0x00, 0x15}, Package () {0x0016FFFF, 0x01, 0x00, 0x16}, Package () {0x0016FFFF, 0x02, 0x00, 0x17}, Package () {0x0016FFFF, 0x03, 0x00, 0x10}, Package () {0x0017FFFF, 0x00, 0x00, 0x11}, Package () {0x0019FFFF, 0x00, 0x00, 0x1E}, Package () {0x0019FFFF, 0x01, 0x00, 0x1F}, Package () {0x0019FFFF, 0x02, 0x00, 0x20}, Package () {0x001AFFFF, 0x00, 0x00, 0x12}, Package () {0x001CFFFF, 0x00, 0x00, 0x10}, Package () {0x001CFFFF, 0x01, 0x00, 0x11}, Package () {0x001CFFFF, 0x02, 0x00, 0x12}, Package () {0x001CFFFF, 0x03, 0x00, 0x13}, Package () {0x001DFFFF, 0x00, 0x00, 0x10}, Package () {0x001DFFFF, 0x01, 0x00, 0x11}, Package () {0x001DFFFF, 0x02, 0x00, 0x12}, Package () {0x001DFFFF, 0x03, 0x00, 0x13}, Package () {0x001EFFFF, 0x00, 0x00, 0x21}, Package () {0x001EFFFF, 0x01, 0x00, 0x22}, Package () {0x001EFFFF, 0x02, 0x00, 0x23}, Package () {0x001EFFFF, 0x03, 0x00, 0x24}, Package () {0x001FFFFF, 0x01, 0x00, 0x15}, Package () {0x001FFFFF, 0x02, 0x00, 0x16}, Package () {0x001FFFFF, 0x03, 0x00, 0x17}, Package () {0x001FFFFF, 0x00, 0x00, 0x14}, Else Package () {0x0001FFFF, 0x00, 0x00, 0x0B}, Package () {0x0001FFFF, 0x01, 0x00, 0x0A}, Package () {0x0001FFFF, 0x02, 0x00, 0x0B}, Package () {0x0002FFFF, 0x00, 0x00, 0x0B}, Package () {0x0004FFFF, 0x00, 0x00, 0x0B}, Package () {0x0005FFFF, 0x00, 0x00, 0x0B}, Package () {0x0008FFFF, 0x00, 0x00, 0x0B}, Package () {0x0012FFFF, 0x01, 0x00, 0x0B}, Package () {0x0012FFFF, 0x02, 0x00, 0x0B}, Package () {0x0014FFFF, 0x00, 0x00, 0x0A}, Package () {0x0014FFFF, 0x01, 0x00, 0x0B}, Package () {0x0014FFFF, 0x02, 0x00, 0x0B}, Package () {0x0014FFFF, 0x03, 0x00, 0x0B}, Package () {0x0016FFFF, 0x00, 0x00, 0x0B}, Package () {0x0016FFFF, 0x01, 0x00, 0x0B}, Package () {0x0016FFFF, 0x02, 0x00, 0x0B}, Package () {0x0016FFFF, 0x03, 0x00, 0x0B}, Package () {0x0017FFFF, 0x00, 0x00, 0x0A}, Package () {0x001AFFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x00, 0x00, 0x0B}, Package () {0x001CFFFF, 0x01, 0x00, 0x0A}, Package () {0x001CFFFF, 0x02, 0x00, 0x0B}, Package () {0x001CFFFF, 0x03, 0x00, 0x0B}, Package () {0x001DFFFF, 0x00, 0x00, 0x0B}, Package () {0x001DFFFF, 0x01, 0x00, 0x0A}, Package () {0x001DFFFF, 0x02, 0x00, 0x0B}, Package () {0x001DFFFF, 0x03, 0x00, 0x0B}, Package () {0x001FFFFF, 0x01, 0x00, 0x0B}, Package () {0x001FFFFF, 0x02, 0x00, 0x0B}, Package () {0x001FFFFF, 0x03, 0x00, 0x0B}, Package () {0x001FFFFF, 0x00, 0x00, 0x0B}, Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I914ac65470635f351d6311dc9b65e8e4d8d8ecfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/55968 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/cannonlake: Add some missing DEVFN macrosTim Wawrzynczak2021-06-291-0/+12
| | | | | | | | | | | BUG=b:130217151 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: If535ad0bdd46d3315493155e64968d305aa34799 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55967 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/irq: Add function to return IRQ for PCI devfnTim Wawrzynczak2021-06-292-1/+19
| | | | | | | | | | | | | The IRQ for a single device may be required elsewhere, therefore provide get_pci_devfn_irq. BUG=b:130217151, b:171580862, b:176858827 Change-Id: Ibebd821767a2698c9e60b09eeeff3bb596359728 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55826 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/irq: Internally cache PCI IRQ resultsTim Wawrzynczak2021-06-292-23/+52
| | | | | | | | | | | | | | The results of the PCI IRQ assignments are used in several places, so it makes for a nicer API to cache the results and provide simpler functions for the SoCs to call. BUG=b:130217151, b:171580862, b:176858827 Change-Id: Id79eae3f2360cd64f66e7f53e1d78a23cfe5e9df Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55825 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/irq: Add function to program north PCI IRQsTim Wawrzynczak2021-06-292-0/+21
| | | | | | | | | | | | | | | | | Because the FSP interface for PCI IRQs only includes the PCH devices, this function is the complement to that, taking the list of irq entries, and programming the PCI_INTERRUPT_LINE registers. BUG=b:130217151, b:171580862, b:176858827 TEST=boot brya with patch train, verify with `lspci -vvv` that for all the north PCI devices, their IRQ was either the one programmed by this function, or an MSI was used. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I81cf7b25f115e41deb25767669b5466b5712b177 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55817 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common/block/irq: Add support for intel_write_pci0_PRTTim Wawrzynczak2021-06-293-0/+54
| | | | | | | | | | | | | Add a new function to fill out the data structures necessary to generate a _PRT table. BUG=b:130217151, b:171580862, b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I21a4835890ca03bff83ed0e8791441b3af54cb62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51159 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/common: Add new IRQ moduleTim Wawrzynczak2021-06-294-0/+402
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel FSP provides a default set of IO-APIC IRQs for PCI devices, if the DevIntConfigPtr UPD is not filled in. However, the FSP has a list of rules that the input IRQ table must conform to: 1) One entry per slot/function 2) Functions using PIRQs must use IOxAPIC IRQs 16-23 3) Single-function devices must use INTA 4) Each slot must have consistent INTx<->PIRQy mappings 5) Some functions have special interrupt pin requirements 6) PCI Express RPs must be assigned in a special way (FIXED_INT_PIN) 7) Some functions require a unique IRQ number 8) PCI functions must avoid sharing an IRQ with a GPIO pad which routes its IRQ through IO-APIC. Since the FSP has no visibility into the actual GPIOs used on the board when GpioOverride is selected, IRQ conflicts can occur between PCI devices and GPIOs. This patch gives SoC code the ability to generate a table of PCI IRQs that will meet the BWG/FSP rules and also not conflict with GPIO IRQs. BUG=b:130217151, b:171580862, b:176858827 TEST=Boot with patch series on volteer, verify IO-APIC IRQs in `/proc/interrupts` match what is expected. No `GSI INT` or `could not derive routing` messages seen in `dmesg` output. Verified TPM, touchpad, touchscreen IRQs all function as expected. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0c22a08ce589fa80d0bb1e637422304a3af2045c Reviewed-on: https://review.coreboot.org/c/coreboot/+/49408 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* southbridge/intel/common: Move invalid PIRQ value to 0Tim Wawrzynczak2021-06-294-19/+30
| | | | | | | | | | | This makes structs that contain an `enum pirq` field that is default-initialized have the value PIRQ_INVALID Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Idb4c7d79de13de0e4b187a42e8bdb27e25e61cc1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55281 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/guybrush: Initialize WWAN for USB if requestedMartin Roth2021-06-292-0/+20
| | | | | | | | | | | | | | | | | | To set the Fibocom 850-GL module to USB mode, it needs to be disabled when PCIe training happens, or it will automatically switch to PCIe mode. This patch makes sure it's shut down when training happens in FSP-M. It will be brought up in ramstage and will be available for USB enumeration later. BUG=b:187316460 TEST=Run lsusb from the OS and see that the Fibocom module is present on USB. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I153eb6cd7c3a0e2cc3b71c99f76db3e565173cfe Reviewed-on: https://review.coreboot.org/c/coreboot/+/54743 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/guybrush: Update romstage power-on timings for PCIeMartin Roth2021-06-297-0/+73
| | | | | | | | | | | | | | | | | | This configures the romstage portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. The PCIe_RST line is anded with the Aux reset lines, so to take the PCIe devices out of reset, both need to be brought hign. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib1990bba31c84827467d4ff8a15f1e0682501e70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54741 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/guybrush: Update bootblock power-on timings for PCIeMartin Roth2021-06-296-23/+145
| | | | | | | | | | | | | | | | | | | | | | This configures the bootblock portion of the PCIe GPIOs in the correct sequence to meet the power-on timings. Setting the PCIE Reset happens in coreboot instead of in the FSP. The Aux reset lines are anded with the PCIe RST line, so both have to be brought up together. On v1 of guybrush, the PCIe reset line also resets EC communication, so it must be brought up immediately on that version. BUG=b:184796302, b:184598323 TEST=Verify timings between GPIO init sections. All available modules are present after training. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I2d0b812b654b0cd317a2c8c1ce554e850c96be44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* Kconfig: Escape variablesPatrick Georgi2021-06-297-12/+12
| | | | | | | | | | | New kconfig parsers interpret $(var) themselves, leading to empty fields. Old kconfig understands \$(var), so use that. Change-Id: I927fc9dc7a66211bfe51d4324cf7c51b555ea3a8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55912 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/herobrine: Add Senor and Piglin variantsShelley Chen2021-06-293-8/+22
| | | | | | | | | | | | | | | | Add configs for Herobrine variants. Also enable ec sw sync as this should not be disabled by default. BUG=b:182963902 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_SENOR -x -a -B ./util/abuild/abuild -p none -t GOOGLE_PIGLIN -x -a -B Change-Id: Ide4e375aa0236dce65a954a2f68455d05fa841eb Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55829 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* mb/google/guybrush: provide full range backlight settings to kernelPratik Vishwakarma2021-06-291-0/+1
| | | | | | | | | | | | | Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide full range backlight settings to the kernel. BUG=b:190443612 Change-Id: If071b701c383e3a6b78bf45a562f5a9b31397835 Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/brya0: Enable MIPI UFCVarshit B Pandya2021-06-291-2/+66
| | | | | | | | | | | | | | | | | | | 1. Add 2 port 2 endpoint 2. Add support for OVTI5675 3. Guard entries in override device tree by FW_CONFIG MIPI UFC is on I2C2 This configuration is as per P2 schematics BUG=b:190674542 TEST=Build and Boot on Brya Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id3ef974994fd0d447e398b365cdf01d78c94cc4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/guybrush: Configure eSPI requirements before setting it upMartin Roth2021-06-281-0/+13
| | | | | | | | | | | | | | | | When initializing eSPI early, guybrush has requirements to configure the bus properly. Those are normally run in bootblock_mainboard_early_init, but when setting up eSPI early, those have not run yet. BUG=192100564 TEST=Build along with previous patch, eSPI works on guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ifec6113d48aea0bb5efe47909e4faf0161148a99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55864 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/cezanne: Add call to mb to configure eSPI requirementsMartin Roth2021-06-283-0/+8
| | | | | | | | | | | | | | | | When initializing espi early, there may be mainboard requirements to configure the bus properly. This allows the mainboard to do that. BUG=192100564 TEST=Build along with next patch, eSPI works on guybrush Change-Id: Icc02877a09b8f8ed20fd1b04f3cee0509f1a85c5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/volteer/var/volet: add G2 touch supportSheng-Liang Pan2021-06-281-0/+15
| | | | | | | | | | | | | | Enable G2 touchscreen support for Volet. BUG=b:185097280 TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I907356448b5d5cbf3974717654ea09cd995962f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55835 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/blipper: Update devicetree and gpio settingZanxi Chen2021-06-282-9/+43
| | | | | | | | | | | | | | | | | | | | | | To reduce power load, set unused GPIOs to NC and close unused interface in devicetree. GPIOs and interfaces are as below: GPIO: GPP_C18/C19/D12/D14/D15/D19/D20/D21/E00/E02/H06/H07 Interface: I2C1/I2C3/I2C5 USB: port2_3/2_4/2_6 BUG=b:185044041 BRANCH=dedede TEST=Built bios and test, it reduces power load without affecting device function. Change-Id: Ib5999f0e129bf3e660fe293eda7af3e8e1426151 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Ben Kao <ben.kao@intel.com>
* mb/google/brya0: Add FW_CONFIG for UFCVarshit B Pandya2021-06-281-0/+4
| | | | | | | | | | | | UFC on brya can be USB or MIPI Add FW_CONFIG bit for this option Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I2f1492d7c769aba8da80763124dda474b32cfbfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya: Update mainboard properties for BB retimer upgradeMaulik V Vaghela2021-06-282-0/+17
| | | | | | | | | | | | | | | | | | This changes updates mainboard properties by adding DFP number and power_gpio for each DFP. Reference CB:54292 BUG=b:186521258 TEST=Updated BB retimer FW from 3.4 to 3.5 without any device connected. Change-Id: I24a02fd446cb66bda9e66e59802b4deea6894273 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
* mb/google/dedede/var/sasukette: Update DPTF parametersTao Xia2021-06-281-4/+4
| | | | | | | | | | | | | | | Update DPTF parameters from internal thermal team. BUG=b:180875580 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I4dbe3947779395903d7999627948d3e97d6cc985 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* src/device/dram: Add terminating new lines to printk stringsNikolai Vyssotski2021-06-282-2/+2
| | | | | | | | | | | BUG=b:184124605 TEST=check serial log Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Change-Id: I521a2541e23d047e255b0cc8068ad63dfaf70bfa Reviewed-on: https://review.coreboot.org/c/coreboot/+/55851 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* mb/google/dedede/var/cret: Add ssfc codec cs42l42 supportDtrain Hsu2021-06-283-1/+46
| | | | | | | | | | | | | Add cs42l42 codec support in cret. BUG=b:188623237, b:189073353 TEST=Build and boot to check functional with cs42l42 EV board. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I2c53291e07fd785c1360c05171eed634788bc665 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55091 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/adlrvp_m: Enable TCSS USB ports device pathBernardo Perez Priego2021-06-281-1/+15
| | | | | | | | | | | | | | This provide a more consistent mechanism to enable corresponding USB TCSS port. BUG=b:182960979 TEST=Boot device, Type C port should operate correctly. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/pirika: Update DPTF parametersAlex1 Kao2021-06-281-0/+42
| | | | | | | | | | | | | | | | Update DPTF parameters from internal thermal team. BUG=b:190518303 BRANCH=None TEST=emerge-dedede coreboot Change-Id: I4005047e0c5f39a12c161a92fbd0afaaec1dc976 Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
* security/intel/cbnt: Fix loggingArthur Heymans2021-06-281-13/+13
| | | | | | | | | | | The wrong format was used. It looks like struct bitfields are of type int according to gcc so %u needs to be used and not %lu. Change-Id: I54419d722aec0d43e6f54a4bb4eb4d899c909fec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55847 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/pirika: Support audio AMP auto modeAlex1 Kao2021-06-281-0/+8
| | | | | | | | | | | | | | | Support audio AMP selection with fw_config. BUG=b:188446060 BRANCH=None. TEST=built pass Change-Id: Idf0eb2a87bfa9665e61d185e37adb90987f3cefb Signed-off-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55664 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com>
* mb/google/dedede/var/blipper: Enable ELAN touchscreenZanxi Chen2021-06-281-15/+14
| | | | | | | | | | | | | | | | Modify driver from hid to generic(ELAN0001 that used generic driver without hid). BUG=b:191620724 BRANCH=dedede TEST=build bios and boot, touchscreen will work properly. Change-Id: Ife77d514d9906049f237edd169bc07bb53c48579 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
* soc/intel: Drop casts around `soc_read_pmc_base()`Angel Pons2021-06-2810-25/+18
| | | | | | | | | | | | | | | | | The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then casted to a pointer type for use with `read32()` and/or `write32()`. But since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()` functions live in `arch/mmio.h`. These functions use the `uintptr_t type for the address parameter instead of a pointer type, and using them with the `soc_read_pmc_base()` function allows dropping the casts to pointer. Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 14:50:37 +0000