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riscv
Commit message (
Expand
)
Author
Age
Files
Lines
*
src/acpi to src/lib: Fix spelling errors
Martin Roth
2021-10-05
2
-2
/
+2
*
arch/riscv: Avoid gcc11 replacing memset implementation with memset call
Patrick Georgi
2021-09-19
1
-1
/
+1
*
arch/riscv/trap_handler: add missing types.h include
Felix Held
2021-09-17
1
-0
/
+1
*
arch/{arm,ppc64,riscv}: Remove cpu_info
Raul E Rangel
2021-07-26
1
-11
/
+0
*
cbfs: Remove prog_locate() for payloads (SELF and FIT)
Julius Werner
2021-03-17
1
-3
/
+0
*
src: Remove redundant include <rules.h>
Elyes HAOUAS
2021-02-07
1
-1
/
+0
*
symbols: Change implementation details of DECLARE_OPTIONAL_REGION()
Julius Werner
2020-08-27
1
-2
/
+0
*
src/arch: Drop unneeded empty lines
Elyes HAOUAS
2020-08-24
3
-4
/
+0
*
src: Remove unused 'include <stddef.h>
Elyes HAOUAS
2020-08-18
3
-3
/
+0
*
treewide: Add Kconfig variable MEMLAYOUT_LD_FILE
Furquan Shaikh
2020-06-13
1
-3
/
+3
*
src: Remove unused '#include <cbfs.h>'
Elyes HAOUAS
2020-06-02
1
-1
/
+0
*
src: Remove unused 'include <lib.h>'
Elyes HAOUAS
2020-05-18
1
-1
/
+0
*
src: Remove leading blank lines from SPDX header
Elyes HAOUAS
2020-05-18
1
-4
/
+0
*
src: Remove unused '#include <stdint.h>'
Elyes HAOUAS
2020-05-13
1
-1
/
+0
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
42
-42
/
+0
*
src/arch/riscv: Convert to SPDX license header
Patrick Georgi
2020-03-06
42
-694
/
+84
*
commonlib: Add commonlib/bsd
Julius Werner
2020-01-28
4
-5
/
+3
*
src/arch: Remove unused <stdlib.h>
Elyes HAOUAS
2019-12-19
1
-1
/
+0
*
arch/*/*/early_variables.h: drop unused files
Arthur Heymans
2019-11-30
1
-29
/
+0
*
Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol
Arthur Heymans
2019-11-25
1
-1
/
+0
*
lib/Kconfig: Remove RAMSTAGE_CBMEM_TOP_ARG
Arthur Heymans
2019-11-10
1
-1
/
+0
*
arch/riscv: Pass cbmem_top to ramstage via calling argument
Arthur Heymans
2019-11-10
3
-6
/
+11
*
arch/riscv: Use FDT from calling argument when using FIT
Arthur Heymans
2019-11-06
1
-14
/
+4
*
arch/riscv: Rename `stages.c` to `romstage.c`
Nico Huber
2019-11-06
2
-10
/
+1
*
arch/riscv: Don't link `stages.c` into ramstage
Nico Huber
2019-11-05
1
-1
/
+0
*
src: Remove unused 'include <string.h>'
Elyes HAOUAS
2019-10-20
1
-1
/
+0
*
arch/x86: Refactor CAR_GLOBAL quirk for FSP1.0
Kyösti Mälkki
2019-09-09
1
-1
/
+3
*
arch/non-x86: Use ENV_ROMSTAGE_OR_BEFORE
Kyösti Mälkki
2019-08-26
1
-1
/
+1
*
arch/non-x86: Remove use of __PRE_RAM__
Kyösti Mälkki
2019-08-20
1
-5
/
+1
*
arch/riscv: Enable FIT support
Jonathan Neuschäfer
2019-08-08
2
-0
/
+142
*
riscv: add support for OpenSBI
Xiang Wang
2019-08-03
7
-11
/
+182
*
riscv: Remove unused headers
Patrick Rudolph
2019-07-28
1
-2
/
+0
*
arch, include, soc: Use common stdint.h
Jacob Garber
2019-07-12
1
-79
/
+0
*
arch/riscv: Make RISCV specific options depend on ARCH_RISCV
Arthur Heymans
2019-07-02
1
-11
/
+12
*
arch/riscv/mcall: Drop debug code
Patrick Rudolph
2019-06-28
1
-9
/
+0
*
riscv: workaround selfboot putting the coreboot table into prog_entry_arg
Xiang Wang
2019-06-23
1
-0
/
+7
*
riscv: use mret to invoke M-mode payload and disable interrupts
Xiang Wang
2019-06-23
1
-5
/
+20
*
riscv: Fix MENTRY_FRAME_SIZE to fit different machine lengths
Xiang Wang
2019-06-23
1
-1
/
+1
*
arch/riscv/Kconfig: Make correct default value for CONFIG_ARCH_RISCV_M
Subrata Banik
2019-06-04
1
-2
/
+2
*
src: Use include <console/console.h> when appropriate
Elyes HAOUAS
2019-04-23
1
-1
/
+0
*
src: Add missing include 'console.h'
Elyes HAOUAS
2019-04-23
1
-1
/
+0
*
src: Use 'include <string.h>' when appropriate
Elyes HAOUAS
2019-03-20
1
-1
/
+0
*
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-03-08
2
-3
/
+3
*
arch/io.h: Separate MMIO and PNP ops
Kyösti Mälkki
2019-03-04
1
-3
/
+3
*
device/mmio.h: Add include file for MMIO ops
Kyösti Mälkki
2019-03-04
1
-1
/
+1
*
riscv: Add initial support for 32bit boards
Philipp Hug
2019-02-13
7
-16
/
+46
*
riscv: Use correct argument in a1 when invoking payload
Philipp Hug
2019-02-09
1
-1
/
+1
*
riscv: Show hart id in trap handler
Philipp Hug
2019-02-02
1
-0
/
+2
*
riscv: Simplify payload handling
Xiang Wang
2019-02-02
10
-59
/
+94
*
riscv: ARCH_RISCV_RV{32,64} selects ARCH_RISCV
Ronald G. Minnich
2019-01-24
1
-1
/
+2
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