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* ec, lib, security, sb: Add SPDX license headers to Kconfig filesMartin Roth2024-02-1817-0/+34
| | | | | | | | Change-Id: Ie63499a4b432803a78af1c52d49e34cf1653ba17 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80589 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin: Remove ubtc.aslSean Rhodes2024-02-152-52/+0
| | | | | | | | | | Remove the ubtc.asl as it's no longer needed. Change-Id: I8564bb7d9bd94c8303c543c078bc76192539c5f2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80484 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin: Remove the CMOS Bank 1 entriesSean Rhodes2024-02-151-16/+0
| | | | | | | | | | These entries no longer exist as they are stored in CFR. Change-Id: Ia85855fddc36db76a65490a1d685e1943db28b74 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/starlabs/merlin: Remove the call to pc_keyboard_initSean Rhodes2024-02-141-2/+0
| | | | | | | | | | As DRIVERS_PS2_KEYBOARD isn't set, this function is not doing anything. Change-Id: Ie8842a32fca56f330a0f044cf96112dc5cae6546 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/lenovo/h8/acpi: Support pulsing LEDLOGO on Haswell ThinkPadsEvgeny Sorokin2024-02-122-0/+20
| | | | | | | | | | | | | | | | | | | | | | | The name LEDLOGO comes from schematics. It's the red indicator, embedded in the dot of the 'i' of the ThinkPad logo on laptop's lid. In vendor firmware, this led starts fading in-and-out, or, in other words, pulsing, when laptop is put to S3. It helps to determine whether the laptop is in S3 just by taking a look at the logo. As of now, coreboot doesn't do anything with this particular indicator, it's always in enabled (on) state, which is not very convenient. This patch fixes it. Tested on T440p. Change-Id: I85fb69c8c1bed8635a1b31e9b8385c7036bb46dd Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80437 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* device/device.h: Rename busses for clarityArthur Heymans2024-01-311-1/+1
| | | | | | | | | | This renames bus to upstream and link_list to downstream. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: I80a81b6b8606e450ff180add9439481ec28c2420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* include/device/device.h: Remove CHIP_NAME() macroNicholas Sudsgaard2024-01-3121-21/+21
| | | | | | | | | | | | | | | | | | | | | | | Macros can be confusing on their own; hiding commas make things worse. This can sometimes be downright misleading. A "good" example would be the code in soc/intel/xeon_sp/spr/chip.c: CHIP_NAME("Intel SapphireRapids-SP").enable_dev = chip_enable_dev, This appears as CHIP_NAME() being some struct when in fact these are defining 2 separate members of the same struct. It was decided to remove this macro altogether, as it does not do anything special and incurs a maintenance burden. Change-Id: Iaed6dfb144bddcf5c43634b0c955c19afce388f0 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80239 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Jakub Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* ec: Rename Makefiles from .inc to .mkMartin Roth2024-01-2425-0/+0
| | | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic060f3605cd18d4bf774573c21957f626f984e2c Reviewed-on: https://review.coreboot.org/c/coreboot/+/80069 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* ec/dell/mec5035: Hook up radio enables to option APINicholas Chin2024-01-231-0/+5
| | | | | | | | | | Change-Id: Ibfa17ca83ca178c942d9c41533152235384e0cdf Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Original-Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/77535 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* ec/dell/mec5035: Add command to control radio stateNicholas Chin2024-01-232-0/+23
| | | | | | | | | | | | | | | This was determined by sniffing the LPC bus while moving the hardware wireless switch between the enabled and disabled positions on the Latitude E6400. The vendor BIOS provides options to change which radios the switch controls, which was used to determine the mapping between each radio device and the command argument values. Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77534 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* treewide: Use show_notices target for warningsMartin Roth2023-12-203-3/+3
| | | | | | | | | | | This updates all warnings currently being printed under the files_added and build_complete targets to the show_notices target. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia14d790dd377f2892f047059b6d24e5b5c5ea823 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79423 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/ipmi to lib: Fix misspellings & capitalization issuesMartin Roth2023-12-131-1/+1
| | | | | | | | Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I926ec4c1c00339209ef656995031026935e52558 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77637 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Provide ec_sync wake optionMark Hasemeyer2023-12-111-3/+10
| | | | | | | | | | | | | | | | | | | | | The ACPI spec defines keywords for the GpioInt and Interrupt resources to specify whether a given pin is wake capable. Some boards are using the ec sync interrupt pin to wake the system so the CREC _CRS needs to be updated accordingly. Provide a new macro that allows a board to specify whether its ec sync pin is wake capable. BUG=b:243700486 TEST=Dump ACPI and verify ExclusiveAndWake share type is set when EC_SYNC_IRQ_WAKE_CAPABLE is defined Change-Id: I483c801ff0fee4d3ce0a3b2fc220e0bd9356a612 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Forest Mittelberg <bmbm@google.com>
* ec/lenovo/h8/acpi/thermal: Make NameSeg FPWR all upper casePaul Menzel2023-12-041-2/+2
| | | | | | | | | | | | | | | | | | | | Building the Lenovo T60/T60p, iasl 20230628 shows the remark below: dsdt.asl 2099: PowerResource (FPwR, 0, 0) Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR) dsdt.asl 2118: Name (_PR0, Package () { FPwR }) Remark 2182 - ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (FPWR) Address it by making it all upper case. Change-Id: Ia7924b015e76c43818d2d82da35ce0013d721c26 Fixes: 3ab13a8691cb ("ec/lenovo/h8/acpi/thermal: Add support for passive cooling") Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79367 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Update ec_cmd_api.h and ec_commands.hSimon Glass2023-11-162-6/+471
| | | | | | | | | | | | | | | | | | | Generated using update_ec_headers.sh [EC-DIR]. The original include/ec_commands.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state The original include/ec_cmd_api.h version in the EC repo is: ab9b64ac4c Add a host command to print info about AP-firmware state BUG=b:300525571 BRANCH=none TEST=none Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin/ite: Adjust the mirror flag handlingSean Rhodes2023-10-242-36/+7
| | | | | | | | | | | | | | | | | | | | | In EC versions older than 1.18, if the mirror flag was enabled, the EC would mirror once the system reached S5. When a mirror is successful, the system will automatically power on, as it acts like it's been in G3. This led to machines turning on when the intention was them to be off. In 1.18 and later, they're installed when turning on. The result was slower boot times when mirroring, but no unwanted powering on. Because of this, coreboot no longer needs to power off when setting the mirror flag. Change-Id: I973c1ecd59f32d3353ca392769b44aadf5fcc9c3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* Revert "ec/dell/mec5035: Hook up radio enables to option API"Matt DeVillier2023-10-201-5/+0
| | | | | | | | | | | | | This reverts commit bb5fa6419dfd71950e61e75eecd48ef8203bb1b1. Reason for revert: accidentally committed out of order; reverting to unbreak tree Change-Id: I36aa1fd3a0befe49b7e9e34198676f16fb08cf73 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78524 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: Martin L Roth <gaumless@gmail.com>
* ec/dell/mec5035: Hook up radio enables to option APINicholas Chin2023-10-201-0/+5
| | | | | | | | Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* ec/google/chromeec: Add is_battery_present_and_above_critical_thresholdJamie Ryu2023-10-162-0/+24
| | | | | | | | | | | | | | | This adds is_battery_present_and_above_critical_threshold to check the battery is present and the battery level is above critical level. BUG=b:296952944 TEST=Build rex and check is_battery_present_and_above_critical_threshold returns the correct battery status. Change-Id: Ib38be55bc42559bab4f12d5e8580ddc3e1a6acc1 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* ec/starlabs/merlin: Update the Q EventsSean Rhodes2023-10-041-4/+2
| | | | | | | | | | | | Simplify the Q events for the battery and charger to just notify when a status has changed. The EC will trigger these events when either has changed. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3300be5254549fe5cd3b3490d9191240c6d36b6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/77405 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi/acpigen_ps2_keybd: Reduce minimum keys, optional alpha/num/punctJonathon Hall2023-10-021-1/+2
| | | | | | | | | | | | | Librem 11's volume keys act as a PS/2 keyboard with only those two keys. Reduce the minimum number of top-row keys to 2. Make the "rest of keys" (alphanumerics, punctuation, etc.) optional. Change-Id: Idf80b184ec816043138750ee0a869b23f1e6dcf2 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* clean-up: Remove the no more necessary `ENV_HAS_DATA_SECTION` flagJeremy Compostella2023-09-185-7/+4
| | | | | | | | | | | | | With commit b7832de0260b042c25bf8f53abcb32e20a29ae9c ("x86: Add .data section support for pre-memory stages"), the `ENV_HAS_DATA_SECTION' flag and its derivatives can now be removed from the code. Change-Id: Ic0afac76264a9bd4a9c93ca35c90bd84e9b747a2 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77291 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/hp/kbc1126: Use packed over attrbute__((packed))Elyes Haouas2023-09-171-2/+2
| | | | | | | | Change-Id: Ia4b142a5eac2aab7e4fa6e32ed68c96934ec6c32 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* vc/google/chromeos: Move clear_ec_ap_idle() to common codeDerek Huang2023-09-142-0/+15
| | | | | | | | | | | | | | | | Previously the clear_ec_ap_idle() is implemented in cr50_enable_update.c and be called in the file. Move it to common code so that it can be called in cse_board_reset.c TEST=emerge-brask coreboot Change-Id: I2dbe41b01e70f7259f75d967e6df694a3e0fac23 Signed-off-by: Derek Huang <derekhuang@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77631 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* ec/lenovo/h8/h8.c: Use sizeof()Elyes Haouas2023-09-071-1/+1
| | | | | | | | | | | | Use 'sizeof(ecfw)' instead of 'sizeof ecfw'. sizeof operator should only be used for types and variables require sizeof(). Change-Id: Ifae1680917bb0ce610e6ba753741aae233a71103 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* ec/starlabs/merlin: Unconditionally enable the Keyboard BacklightSean Rhodes2023-08-302-18/+6
| | | | | | | | | | | | | | | | KBL_STATE was originally intended to provide more granular control of the keyboard backlight. However, KBL_BRIGHTNESS has a valid value of "off" which achieves the same thing. Therefore, unconditionally set the KBL_STATE to enabled, and rely on KBL_BRIGHTNESS. Change-Id: Ic7ee6b96b1dcaa6633b111e92097bce87908885e Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77201 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/wilco/superio: Adjust PS2K HID/CID for Windows driversMatt DeVillier2023-08-211-2/+2
| | | | | | | | | | | | | | Allows coolstar's Windows overlay drivers to attach, while not affecting operation under Linux or ChromeOS TEST=build/boot Win11, Linux 6.x on google/drallion Change-Id: I30ab2e9da00743c4d7086aac94652be46040f36d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77305 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/wilco/acpi: Read message when notifying UCSICoolStar2023-08-212-22/+30
| | | | | | | | | | | | | | Allows the EC to be properly notified of type-c events like charger wattage too low (eg), TEST=build/boot Win11, Linux 6.x on google/drallion Change-Id: I7a4130cf6f8c24e3f91e327adf1f3e563322c0af Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77282 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/wilco: Correct scope of UCSI ACPI deviceCoolStar2023-08-215-177/+195
| | | | | | | | | | | | | | | Set the USCI device scope to _SB and set HID to USBC000 so Windows driver attaches. This matches the ACPI used by the non-Chromebook version of the Dell Latittude 7410 (which uses the same EC). TEST=build/boot Win11 on google/drallion Change-Id: If482fa4a4856c7bc085795bc72b35ebefe2f15c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77281 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/wilco/acpi: Unhide GOOG000C ACPI deviceMatt DeVillier2023-08-211-1/+1
| | | | | | | | | | | | | Allows coolstar's Windows drivers to attach. TEST=build/boot Win11 on google/drallion Change-Id: Idd339811563cd2cdfc4cc31bc5660a62f4e36a66 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* ec/google/wilco/acpi/dptf: Fix mutex synclevelMatt DeVillier2023-08-211-1/+1
| | | | | | | | | | | | | | | | Both Windows and MacOS get cranky if the Mutex synclevel is non-zero, aborting any Acquire() call with Mutex param that has a non-zero synclevel. TEST=build/boot Win11 on google/drallion, verify DPTF driver loaded and functional. Change-Id: Ie77e9ed04658b508b2063ae219afcdc0ac465c58 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77279 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/wilco: Fix ACPI EC RAM read/write opsMatt DeVillier2023-08-202-3/+7
| | | | | | | | | | | | | | | | | While debugging lack of battery status under Windows, it was discovered that the read/write flags in the args to the EC RAM 'ECRW' method were not being correctly identified. Force set them from the R() and W() methods which call ECRW() so those calls are processed properly. TEST=build/boot Windows on google/drallion, verify battery status, charging, etc are all reported properly. Change-Id: I2a40b8d50ba65213813c781e53b56cc1a8b8debf Signed-off-by: Coolstar <coolstarorganization@gmail.com> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* ACPI: Add usb_charge_mode_from_gnvs()Kyösti Mälkki2023-08-162-0/+16
| | | | | | | | | | | | | | | Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/starlabs/merlin/ite: Don't attempt EC mirror without a counterSean Rhodes2023-08-111-26/+19
| | | | | | | | | | | If the variable `mirror_flag_attempts` isn't accessible, or doesn't have a value, don't attempt to mirror the EC. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ia39b2ce4ffcb8db3a335449c8bdb0d5c8a28a52c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/starlabs/merlin: Change the symbol to check before mirroringSean Rhodes2023-08-111-1/+1
| | | | | | | | | | | | The EC should be mirrored (if it's out of date) unconditionally if the board support Thunderbolt. Use DRIVERS_INTEL_USB4_RETIMER instead of SOC_INTEL_COMMON_BLOCK_TCSS as it's more suitable. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I27b238d4d404746c9a70bacf8e60d9e0b0e1ccca Reviewed-on: https://review.coreboot.org/c/coreboot/+/76579 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/starlabs/merlin/ite: Print version mismatchesSean Rhodes2023-08-101-2/+5
| | | | | | | | | | | If the version of the EC firmware in coreboot doesn't match the firmware that the EC is running, print the versions. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I55c09b8d5ffe8ca9135384c823d005b55cfd83d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76380 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/tgl: Use the merlin ec codeSean Rhodes2023-08-103-472/+0
| | | | | | | | | | | | | Switch the TGL variant to use the "merlin" EC variant, and delete the no longer needed "TGL" EC variant. This is not a functional change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id4d305490b48c1c79ea52b0bbaa79b675412e0b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76332 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/starlabs/starbook/adl: Use the merlin ec codeSean Rhodes2023-08-103-459/+0
| | | | | | | | | | | | | Switch the ADL variant to use the "merlin" EC variant, and delete the no longer needed "ADL" EC variant. This is not a functional change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I61e56cc95a26be60d7f10c89d26bce2d857ae81a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/starlabs/merlin: Remove the UCSI ACPISean Rhodes2023-08-109-92/+0
| | | | | | | | | | The UCSI mailbox isn't used, so remove it. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I03587a2322b1f34fa26a5c2ba7906a4e1ae82ae0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/starlabs/merlin: Update the merlin variantSean Rhodes2023-08-103-390/+39
| | | | | | | | | | | | | | | | | Merlin was the name for the open-source variant of the EC. It ended up getting entirely rewritten to work with SDCC, and is currently being used on starbook/adl. The source code isn't available at the time of this commit due to some old ITE XLT code being used. Add the latest version of the code, replacing the old code, so the boards can be migrated over. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ib8384fc9322058297e8219ac8e483ac37a70bd33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* ec/google/chromeec: move TBMC ACPI device under CRECMatt DeVillier2023-08-043-7/+8
| | | | | | | | | | | | | | | | | | | Tablet motion control is a function of the EC, and under Windows, the TBMC device needs to be initialized after CREC, or driver init will fail. The only way to ensure this happens is for TBMC to be a child device under CREC. TEST=build/boot Win11, Linux on google/eve, verify tablet mode drivers loaded and orientation switching functional under both OSes. Change-Id: I5e9eab9ae277b5a04dc2666960a727e5680bf6f4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76792 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* ec/google/chromeec: Unhide ChromeEC PD ACPI deviceMatt DeVillier2023-07-311-1/+1
| | | | | | | | | | | | | | | | Set the ACPI status (_STA) for the PD device enabled+visible, to allow coolstar's Windows drivers for USB4/Thunderbolt to attach. TEST=build/boot Win11 on google/drobit, install USB4/TB drivers, verify USB4/TB ports are functional for PD and data at USB4 speeds. Change-Id: I84a20cfaf7e077469f8361b3da3b031d9fd84134 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* ec/google/chromeec: Unhide GOOG0004 ACPI deviceMatt DeVillier2023-07-311-1/+1
| | | | | | | | | | | | | | | | | Set the ACPI status (_STA) for the EC ACPI to enabled+visible, to allow coolstar's Windows drivers for the EC and keyboard backlight to attach. TEST=build/boot Win11 on google/samus, install EC/kblight drivers, verify keyboard backlight control functional. Change-Id: I3e9578f1ef18b3bebb93a9ae2ae4e27bc38f648d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76790 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* {ec,mb}/system76: Replace color keyboard logicTim Crawford2023-07-182-35/+38
| | | | | | | | | | | | System76 EC since system76/ec@9ac513128ad9 detects if the keyboard is white or RGB backlit via `RGBKB-DET#` at runtime. Remove the Kconfig for the selection and update the ACPI methods for the new functionality. Change-Id: I60d3d165a58e30d2afc8736c0eb64dd90c8227ca Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76152 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Split wait-loop for DP and HPD flagsKapil Porwal2023-07-153-10/+54
| | | | | | | | | | | | | | | | | Split wait-loop for DP and HPD flags as below - - google_chromeec_wait_for_hpd - google_chromeec_wait_for_dp_mode_entry BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e565d6134f6433930916071e94d56d92dc6cb06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76370 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Call `wait_for_dp_hpd` only in AP mode entryKapil Porwal2023-07-151-0/+10
| | | | | | | | | | | | | | | Wait for DP/HPD flags only in AP initiated mode entry BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5137c346fbf1edabc60a53e0978e32f54885c330 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76369 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ec/google/chromeec: Skip TCSS `wait_for_connection` for AP mode entryKapil Porwal2023-07-151-0/+5
| | | | | | | | | | | | | | | Skip TCSS `wait_for_connection` for AP initiated mode entry. BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia04ff470961831237fe851f7ae3feaa5623d4b4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76368 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* ec/google/chromeec: Skip unnecessary call to TCSS `enter_dp_mode` cmdKapil Porwal2023-07-151-0/+7
| | | | | | | | | | | | | | | Skip TCSS `enter_dp_mode` command when there is no USB device detected on the port. BUG=b:247670186 TEST=Verify display over TCSS and its impact on boot time for google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ie6cd84cab3631596d4d7178dae2040e25c621f63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* ec/system76/ec: Do not call reset on wakeTim Crawford2023-07-031-3/+0
| | | | | | | | | | | | Resetting the device will cause the keyboard backlight and airplane LED to lose their state. Change-Id: I2f46542fb6b32c479b01335149c9190f6fa1421f Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75275 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious2023-06-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The prefix POSTCODE makes it clear that the macro is a post code. Hence, replace related macros starting with POST to POSTCODE and also replace every instance the macros are invoked with the new name. The files was changed by running the following bash script from the top level directory. sed -i'' '30,${s/#define POST/#define POSTCODE/g;}' \ src/commonlib/include/commonlib/console/post_codes.h; myArray=`grep -e "^#define POSTCODE_" \ src/commonlib/include/commonlib/console/post_codes.h | \ grep -v "POST_CODES_H" | tr '\t' ' ' | cut -d ' ' -f 2`; for str in ${myArray[@]}; do splitstr=`echo $str | cut -d '_' -f2-` grep -r POST_$splitstr src | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; grep -r "POST_$splitstr" util/cbfstool | \ cut -d ':' -f 1 | xargs sed -i'' -e "s/POST_$splitstr/$str/g"; done Change-Id: I25db79fa15f032c08678f66d86c10c928b7de9b8 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76043 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-17 00:19:54 +0000