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path: root/src/include/cpu/amd/msr.h
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* include/cpu/amd/msr: introduce and use PSTATE_MSR_COUNTFelix Held2023-07-181-0/+1
* soc/amd/common/block/acpi/cpu_power_state: use pstate_msr unionFelix Held2023-03-231-2/+0
* soc/amd/include/msr: factor out P state MSR enable bit to cpu/amd/msr.hFelix Held2023-03-081-0/+3
* soc/amd: introduce and use PSTATE_MSR macroFelix Held2023-02-281-4/+1
* soc/amd/sabrina/acpi: Correct VID decoding on SabrinaFred Reitberger2022-06-091-3/+0
* include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSRFelix Held2021-07-161-1/+0
* include/cpu/amd/msr: add and use MC_CTL_MASK macroFelix Held2021-07-141-2/+1
* include/cpu/x86/msr: move MC0_CTL_MASK to include/cpu/amd/msrFelix Held2021-07-141-0/+1
* include/cpu/amd/msr: rename MSR_PSP_ADDR to PSP_ADDR_MSRFelix Held2021-02-191-1/+1
* soc/amd/common/amdblocks/psp: move MSR_PSP_ADDR to include/cpu/amd/msr.hFelix Held2021-02-191-0/+1
* soc/amd/picasso: Separate CPUID defs into new headerJason Glenesk2021-01-021-5/+0
* soc/amd/picasso: Generate ACPI pstate and cstate objects in cbJason Glenesk2020-09-251-3/+13
* include/cpu/amd/msr: move SMM_LOCK bit right after HWCR_MSR definitionFelix Held2020-07-091-1/+1
* soc/amd/picasso/bootblock: Write EIP to secure S3Raul E Rangel2020-06-221-0/+1
* amd/common: Add the macro definition for patch level MSRZheng Bao2020-06-101-0/+1
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* src/include: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-3/+0
* cpu/amd/msr: Clarify MMIO_CONF shift valueMarshall Dawson2019-07-021-1/+1
* cpu/amd: Use common AMD's MSRElyes HAOUAS2018-11-051-0/+2
* cpu/amd: Use common AMD's MSRElyes HAOUAS2018-10-181-6/+51
* src/include: Wrap lines at 80 columnsLee Leahy2017-03-131-1/+2
* cpu/amd: de-duplicate MSR include filesStefan Reinauer2015-11-231-0/+45