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* device/dram/common.h: Use C over CPPArthur Heymans2022-05-111-5/+5
* include/device/dram/ddr3.h: Don't redefine 'printram(x, ...)'Elyes HAOUAS2022-02-211-15/+0
* arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik2021-11-111-0/+10
* device/dram: Add LPDDR4 utilitiesRob Barnes2021-06-091-0/+20
* device/dram/ddr3: Drop unused MRS helpersAngel Pons2021-04-051-130/+0
* device/dram/ddr4.h: Align with DDR3 and DDR2Angel Pons2021-04-051-18/+18
* device/dram/ddr3: Rename DDR3 SPD memory typesAngel Pons2021-04-051-18/+18
* device/dram/ddr3: Get rid of useless typedefsAngel Pons2021-04-051-9/+9
* device/dram: Move SPD manufacturer names out of arch/x86Patrick Rudolph2021-02-161-0/+10
* src: Change bare 'unsigned' to 'unsigned int'Martin Roth2020-11-161-15/+15
* device/dram: Add method for converting MHz to MT/sRob Barnes2020-09-161-0/+5
* src/include: Drop unneeded empty linesElyes HAOUAS2020-09-142-2/+0
* src: Change BOOL CONFIG_ to CONFIG() in comments & stringsMartin Roth2020-07-262-4/+4
* src: Remove redundant includesElyes HAOUAS2020-06-022-2/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-114-4/+0
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-063-36/+3
* treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi2020-05-063-6/+3
* src/include: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-174-5/+0
* src/{device,drivers,mb,nb,soc,sb}: Remove unused 'include <console/console.h>'Elyes HAOUAS2019-10-211-0/+1
* src/{drivers/vpd,include/device/dram}: Add missing 'include <stdint.h>'Elyes HAOUAS2019-10-211-0/+2
* dram: Add basic DDR4 SPD parsingAndrey Petrov2019-08-142-1/+88
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-082-2/+2
* nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.cPatrick Rudolph2018-08-211-1/+4
* nb/intel/sandybridge: Fill in DIMM serial numberPatrick Rudolph2018-08-201-0/+2
* device/dram/ddr3: improve XMP supportDan Elkouby2018-04-161-0/+2
* device/dram/ddr2.c: Add methods to compute to identify dramArthur Heymans2018-04-092-0/+3
* device/ddr2,ddr3: Rename and move a few thingsArthur Heymans2018-02-223-92/+91
* device/dram/ddr2.c: Store the checksum in the decoded SPD structArthur Heymans2017-12-201-0/+1
* device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flagArthur Heymans2017-09-221-0/+2
* device/dram/ddr2: Add a function to normalize tCLKArthur Heymans2017-09-061-1/+2
* device/dram/ddr3.h: Add brackets around macroArthur Heymans2017-06-221-1/+1
* haswell: add CBMEM_MEMINFO table when initing RAMMatt DeVillier2017-06-161-0/+13
* nb/intel/sandybridge: Improve CAS freq selectionArthur Heymans2017-06-121-0/+2
* device/dram/ddr2.c: Fix is_registered_ddr2Arthur Heymans2017-06-091-1/+1
* src/include: Fix space between type, * and variable nameLee Leahy2017-03-131-3/+3
* device/dram/ddr2: Add common ddr2 spd decoderPatrick Rudolph2017-03-102-1/+219
* src/include: Indent code using tabsLee Leahy2017-03-091-2/+2
* src/include: Fix unsigned warningsLee Leahy2017-03-091-15/+15
* device/dram/ddr3: Calculate CRC16 of SPD unique identifierKyösti Mälkki2016-11-201-0/+1
* SPD: fix DDR3 SDRAM memory module typesElyes HAOUAS2016-06-241-2/+8
* include/device/dram/ddr3: Add additional frequenciesPatrick Rudolph2016-06-201-0/+4
* include/device/dram: Fix DDR3-1866Patrick Rudolph2016-03-051-1/+1
* src/device/dram/ddr3: Parse additional informationPatrick Rudolph2016-03-031-0/+4
* nb/intel/sandybridge/romstage: Read fuse bits for max MEM ClkPatrick Rudolph2016-03-021-1/+3
* nb/intel/sandybridge/raminit: Add XMP supportPatrick Rudolph2016-02-201-0/+12
* header files: Fix guard name comments to match guard namesMartin Roth2016-01-181-1/+1
* tree: drop last paragraph of GPL copyright headerPatrick Georgi2015-10-311-3/+0
* Change #ifdef and #if defined CONFIG_ bools to #if IS_ENABLED()Martin Roth2015-07-121-1/+1
* device: DDR3 generic code 64bit fixStefan Reinauer2015-06-221-1/+1
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