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* lib: Move IP checksum to commonlibJulius Werner2024-02-021-4/+3
| | | | | | | | | | | | | | | | | | | | | | This patch moves the IP checksum algorithm into commonlib to prepare for it being shared with libpayload. The current implementation is ancient and pretty hard to read (and does some unnecessary questionable things like the type-punning stuff which leads to suboptimal code generation), so this reimplements it from scratch (that also helps with the licensing). This algorithm is prepared to take in a pre-calculated "wide" checksum in a machine-register-sized data type which is then narrowed down to 16 bits (see RFC 1071 for why that's valid). This isn't used yet (and the code will get optimized out), but will be used later in this patch series for architecture-specific optimization. Change-Id: Ic04c714c00439a17fc04a8a6e730cc2aa19b8e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80251 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <czapiga@google.com>
* Center bootsplash on bigger framebuffersNico Huber2023-07-171-1/+2
| | | | | | | | | | | | | | | In the JPEG decoder, use `bytes_per_line` instead of `width` for address calculations, to allow for bigger framebuffers. When calling jpeg_decode(), add an offset to the framebuffer address so the picture gets centered. Change-Id: I0174bdccfaad425e708a5fa50bcb28a1b98a23f7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* lib/version: Move board identification stringsKyösti Mälkki2023-04-221-1/+2
| | | | | | | | | | | | | | | These strings are now only expanded in lib/identity.c. This improves ccache hit rates slightly, as one built object file lib/version.o is used for all variants of a board. Also one built object file lib/identity.o can become a ccache hit for successive builds of a variant, while the commit hash changes. Change-Id: Ia7d5454d95c8698ab1c1744e63ea4c04d615bb3b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* treewide: stop calling custom TPM log "TCPA"Sergii Dmytruk2023-01-111-1/+1
| | | | | | | | | | | TCPA usually refers to log described by TPM 1.2 specification. Change-Id: I896bd94f18b34d6c4b280f58b011d704df3d4022 Ticket: https://ticket.coreboot.org/issues/423 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* coreboot_tables: Make existing alignment conventions more explicitJulius Werner2022-12-221-5/+9
| | | | | | | | | | | | | | | | | | There seem to be some recurring vague concerns about the alignment of coreboot table entries. While the existing implementation has been producing tables with a well-defined alignment (4 bytes) for a long time, the code doesn't always make it very clear. This patch adds an explicit constant to codify that alignment, assertions to check it after each entry, and adds explicit padding to the few entry structures that were relying on compiler padding to return a correct sizeof() value. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Iaeef29ef255047a855066469e03b5481812e5975 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70158 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Peter Stuge <peter@stuge.se>
* lib/coreboot_table: Rename lb_fill_pcieArthur Heymans2022-11-041-2/+2
| | | | | | | | | | By convention 'fill_lb_xxx' is used. Change-Id: I046016b3898308bb56b4ad6a5834ab942fdd50f2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69183 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/coreboot_table: Simplify API to set up lb_serialArthur Heymans2022-11-041-13/+16
| | | | | | | | | | | | | | | | | Instead of having callbacks into serial console code to set up the coreboot table have the coreboot table code call IP specific code to get serial information. This makes it easier to reuse the information as the return value can be used in a different context (e.g. when filling in a FDT). This also removes boilerplate code to set up lb_console entries by setting entry based on the type in struct lb_uart. Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* coreboot_tables: Drop uart PCI addrArthur Heymans2022-10-261-1/+0
| | | | | | | | | | | | | | | Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* coreboot_tables: Add PCIe info to coreboot tableJianjun Wang2022-05-191-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 'lb_fill_pcie' function to pass PCIe information from coreboot to libpayload, and add CB_ERR_NOT_IMPLEMENTED to the cb_err enum for the __weak function. ARM platform usually does not have common address for PCIe to access the configuration space of devices. Therefore, new API is added to pass the base address of PCIe controller for payloads to access PCIe devices. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: I6cdce21efc66aa441ec077e6fc1d5d1c6a9aafb0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Shelley Chen <shchen@google.com>
* lib: Remove unused <stdlib.h> and use <types.h> when appropriateElyes HAOUAS2022-04-241-1/+1
| | | | | | | | | | | Unused <stdlib.h> found using: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l 'memalign(\|malloc(\|calloc(\|free(' -- src/) Change-Id: I5ad171679cbfa67d522bd1105fb58e0f84b9cb89 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <martinroth@google.com>
* lib/coreboot_table.c: Use align macroArthur Heymans2022-04-201-3/+1
| | | | | | | | Change-Id: Ie874fe2c023157fad0adc021faa45e70822208da Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* coreboot_tables: Replace 'struct lb_uint64' with lb_uint64_tJianjun Wang2022-04-141-2/+2
| | | | | | | | | | | | | | | Replace 'struct lb_uint64' with 'typedef __aligned(4) uint64_t lb_uint64_t', and remove unpack_lb64/pack_lb64 functions since it's no longer needed. Also replace 'struct cbuint64' with 'cb_uint64_t' and remove 'cb_unpack64' in libpayload for compatible with lb_uint64_t. Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com> Change-Id: If6b037e4403a8000625f4a5fb8d20311fe76200a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* coreboot_tables.c: Expose the ACPI RSDPArthur Heymans2022-03-091-0/+14
| | | | | | | | | | | | | | | | | | | | | The ACPI RSDP can only be found in: - legacy BIOS region - via UEFI service On some systems like ARM that legacy BIOS region is not an option, so to avoid needing UEFI it makes sense to expose the RSDP via a coreboot table entry. This also adds the respective unit test. Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62573 Reviewed-by: Lance Zhao Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* coreboot tables: Add type-c port info to coreboot tableNick Vaccaro2021-10-041-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This change adds type-c port information for USB Type-C ports to the coreboot table. This allows depthcharge to know the usb2 and usb3 port number assignments for each available port, as well as the SBU and data line orientation for the board. BUG=b:149830546 TEST='emerge-volteer coreboot chromeos-bootimage' and verify it builds successfully. Cherry-pick CL to enable this feature for volteer, flash and boot volteer2 to kernel, log in and check cbmem for type-c info exported to the payload: localhost ~ # cbmem -c | grep type-c added type-c port0 info to cbmem: usb2:9 usb3:1 sbu:0 data:0 added type-c port1 info to cbmem: usb2:4 usb3:2 sbu:1 data:0 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: Ice732be2fa634dbf31ec620552b383c4a5b41451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* nvs: Add Chrome OS NVS (CNVS) information to coreboot tablesFurquan Shaikh2021-06-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CB:51638 separated Chrome OS NVS from global NVS by allocating it separately in CBMEM. CNVS is used in depthcharge to fill firmware information at boot time. Thus, location of CNVS needs to be shared in coreboot tables for depthcharge to use. This change adds a new coreboot table tag `CB_TAG_ACPI_CNVS`/`CB_TAG_ACPI_CNVS`(0x41) which provides the location of CNVS in CBMEM to payload (depthcharge). Additionally, CB:51639 refactored device nvs(DNVS) and moved it to the end of GNVS instead of the fixed offset 0x1000. DNVS is used on older Intel platforms like baytrail, braswell and broadwell and depthcharge fills this at boot time as well. Since DNVS is no longer used on any new platforms, this information is not passed in coreboot tables. Instead depthcharge is being updated to use statically defined offsets for DNVS. BUG=b:191324611, b:191324611 TEST=Verified that `crossystem fwid` which reads fwid information from CNVS is reported correctly on brya. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I3815d5ecb5f0b534ead61836c2d275083e397ff0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55665 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/coreboot_table.c: Remove unnecessary CPP useArthur Heymans2021-05-051-6/+5
| | | | | | | | Change-Id: Ib93617867b946e208c31275d55d380aab7e51a50 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* coreboot_tables: Print strapping IDs when adding them to coreboot tableJulius Werner2021-04-021-1/+12
| | | | | | | | | | | | | These used to be printed before CB:46605. Having them in the logs can be a huge timesaver when debugging logs sent to you by other people (especially from systems that don't boot all the way). Let's add them back. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifdbfdd29d25a0937c27113ace776f7aec231a57d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* coreboot_table: Use precision when printing lb_gpio nameJulius Werner2021-02-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The lb_gpio coreboot table entries use name fields fixed to 16 bytes. GCC will not allow creating a static initializer for such a field with a string of more than 16 characters... but exactly 16 characters is fine, meaning there's no room for the terminating NUL byte. The payloads (at least depthcharge) can deal with this as well because they're checking the size when looking at that table entry, but our printk("%16s") does not and will happily walk over the end until somewhere else in memory we finally find the next NUL byte. We should probably try to avoid strings of exactly 16 characters in this field anyway, just in case -- but since GCC doesn't warn about them they can easily slip back in. So solve this bug by also adding a precision field to the printk, which will make it stop overrunning the string. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ifd7beef00d828f9dc2faa4747eace6ac4ca41899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
* coreboot_table: Move VBOOT_VBNV supportKyösti Mälkki2021-02-041-14/+2
| | | | | | | | | | | | The guard changes from (CHROMEOS && PC80_SYSTEM) to VBOOT_VBNV_CMOS here. Change-Id: I653285c04e864aa6a3494ba1400787fa184ba187 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Furquan Shaikh <furquan@google.com>
* coreboot_table: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki2021-02-041-7/+2
| | | | | | | | | | Change-Id: I0c42720fdcc3b05337af692ed93a424575defd36 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48786 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* coreboot_table: Drop <vboot/misc.h> includeKyösti Mälkki2021-02-041-1/+0
| | | | | | | | | | Could have been removed with commit 63b9700b2c already. Change-Id: Ie1083bce1794613c7dc683ae533e42fb5af39adf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50249 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* coreboot_table: Convert some CONFIG(CHROMEOS) preprocessorKyösti Mälkki2020-12-311-6/+6
| | | | | | | | | | Change-Id: I1e63a419db92642df6b7956050c39540c2ae11d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48781 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb,soc/intel: Drop unnecessary headersKyösti Mälkki2020-12-221-7/+0
| | | | | | | | | | | | | | Files under sb/ or soc/ should not have includes that tie those directly to external components like ChromeEC os ChromeOS vendorcode. Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* drivers/tpm: Implement full PPIPatrick Rudolph2020-12-211-0/+4
| | | | | | | | | | | | | | | | | | | | Implement the ACPI PPI interface as described in "TCG PC Client Physical Presence Interface Specification" Version 1.3. Add a new Kconfig that allows to use the full PPI instead of the stub version compiled in. This doesn't add code to execute the PPI request, as that's up to the payload with graphical UI support. Tested on GNU/Linux 5.6 using the sysfs interface at: /sys/class/tpm/tpm0/ppi/ Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45568 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cbfs: Simplify load/map API names, remove type argumentsJulius Werner2020-12-021-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* cbfs: Add metadata cacheJulius Werner2020-11-211-7/+4
| | | | | | | | | | | | | | | | | | | This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer that stores the headers of all CBFS files. Similar to the existing FMAP cache, this cache should reduce the amount of SPI accesses we need to do every boot: rather than having to re-read all CBFS headers from SPI flash every time we're looking for a file, we can just walk the same list in this in-memory copy and finally use it to directly access the flash at the right position for the file data. This patch adds the code to support the cache but doesn't enable it on any platform. The next one will turn it on by default. Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lib/libpayload: Replace strapping_ids with new board configuration entryTim Wawrzynczak2020-10-301-56/+23
| | | | | | | | | | | | | | | | There are currently 3 different strapping ID entries in the coreboot table, which adds overhead. The new fw_config field is also desired in the coreboot table, which is another kind of strapping id. Therefore, this patch deprecates the 3 current strapping ID entries (board ID, RAM code, and SKU ID), and adds a new entry ("board_config") which provides board ID, RAM code, SKU ID, as well as FW_CONFIG together. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1ecec847ee77b72233587c1ad7f124e2027470bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/46605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* drivers/smmstore: Implement SMMSTORE version 2Patrick Rudolph2020-10-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMMSTORE version 2 is a complete redesign of the current driver. It is not backwards-compatible with version 1, and only one version can be used at a time. Key features: * Uses a fixed communication buffer instead of writing to arbitrary memory addresses provided by untrusted ring0 code. * Gives the caller full control over the used data format. * Splits the store into smaller chunks to allow fault tolerant updates. * Doesn't provide feedback about the actual read/written bytes, just returns error or success in registers. * Returns an error if the requested operation would overflow the communication buffer. Separate the SMMSTORE into 64 KiB blocks that can individually be read/written/erased. To be used by payloads that implement a FaultTolerant Variable store like TianoCore. The implementation has been tested against EDK2 master. An example EDK2 implementation can be found here: https://github.com/9elements/edk2-1/commit/eb1127744a3a5d5c8ac4e8eb76f07e79c736dbe2 Change-Id: I25e49d184135710f3e6dd1ad3bed95de950fe057 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40520 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* lib/coreboot_table: Add Intel FSP version to coreboot tableJohnny Lin2020-07-041-0/+7
| | | | | | | | | | | | | | | | | Add a new LB_TAG_PLATFORM_BLOB_VERSION for FSP version, it would add Intel FSP version to coreboot table LB_TAG_PLATFORM_BLOB_VERSION when PLATFORM_USES_FSP2_0 is selected. Tested=On OCP Delta Lake, with an updated LinuxBoot payload cbmem utility can see "LB_TAG_PLATFORM_BLOB_VERSION": "2.1-0.0.1.120" Change-Id: I92a13ca91b9f66a7517cfd6784f3f692ff34e765 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* src/lib: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-041-14/+2
| | | | | | | | | | Done with sed and God Lines. Only done for C-like code for now. Change-Id: Id3a0b63272ebda3dad13803700bcff36d36f4815 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40054 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* src (minus soc and mainboard): Remove copyright noticesPatrick Georgi2020-03-171-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | They're listed in AUTHORS and often incorrect anyway, for example: - What's a "Copyright $year-present"? - Which incarnation of Google (Inc, LLC, ...) is the current copyright holder? - People sometimes have their editor auto-add themselves to files even though they only deleted stuff - Or they let the editor automatically update the copyright year, because why not? - Who is the copyright holder "The coreboot project Authors"? - Or "Generated Code"? Sidestep all these issues by simply not putting these notices in individual files, let's list all copyright holders in AUTHORS instead and use the git history to deal with the rest. Change-Id: I89b10076e0f4a4b3acd59160fb7abe349b228321 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* treewide: Capitalize 'CMOS'Elyes HAOUAS2020-02-241-1/+1
| | | | | | | | | Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Peter Lemenkov <lemenkov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* printf: Automatically prefix %p with 0xJulius Werner2019-12-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the POSIX standard, %p is supposed to print a pointer "as if by %#x", meaning the "0x" prefix should automatically be prepended. All other implementations out there (glibc, Linux, even libpayload) do this, so we should make coreboot match. This patch changes vtxprintf() accordingly and removes any explicit instances of "0x%p" from existing format strings. How to handle zero padding is less clear: the official POSIX definition above technically says there should be no automatic zero padding, but in practice most other implementations seem to do it and I assume most programmers would prefer it. The way chosen here is to always zero-pad to 32 bits, even on a 64-bit system. The rationale for this is that even on 64-bit systems, coreboot always avoids using any memory above 4GB for itself, so in practice all pointers should fit in that range and padding everything to 64 bits would just hurt readability. Padding it this way also helps pointers that do exceed 4GB (e.g. prints from MMU config on some arm64 systems) stand out better from the others. Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: David Guckian
* lib/coreboot_table: Add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot tableYu-Ping Wu2019-12-021-22/+1
| | | | | | | | | | | | | | | | | | | | Since struct vb2_shared_data already contains workbuf_size and vboot_workbuf_size is never used in depthcharge, remove it from struct sysinfo_t. In addition, remove lb_vboot_workbuf() and add CBMEM_ID_VBOOT_WORKBUF pointer to coreboot table with add_cbmem_pointers(). Parsing of coreboot table in libpayload is modified accordingly. BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot libpayload depthcharge; Akali booted correctly Change-Id: I890df3ff93fa44ed6d3f9ad05f9c6e49780a8ecb Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
* security/vboot: Remove struct vboot_working_dataYu-Ping Wu2019-12-021-6/+4
| | | | | | | | | | | | | | | | | | | | After CB:36808, CB:36844 and CB:36845, all fields except buffer_offset were removed from struct vboot_working_data. Since buffer_offset is used to record the offset of the workbuf relative to the whole structure, it is no longer needed. This patch removes the structure, and renames vboot_get_working_data() to vboot_get_workbuf(). BRANCH=none BUG=chromium:1021452 TEST=emerge-nami coreboot Change-Id: I304a5e4236f13b1aecd64b88ca5c8fbc1526e592 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
* cbfs: switch to region_device for location APIsAaron Durbin2019-11-201-4/+4
| | | | | | | | | | | | | | | Drop struct cbfs_props and replace with struct region_device object. The goal of the cbfs locator APIs are to determine the correct region device to find the cbfs files. Therefore, start directly using struct region_device in the cbfs location paths. Update the users of the API and leverage the default boot region device implementation for apollolake. Change-Id: I0158a095cc64c9900d8738f8ffd45ae4040575ea Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* security/vboot: Remove buffer_size from struct vboot_working_dataYu-Ping Wu2019-11-201-1/+8
| | | | | | | | | | | | | | | Since buffer_size is no longer used, remove it from struct vboot_working_data. BRANCH=none BUG=chromium:1021452 TEST=emerge-kukui coreboot Change-Id: Ie770e89b4a45e0ec703d5bbb8fb6a298ce915056 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* fmap: Add get_fmap_flash_offset()Furquan Shaikh2019-09-271-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CB:35377 changed the behavior of find_fmap_directory() to return pointer to CBMEM_ID_FMAP if fmap is cached in cbmem. lb_boot_media_params() calls find_fmap_directory to add offset of fmap in flash to coreboot table. However, because of the change in behavior of find_fmap_directory(), it ended up adding 0 as the offset. This change adds a new function get_fmap_flash_offset() which returns the offset of fmap in flash. Ideally, all payloads should move to using the FMAP from CBMEM. However, in order to maintain compatibility with payloads which are not updated, ensure that fmap_offset is updated correctly. Since find_fmap_directory() is no longer used outside fmap.c, this change also removes it from fmap.h and limits scope to fmap.c. In a follow up patch, we need to push a change to libpayload to expose the fmap cache pointer to lib_sysinfo. BUG=b:141723751 Change-Id: I7ff6e8199143d1a992a83d7de1e3b44813b733f4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35639 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com>
* lib/fmap: Cache FMAP in cbmemPatrick Rudolph2019-09-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | For platform independend exposure of FMAP through a kernel module cache the FMAP in CBMEM. In addition add a pointer in coreboot tables pointing to the introduced CBMEM area. To not waste the allocated DRAM, use the cached CBMEM in RAM enabled stages if possible. Tested on qemu using https://github.com/9elements/linux/commits/google_firmware_fmap2 Tested on QEMU and Supermicro X11SSH-TF. Change-Id: I4e01c573c3edfa34dbba5fe7604d4f6e18b584d5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Julius Werner <jwerner@chromium.org>
* lib/coreboot_table: Show splashscreen in lb_table_initJohanna Schander2019-09-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | Every vga init implementation needs to cache the framebuffer state to be able to fill the lb_framebuffer struct later on in the fill_lb_framebuffer call. Showing the bootsplash afterwards guarantees to have the same interface into all the vga drivers. This is by far from ideal, as it only allows for a single driver at compile-time and should be adapted in the future. It was tested on the wip razer blade stealth using vgabios @ 1280x1024 and also in Qemu @ 1280x1024. By default the qemu framebuffer will be initialized in 800x600@32. This can be overwriten by configuration by setting CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_{X,Y}RES . Change-Id: I4bec06d22423627e8f429c4b47e0dc9920f1464e Signed-off-by: Johanna Schander <coreboot@mimoja.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* vboot: deprecate vboot_handoff structureJoel Kitching2019-07-231-19/+0
| | | | | | | | | | | | | | | | vboot_handoff is no longer used in coreboot, and is not needed in CBMEM or cbtable. BUG=b:124141368, b:124192753 TEST=make clean && make runtests BRANCH=none Change-Id: I782d53f969dc9ae2775e3060371d06e7bf8e1af6 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33536 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* commonlib: fix typo LB_TAB_* (instead of LB_TAG_*)Patrick Georgi2019-05-291-2/+2
| | | | | | | | | | Also adapt all users of these symbols Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
* coreboot_tables: pass the early_mmc_wake_hw status to payloadBora Guvendik2019-05-231-0/+19
| | | | | | | | | | | | | | | | Pass the return value from early_mmc_wake_hw() to the payload so that payload can skip sending CMD0 and resetting the card in case of success or in case of a failure in firmware, payload can recover by sending CMD0 and resetting the card. BUG=b:78106689 TEST=Boot to OS Change-Id: Ia4c57d05433c3966118c3642913d7017958cce55 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/25464 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vboot: make vboot workbuf available to payloadJoel Kitching2019-03-191-8/+22
| | | | | | | | | | | | | | | | | | | | Create a new cbtable entry called VBOOT_WORKBUF for storing a pointer to the vboot workbuf within the vboot_working_data structure. BUG=b:124141368, b:124192753 TEST=Build and deploy to eve TEST=util/lint/checkpatch.pl -g origin/master..HEAD TEST=util/abuild/abuild -B -e -y -c 50 -p none -x BRANCH=none Change-Id: Id68f43c282939d9e1b419e927a14fe8baa290d91 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31887 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-081-14/+14
| | | | | | | | | | | | This patch is a raw application of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Move compiler.h to commonlibNico Huber2018-10-081-1/+0
| | | | | | | | | | | | | | | Its spreading copies got out of sync. And as it is not a standard header but used in commonlib code, it belongs into commonlib. While we are at it, always include it via GCC's `-include` switch. Some Windows and BSD quirk handling went into the util copies. We always guard from redefinitions now to prevent further issues. Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbtable: remove chromeos_acpi from cbtableJoel Kitching2018-08-221-16/+0
| | | | | | | | | | | | | | | | Since we can derive chromeos_acpi's location from that of ACPI GNVS, remove chromeos_acpi entry from cbtable and instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET. BUG=b:112288216 TEST=None CQ-DEPEND=CL:1179725 Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9 Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/28190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbmem: rename vdat to chromeos_acpiJoel Kitching2018-08-141-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is a confusingly named section in cbmem called vdat. This section holds a data structure called chromeos_acpi_t, which exposes some system information to the Chrome OS userland utility crossystem. Within the chromeos_acpi_t structure, there is a member called vdat. This (currently) holds a VbSharedDataHeader. Rename the outer vdat to chromeos_acpi to make its purpose clear, and prevent the bizarreness of being able to access vdat->vdat. Additionally, disallow external references to the chromeos_acpi data structure in gnvs.c. BUG=b:112288216 TEST=emerge-eve coreboot, run on eve CQ-DEPEND=CL:1164722 Change-Id: Ia74e58cde21678f24b0bb6c1ca15048677116b2e Signed-off-by: Joel Kitching <kitching@google.com> Reviewed-on: https://review.coreboot.org/27888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-01 18:10:03 +0000