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* mb/google/*: Replace use of gfx/generic addr field with display typeMatt DeVillier2024-02-131-1/+1
| | | | | | | | | | | | | | | Eliminates the use of a magic number, and the resulting DID entry in the _DOD method is the same. TEST=build/boot google/drallion, dump SSDT and verify DID entry is unchanged. Change-Id: Ic929cf7ec6849ba398653226bbe46d27b4e3fa81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/hatch/var/jinlon: Ensure LCD backlight controls generatedMatt DeVillier2024-02-132-1/+9
| | | | | | | | | | | | | | | | | | Jinlon disables the eps device if no privacy screen is present, so add a second generic gfx device 'no_eps' to handle that case, so that ACPI backlight controls are generated either way. Add logic to ensure only one of the two devices is active. TEST=build/boot Win11 on google/hatch (jinlon), ensure LCD backlight controls present and functional on device both with and without a privacy screen. Change-Id: Icf20de97d26c8be76c84e87d5dc6ed1a4b6dbfbc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80178 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/var/jinlon: Use name 'LCD0' for internal panel outputMatt DeVillier2024-02-131-1/+1
| | | | | | | | | | | | | | | | The GMA driver generates the brightness controls expecting the name LCD0, so we need to use it here as well so that the DSDT and SSDT parts match. TEST=build/boot Win11 on google/hatch (jinlon), verify LCD brightness controls are functional. Change-Id: I4204a518876bed38584260f7566d4d6c9aaa042f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80177 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/gale to nyan_blaze: Rename Makefiles from .inc to .mkMartin Roth2024-01-2411-0/+0
| | | | | | | | | | | | | | | | The .inc suffix is confusing to various tools as it's not specific to Makefiles. This means that editors don't recognize the files, and don't open them with highlighting and any other specific editor functionality. This issue is also seen in the release notes generation script where Makefiles get renamed before running cloc. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I92f8bd7e1c9fc6e4120fb94c2299a266304e19de Reviewed-on: https://review.coreboot.org/c/coreboot/+/80107 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/var/jinlon: Increase reset deassert delay to 4 msEran Mitrani2023-12-191-1/+1
| | | | | | | | | | | | | | | | | With 1ms delay, reset is de-asserted too soon, before power is fully up, causing a glitch to the reset signal. The issue is resolved with 4ms delay. TEST=tested on google/jinlon device and observed the issue is resolved. BUG=b:260253945 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Shelley Chen <shchen@google.com>
* mb/google: Reduce DA7219 mic detect threshold to 200ohmTerry Cheong2023-12-152-2/+2
| | | | | | | | | | | | | | | | | The original DA7219 is designed to use a 500ohm mic detection threshold. Some headset mics (e.g. Logitech H111) have a lower DC impedance that is lower than the threshold and thus cannot be detected. Lower the threshold to 200ohm to match the new default value provided by Renasas as in https://patchwork.kernel.org/project/alsa-devel/patch/20231201042933.26392-1-David.Rau.opensource@dm.renesas.com/ to support such headsets. BUG=b:314062160,b:308207450 Change-Id: I6415e84a4622e0c61bc74b94536fe734048a043f Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/hatch: Change WiFi device type from PCI to genericMatt DeVillier2023-11-011-1/+1
| | | | | | | | | | | | | | | | Change the WiFi device type to generic, so that the LPI constraint generator does not create a reference for a device which does not exist in ACPI (SB.PCI0.RP14.MCHC). The invalid reference causes a Windows BSOD. TEST=build/boot Win11 on google/hatch (akemi) Change-Id: Ieab0722a81f0952bb5b6df8e60c4d684ff455418 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78543 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/var/*: Mark fingerprint reader as hiddenMatt DeVillier2023-10-317-7/+7
| | | | | | | | | | | | | | | | Windows doesn't have / will likely never have a signed driver for the FPR, so set the device status as hidden so it will not appear as an unknown device in Windows Device Manager. Linux does not check/care about the ACPI device status. TEST=build/boot Win11 on google/hatch (jinlon), verify FPR does not show up as unknown device under Device Manager. Change-Id: Ia4a908afdabad0ae8db45c4731a00c9cb17b42bb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/hatch/var/palkia: Use chipset devicetree referencesMatt DeVillier2023-10-301-22/+18
| | | | | | | | | | Switch palkia overridetree to use chipset devicetree references. Change-Id: Ic5fd2d139d22824d3ada09325022c37e69b5e2a9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/hatch/var/nightfury: Use chipset devicetree referencesMatt DeVillier2023-10-301-63/+23
| | | | | | | | | | | Switch nightfury overridetree to use chipset devicetree references. Drop USB port overrides which are identical to the baseboard. Change-Id: I9bb028ad12b97fd4510f6d1026fdc16232c64dba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78570 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/var/mushu: Use chipset devicetree referencesMatt DeVillier2023-10-301-13/+13
| | | | | | | | | | Switch mushu overridetree to use chipset devicetree references. Change-Id: Iac05b0b2c5785f2cb69a29aa4d4c3088f164385f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78568 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/hatch/var/kohaku: Use chipset devicetree referencesMatt DeVillier2023-10-301-59/+26
| | | | | | | | | | | Switch kohaku overridetree to use chipset devicetree references. Drop USB port overrides which are identical to the baseboard. Change-Id: Idcfde6882fc433e6a248aff6baf23b1a5bf7d201 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/hatch/var/*: Disable unused device in SerialIO cfgMatt DeVillier2023-10-2711-27/+30
| | | | | | | | | | | | | | | For variants without a digitizer, disable I2C2. For variants without a proximity sensor, disable I2C3. For variants without a fingerprint reader, disable SPI1. For all variants, disable I2C5 as it is unused. Adjust comment blocks as needed. Change-Id: I27e9eb2b0dcc869d1964c0b17c656d6691c0f05e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78553 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/var/jinlon: Use chipset devicetree referencesMatt DeVillier2023-10-271-17/+17
| | | | | | | | | | Switch jinlon overridetree to use chipset devicetree references. Change-Id: I663a1d051d287f8484c5d4d175337f4f24081044 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/hatch/var/kindred: Use chipset devicetree referencesMatt DeVillier2023-10-271-10/+10
| | | | | | | | | | Switch kindred overridetree to use chipset devicetree references. Change-Id: I2c54406948d2db53d25aa7c3dc79cfb5661c4a69 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78564 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/baseboard: Use chipset devicetree referencesMatt DeVillier2023-10-261-72/+35
| | | | | | | | | | | | | | | Switch baseboard devicetree to use chipset devicetree references. Drop any devices whose status (on/off/hidden) matches the default in the chipset DT. TEST=build/boot google/hatch (akemi) Change-Id: I5954c304f3c0e04be7e061c1c23a278f81b6ff4d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mb/google/hatch/var/helios_diskswap: Use chipset devicetree referencesMatt DeVillier2023-10-261-21/+16
| | | | | | | | | | | Switch helios_diskswap overridetree to use chipset devicetree references. Change-Id: I0a3385139c74a59c2006b8963850d00ee39f70a8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78560 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/hatch/var/helios: Use chipset devicetree referencesMatt DeVillier2023-10-261-17/+14
| | | | | | | | | | Switch helios overridetree to use chipset devicetree references. Change-Id: If7901066a0c77231779eb298dc40962d8ac62814 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/hatch/var/hatch: Use chipset devicetree referencesMatt DeVillier2023-10-261-13/+13
| | | | | | | | | | Switch hatch overridetree to use chipset devicetree references. Change-Id: Icccb433ba3e5a1ecb192f8db830674047e801623 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/hatch/var/dratini: Use chipset devicetree referencesMatt DeVillier2023-10-261-14/+14
| | | | | | | | | | Switch dratini overridetree to use chipset devicetree references. Change-Id: I9f365077291ee9fa5f4dcf8835756f4cfd6eeab4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
* mb/google/hatch/var/akemi: Use chipset devicetree referencesMatt DeVillier2023-10-261-68/+18
| | | | | | | | | | | | | Switch akemi overridetree to use chipset devicetree references. Drop USB port overrides which are identical to the baseboard. TEST=build/boot google/hatch (akemi) Change-Id: Ic25fbe4a634f8166047107a33c9fcee764f1159a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78552 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch: Default native SD card interface to off in baseboardMatt DeVillier2023-10-2412-12/+9
| | | | | | | | | | | | | | Default SD card interface (PCI 14.5) to off in the baseboard, and have all variants which use it enable it in their override tree. This will allow for simplification when moving to using the chipset devicetree references in a later patch. Change-Id: I6e1230045f54e0fee376f5eeeca9da4fb9d5f6c4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
* mb/google/hatch: Default I2C3 (proximity sensor) to off in baseboardMatt DeVillier2023-10-248-15/+1
| | | | | | | | | | | | | | Default I2C3 (proximity sensor) to off in baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it (the majority) to drop it from their override trees. Change-Id: If17cb4538a7f64d019e4e28285fb8977de72252f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yuchen He <yuchenhe126@gmail.com>
* mb/google/hatch: Default I2C2 (digitizer) to off in baseboardMatt DeVillier2023-10-2410-15/+1
| | | | | | | | | | | | | | Default I2C2 (digitizer) to off in the baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it (the majority) to drop it from their override trees. Change-Id: Ife42a6b849278362c1951b80b7a95363e68a2541 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78548 Reviewed-by: Yuchen He <yuchenhe126@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
* mb/google/hatch: Default GSPI1 (FPR) to off in baseboardMatt DeVillier2023-10-245-6/+1
| | | | | | | | | | | | | | Default GSPI1 (fingerprint reader) to off in baseboard, since all variants which use one already enable it in their override tree. This allows variants which do not use it to drop it from their override trees. Change-Id: I07979e35b67635ceadd3906e37de177dd081d35a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78547 Reviewed-by: Yuchen He <yuchenhe126@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/jinlon: Add HID to gfx ACPI nodeKornel Dulęba2023-05-221-0/+2
| | | | | | | | | | | | | | | | | | The upstream kernel privacy screen driver uses HID GOOG0010 to look for firmware node to use. This method is used on other boards, e.g. redrix. See: drivers/platform/chrome/chromeos_privacy_screen.c in linux sources. Update jinlon gfx ACPI node to work with that. BUG=b:279092050 TEST=privacy protection screen works with 5.15 and 4.19 kernels Change-Id: Icba41e7f2be7292f713fea10dbe69b3ca128bde7 Signed-off-by: Kornel Dulęba <korneld@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75289 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/hatch: Add SOF chip driverMatt DeVillier2023-05-0311-1/+72
| | | | | | | | | | | | | | | Add SOF chip driver entries for all variants, so that the correct audio config is passed to the OS drivers. TEST=build, boot Windows on several hatch variants, verify audio functional under Windows using coolstar's SOF drivers. Change-Id: Ie791fa873fc7bbab84644f5ea5743bdcdc124908 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/google/hatch: drop include for puff baseboardMatt DeVillier2023-02-141-59/+0
| | | | | | | | | | | | | | | | Commit 45b1da33c80a ("mb/google/hatch: split up hatch and puff baseboards") moved puff out from under hatch into its own mainboard dir, but this basebaord include was left behind. Delete it as it's not needed. TEST=build hatch variants Change-Id: I9045c52006fd232552541d68972d831c8b52da27 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/hatch/kohaku: Fix touchscreen power sequencingMatt DeVillier2023-02-101-1/+1
| | | | | | | | | | | | | | | | | | Commit 525c61f74e94 ("mb/google/hatch: Implement touchscreen power sequencing") contained a copy/paste error; KOHAKU's enable GPIO is set twice in ramstage, and the reset GPIO not at all, leading the touchscreen to not be detected. Correct the copy/paste error by replacing the 2nd instance of GPP_C12 with GPP_D15. TEST=build/boot Windows/Linux on KOHAKU, verify touchscreen works. Change-Id: I08d35f1e2a951cdaa463daa34df2134fdc8c65c8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/*: Remove lapic from devicetreeArthur Heymans2023-01-301-3/+1
| | | | | | | | | | | | The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* drivers/i2c/generic: Drop 'disable_gpio_export_in_crs' flagMatt DeVillier2023-01-154-4/+0
| | | | | | | | | | | | | | | | | | | | | | | Exposing the GPIOs via an ACPI PowerResource and the _CRS results in the OS driver and ACPI thinking they own the GPIO. This can cause timing problems because it's not clear which system should be controlling the GPIO. Previously, we flagged as an error any device which set the 'has_power_resource' flag but did not set 'disable_gpio_export_in_crs.' There's no reason to require explicit disablement however, so drop the superfluous 'disable' flag, and change the _CRS generation to check if the GPIOs will be exported via the 'has_power_resource' flag instead. BUG=b:265055477 TEST=build/boot skyrim, dump SSDT and verify touchscreen GPIOs only listed under PRx, not under _CRS. Change-Id: I837ae6c6fe4b8e1c4e10686406cba06bdb7759d2 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
* mainboard: Remove duplicated <soc/gpio.h>Elyes Haouas2023-01-137-7/+0
| | | | | | | | | | <gpio.h> chain-include <soc/gpio.h>. Change-Id: Ia57d5cd33c70b6a755babd4db56c64c0e3666f9f Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/hatch: Use runtime detection for touchscreens/digitizersMatt DeVillier2022-12-2311-24/+24
| | | | | | | | | | | | | | | | | | Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple hatch variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I2eae486eaa5e42cfe42ecc066a58b09fe2bd9138 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71062 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier2022-12-2311-18/+18
| | | | | | | | | | | | | The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I580348d0aabb24f0241d6e9992c5a17942bd57ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/hatch/*: Add missing enable GPIO for ELAN touchscreensMatt DeVillier2022-12-233-0/+9
| | | | | | | | | | | | | | | Some ELAN touchscreens were missing the entries for the enable GPIO and associated delays. Add them to variants with ELAN0001 touchscreens missing the entries. TEST=tested with rest of patch train Change-Id: I9ce81ad6ee8183c522d05fbe3f57af87e5895df3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* mb/google/hatch: Implement touchscreen power sequencingMatt DeVillier2022-12-2310-3/+203
| | | | | | | | | | | | | | | | For touchscreens on hatch variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I86c5f41b7820eaf5252c276ae854a4206e09385f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71059 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch: Add method to set GPIOs in romstageMatt DeVillier2022-12-232-0/+9
| | | | | | | | | | | | | | | Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: I1939387b5bb98d6d282fd044e9ce8780dbe0d2c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/hatch: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier2022-12-223-3/+6
| | | | | | | | | | | | | | | | The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on akemi/kohaku, verify all touchpad functions work correctly. Change-Id: Icb552caa69428908e5e3342139b578a145fa2797 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/hatch/kohaku: set VBT boot resolution to 1080pMatt DeVillier2022-12-191-0/+0
| | | | | | | | | | | | | Boot menus are too small at native 4K res on some panels, so set fixed display resolution to 1920x1090p TEST=build/boot KOHAKU with 4K display, verify boot menu text legible. Change-Id: I82563c83de7ab302151f60d86b8a6824330d03ea Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mb/google/hatch/dratini: increase power enable to reset deassert delayEran Mitrani2022-12-141-1/+1
| | | | | | | | | | | | | | | With 1ms delay, reset is de-asserted too soon, before power is fully up, causing a glitch to the reset signal. The issue is resolved with 4ms delay. TEST=tested on dratini device and observed the issue is resolved. BUG=b:260253945 Change-Id: I5c3edbc6ac90d5042c2d3c5b01573d4bb1ea676d Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70666 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch/var/kohaku: ensure FPMCU is power cycled on resetTarun Tuli2022-11-022-3/+18
| | | | | | | | | | | | | | | | | | | | | | Leakage from the SPI CS line onto the FPMCU VDD rail was preventing the FPMCU from fully shutting down on AP reset. Instead of simply turning off the power rail, now ensure the CS line is not driven high until late in coreboot. This ensures it is completely off for the requisite minimum of 200ms (now measured at approx 1100ms). BUG=b:245953688 TEST=Confirmed FPMCU is still functional on Kohaku. Confirmed FpRebootPowerCycle unit test now passes BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1e7e32f61c3ac1b3154d42821cc1dd4c5d3de303 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68819 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch: Add variant finalize support for hatch devicesTarun Tuli2022-11-022-0/+13
| | | | | | | | | | | | | | | Provide a variant_finalize() method and call to be invoked from mainboard_ops.final BUG=b:245953688 TEST=Hatch and variants build BRANCH=Hatch Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I9253ed4be1b08d0c7f65526c9b26dbcd00ffccc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68821 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mainboard/google: Remove ACPI ALS deviceGwendal Grignou2022-10-181-3/+0
| | | | | | | | | | | | | | | | | | | Remove the ACPI ALS device from the EC configuration for newer devices, because some do not have light sensors, and those who do have their ALS presented through the new EC sensor interface already. Inspired from commit ("f13e2501525f ("UPSTREAM: mainboard/google/eve: Remove ACPI ALS device") BUG=b:253967865 BRANCH=none TEST=Boot a device and ensure that 'acpi-als' device is not present in /sys/bus/iio/devices. Change-Id: Ibcfa9e8c5a4679d557150998fd255789d3f8a272 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68493 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/hatch: split up hatch and puff baseboardsMatt DeVillier2022-09-2264-7431/+0
| | | | | | | | | | | | | | | | | The hatch and puff baseboards have diverged enough to where it makes more sense to split them into separate boards. Copy the mb/google/hatch directory into a new dir 'puff' and strip out all boards and items related to the hatch baseboard. Remove all puff-related items from the original hatch directory. Clean up and alphabetize Kconfig selections. Test: build and boot akemi hatch variant and wyvern puff variant. Change-Id: I8c7350f3afcff3ddefc6fa14054a3f9257568cd3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62970 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* timer: Change timer util functions to 64-bitRob Barnes2022-09-141-1/+1
| | | | | | | | | | | | | | | | | | | | Since mono_time is now 64-bit, the utility functions interfacing with mono_time should also be 64-bit so precision isn't lost. Fixed build errors related to printing the now int64_t result of stopwatch_duration_[m|u]secs in various places. BUG=b:237082996 BRANCH=All TEST=Boot dewatt Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/*/{device,override}tree: Set touchpads to use detect (vs probed) flagMatt DeVillier2022-09-096-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, ChromeOS devices have worked around the problem of OEMs using several different parts for touchpads/touchscreens by using a ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel) to indicate that the device may or may not be present, and that the driver should probe to confirm device presence. Since c636142b, coreboot now supports detection for i2c devices at runtime when creating the device entries for the ACPI/SSDT tables, rendering the 'probed' flag obsolete for touchpads. Switch all touchpads in the tree from using the 'probed' flag to the 'detect' flag. Touchscreens require more involved power sequencing, which will be done at some future time, after which they will switch over as well. TEST: build/boot at least one variant for each baseboard in the tree. Verify touchpad works under Linux and Windows. Verify only a single touchpad device is present in the ACPI tables. Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ChromeOS: Add DECLARE_x_CROS_GPIOS()Kyösti Mälkki2022-04-071-5/+1
| | | | | | | | Change-Id: I88406fa1b54312616e6717af3d924436dc4ff1a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* ChromeOS: Promote variant_cros_gpio()Kyösti Mälkki2022-04-061-4/+0
| | | | | | | | | | | | | | | | The only purpose of mainboard_chromeos_acpi_generate() was to pass cros_gpio array for ACPI \\OIPG package generation. Promote variant_cros_gpio() from baseboards to ChromeOS declaration. Change-Id: I5c2ac1dcea35f1f00dea401528404bc6ca0ab53c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/hatch/moonbuggy: Update GPIOsPablo Ceballos2022-03-273-40/+59
| | | | | | | | | | | | | | | | | | | | | Implement the GPIOs that have been changed from genesis. - Connect scaler UART on pins C12/C13 - Connect the HDMI redriver I2C on C18/C19 - Connect the iMX8 signals on D1/D2/D3/D21/D22 - Connect the EC interrupt on D14 (same as on scout) - Connect PCH_TYPEC_UPFB on E15 (same as on genesis) - Configure as not connected the following unused pins: D23, E11, E12, F11 -> F22, H0, H8, H9 BUG=b:200876872 TEST=moonbuggy boots Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Signed-off-by: Pablo Ceballos <pceballos@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/hatch/var/jinlon: Fix EPS detection and disablementMatt DeVillier2022-03-072-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ebf14826 [mb/google/hatch/var/jinlon: Switch to using device pointers] broke jinlon boards without an electronic privacy screen (EPS) by disabling the parent device (iGPU) instead of the EPS when determined to be not present via SKU ID. Commit c5a3a4a6 [mb/google/hatch (baseboard): add ACPI backlight support] broke EPS detection by adding a duplicate iGPU device to the devicetree, resulting in the EPS entry being skipped. Fix both of these issues by assigning the device alias to the EPS child device, not the parent (iGPU). Rename the alias for clarity, and combine the duplicate device definitions for the iGPU. Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional in both firmware boot screens and Linux OS. Change-Id: I0615ce361497abe6872085b0dec83292607e53dd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-26 00:43:33 +0000