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Commit message (Expand)AuthorAgeFilesLines
* mb/siemens/chili: Drop redundant Kconfig selectAngel Pons2021-10-271-1/+0
* mb/siemens/mc_ehl2: Adjust PCH serial IO settingsMario Scheithauer2021-10-141-17/+6
* mb/siemens/mc_ehl2: Adjust USB settingsMario Scheithauer2021-10-141-12/+12
* mb/siemens/mc_ehl2: Enable PCI devicesMario Scheithauer2021-10-141-4/+4
* mb/siemens/mc_ehl2: Set coreboot ready LEDMario Scheithauer2021-10-141-0/+11
* mb/siemens/mc_ehl: Remove unneeded 'half_populated' variableWerner Zeh2021-10-121-4/+1
* mb/siemens/mc_ehl: Use SPD data from HW-Info in the first placeWerner Zeh2021-10-121-3/+22
* mb/siemens/mc_ehl2: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer2021-10-112-0/+14
* mb/siemens/mc_ehl: Add variant_mainboard_final()Mario Scheithauer2021-10-112-0/+11
* mb/siemens/mc_ehl2: Enable LPC ComBMario Scheithauer2021-10-111-0/+1
* mb/siemens/mc_ehl2: Disable INTEL_LPSS_UART_FOR_CONSOLEMario Scheithauer2021-10-111-1/+0
* mb/siemens/mc_ehl2: Adjust GPIOsMario Scheithauer2021-10-111-54/+35
* mb/siemens/mc_ehl2: Disable SATA Port 0Mario Scheithauer2021-10-111-1/+1
* mb/siemens/mc_ehl2: Enable SD-CardMario Scheithauer2021-10-111-1/+1
* mb/siemens/mc_ehl2: Move RTC RX6110SA from SMBus to I2C2Mario Scheithauer2021-10-111-17/+23
* mb/siemens/mc_ehl2: Update SPD for DDR4 devicesMario Scheithauer2021-10-111-3/+3
* mb/siemens/mc_ehl: Move UART_FOR_CONSOLE switch to variant levelWerner Zeh2021-10-013-5/+8
* mb/siemens/mc_ehl: Add a new variant mc_ehl2Werner Zeh2021-10-0110-0/+605
* mb/siemens/mc_ehl1: Enable LPSS UARTWerner Zeh2021-10-011-0/+1
* src/*: Specify type of `DIMM_SPD_SIZE` onceAngel Pons2021-09-031-1/+0
* soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by defaultFelix Singer2021-08-283-12/+0
* mb/{kontron/bsl6,siemens/chili}: Add `inhibit_flashlock` nvram optionNico Huber2021-08-131-0/+1
* mb/siemens/mc_ehl: Enable master bit in PCI config space if allowedWerner Zeh2021-08-021-1/+21
* mb/siemens/mc_ehl: Add code to wait for legacy devices before PCI scanWerner Zeh2021-08-021-0/+30
* mb/siemens/mc_ehl1: Disable LTR for all PCIe root portsWerner Zeh2021-07-291-0/+8
* mb/siemens/mc_ehl1: Disable L1 substates for PCIe root portsWerner Zeh2021-07-291-0/+8
* mb/siemens/mc_ehl1: Enable Intel I210 MACPHY driverWerner Zeh2021-07-292-0/+83
* mb/siemens/mc_ehl: Enable Siemens NC-FPGA driverWerner Zeh2021-07-291-0/+2
* mb/siemens/mc_ehl: Enable SIEMENS_HWILIBWerner Zeh2021-07-291-0/+1
* mb/siemens/mc_ehl1: Enable In Band ECCWerner Zeh2021-07-291-0/+6
* mb/siemens/mc_ehl1: Disable System Agent dynamic frequency supportWerner Zeh2021-07-291-1/+1
* mb/siemens/mc_ehl: Enable measured bootWerner Zeh2021-07-291-0/+1
* mb/siemens/mc_ehl: Enable LPC TPMWerner Zeh2021-07-292-1/+7
* mb/siemens/mc_ehl: Add external RTC RX6110SAWerner Zeh2021-07-292-2/+17
* mb/*: Specify type of `VARIANT_DIR` onceAngel Pons2021-07-263-3/+0
* mb/*: Specify type of `FMDFILE` onceAngel Pons2021-07-265-5/+0
* mb/*: Specify type of `DEVICETREE` onceAngel Pons2021-07-263-3/+0
* mb/*: Specify type of `MAINBOARD_PART_NUMBER` onceAngel Pons2021-07-263-3/+0
* mb/*: Specify type of `MAINBOARD_DIR` onceAngel Pons2021-07-263-3/+0
* src/*: Specify type of `CBFS_SIZE` onceAngel Pons2021-07-261-1/+0
* mb/siemens/mc_ehl1: Add GPIO configurationWerner Zeh2021-07-231-256/+154
* mb/siemens/mc_ehl1: Remove SD-Card card detect GPIO in devicetreeWerner Zeh2021-07-231-3/+0
* mb/siemens/mc_apl{1,2,3,5,6}: Use PCI_ALLOW_BUS_MASTER_ANY_DEVICEWerner Zeh2021-07-235-5/+5
* mb/siemens/mc_ehl1: Disable GSPI in devicetreeWerner Zeh2021-07-221-27/+3
* mb/siemens/mc_ehl1: Adjust I2C bus enablement in devicetreeWerner Zeh2021-07-221-12/+12
* mb/siemens/mc_ehl1: Disable power management features for SATAWerner Zeh2021-07-221-2/+2
* mb/siemens/mc_ehl1: Adjust PCIe settings in devicetreeWerner Zeh2021-07-221-8/+8
* mb/siemens/mc_ehl1: Adjust USB port settings in devicetreeWerner Zeh2021-07-221-15/+15
* mb/siemens/mc_ehl1: Remove display related UPDs from devicetreeWerner Zeh2021-07-221-7/+0
* mb/siemens/mc_apl{1,2,3,5,6}: Set PCI bus master bit only if allowedWerner Zeh2021-07-215-14/+21
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 03:11:28 +0000