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* device: Use pcidev_on_root()Kyösti Mälkki2019-01-061-2/+2
* arch/x86: Drop spurious arch/stages.h includesKyösti Mälkki2018-12-281-1/+0
* mainboard: Remove useless include <device/pci_ids.h>Elyes HAOUAS2018-12-191-1/+0
* siemens/mc_apl4: Enable RTC RX6110SA on this mainboardUwe Poeche2018-12-172-1/+16
* siemens/mc_apl4: Enable LVDS Display on mc_apl4Uwe Poeche2018-12-174-0/+299
* siemens/mc_apl4: Add GPIO configurationUwe Poeche2018-12-172-0/+392
* cpu/intel/common: Use a common acpi/cpu.asl fileArthur Heymans2018-11-302-2/+2
* siemens/mc_apl5: Disable PCI clock outputs on XIO bridgesMario Scheithauer2018-11-291-5/+16
* siemens/mc_apl5: Set bus master bit for on-board PCI deviceMario Scheithauer2018-11-291-0/+10
* siemens/mc_apl5: Enable SDCARDMario Scheithauer2018-11-291-1/+1
* mb/*/*/Kconfig: Remove useless commentElyes HAOUAS2018-11-281-1/+1
* siemens/mc_apl5: Adjust the settings for the PCIe root portsMario Scheithauer2018-11-271-12/+12
* siemens/mc_apl1/variants/mc_apl*: Remove unneeded PTN readMario Scheithauer2018-11-262-12/+0
* siemens/mc_apl4: Set CPU clock to minimum ratioWerner Zeh2018-11-231-0/+1
* mb: Set coreboot as DSDT's manufacturer model IDElyes HAOUAS2018-11-233-6/+9
* ACPI: Fix DSDT's revision fieldElyes HAOUAS2018-11-213-3/+3
* siemens/mc_apl5: Add new mainboard variant mc_apl5Mario Scheithauer2018-11-188-0/+517
* mb/siemens/mc_apl1/variants/mc_apl*: Remove unused BOARD_SIEMENS_MC_APL*_VARElyes HAOUAS2018-11-164-4/+4
* src: Remove unneeded include <cbfs.h>Elyes HAOUAS2018-11-161-1/+1
* src: Remove unneeded include <lib.h>Elyes HAOUAS2018-11-163-3/+0
* mb/*/*/Kconfig: Use CONFIG_VARIANT_DIR for devicetreePeter Lemenkov2018-11-165-16/+4
* siemens/mc_apl4: Clean up ramstageMario Scheithauer2018-11-163-104/+0
* siemens/mc_apl4: Overwrite swizzle data for LPDDR4Mario Scheithauer2018-11-162-0/+70
* src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS2018-11-121-1/+0
* siemens/mc_apl4: Enable SDCARDMario Scheithauer2018-11-121-1/+1
* siemens/mc_apl4: Remove external RTC from I2C0Mario Scheithauer2018-11-121-21/+7
* siemens/mc_apl4: Enable all PCIe root portsMario Scheithauer2018-11-121-6/+6
* siemens/mc_apl4: Remove reduced clock rate for I2C0Mario Scheithauer2018-11-121-12/+0
* siemens/mc_apl4: Disable CLKREQ of PCIe root portsMario Scheithauer2018-11-121-5/+6
* siemens/mc_apl3: Disable PCI clock outputs on XIO bridgesMario Scheithauer2018-11-121-5/+17
* siemens/mc_apl3: Set Full Reset Bit into Reset Control RegisterMario Scheithauer2018-11-121-0/+8
* siemens/mc_apl3: Set bus master bit for on-board PCI deviceMario Scheithauer2018-11-121-0/+10
* siemens/mc_apl3: Remove the correction of the Tx signal for SATAMario Scheithauer2018-11-121-8/+0
* siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devicesMario Scheithauer2018-11-121-4/+3
* siemens/mc_apl4: Add new mainboard variant mc_apl4Mario Scheithauer2018-11-076-0/+240
* siemens/mc_apl2: Adjust GPIO settings for mc_apl2Mario Scheithauer2018-11-072-0/+687
* siemens/mc_apl3: Disable I2C7 over devicetreeMario Scheithauer2018-11-071-1/+1
* siemens/mc_apl3: Enable all PCIe root portsMario Scheithauer2018-11-071-6/+6
* siemens/mc_apl3: Remove reduced clock rate for I2C0Mario Scheithauer2018-11-071-12/+0
* siemens/mc_apl3: Disable CLKREQ of PCIe root portsMario Scheithauer2018-11-071-4/+4
* siemens/mc_apl3: Adjust GPIO settings for mc_apl3Mario Scheithauer2018-11-072-0/+416
* mainboard: Remove unneeded include <console/console.h>Elyes HAOUAS2018-11-052-2/+0
* siemens/mc_apl3: Add new mainboard variant mc_apl3Mario Scheithauer2018-10-306-0/+240
* src: Remove unneeded whitespaceElyes HAOUAS2018-10-232-14/+14
* mb/*/*: Clean up FADT checksum assignmentJonathan Neuschäfer2018-10-172-6/+2
* Move compiler.h to commonlibNico Huber2018-10-085-5/+0
* soc/intel/common, mb/google, mb/siemens: Use lower case x for RXDFurquan Shaikh2018-10-061-1/+1
* mc_apl1: Set up SPI OPCODE menu before lockingWerner Zeh2018-10-041-0/+55
* siemens/mc_apl1: Activate clock spreading for PTN3460Mario Scheithauer2018-10-011-2/+2
* siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer2018-09-276-1/+197
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