index
:
coreboot.git
24.02_branch
4.1
4.10_branch
4.11_branch
4.12_branch
4.14_branch
4.15_branch
4.16_branch
4.18_branch
4.19_branch
4.2
4.20_branch
4.22_branch
4.3
4.4
4.8_branch
classic-2014.10
coreboot-v1
coreboot-v3
main
master
rampayload
Coreboot firmware sources
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path:
root
/
src
/
soc
/
intel
/
baytrail
/
pcie.c
Commit message (
Expand
)
Author
Age
Files
Lines
*
src: Remove unneeded whitespace
Elyes HAOUAS
2018-10-23
1
-1
/
+1
*
soc/intel/baytrail: Get rid of device_t
Elyes HAOUAS
2018-05-24
1
-9
/
+10
*
src/soc: Add required space before opening parenthesis '('
Elyes HAOUAS
2016-08-31
1
-1
/
+1
*
tree: drop last paragraph of GPL copyright header
Patrick Georgi
2015-10-31
1
-4
/
+0
*
devicetree: Change scan_bus() prototype in device ops
Kyösti Mälkki
2015-06-04
1
-2
/
+2
*
Remove address from GPLv2 headers
Patrick Georgi
2015-05-21
1
-1
/
+1
*
baytrail: fix the coding error on PCIe L1 exit latency
Kevin L Lee
2015-04-10
1
-1
/
+1
*
Baytrail: Prior to PCI scan, wait for LCTL to be active in 50 ms
Kevin Hsieh
2015-04-10
1
-1
/
+14
*
baytrail: Change all SoC headers to <soc/headername.h> system
Julius Werner
2015-04-07
1
-4
/
+4
*
Baytrail: Fix no_dev_behind_port not executed for RP1/2/3.
Kenji Chen
2015-04-04
1
-0
/
+1
*
Baytrail: Change PCIe root disable algorithm
Kenji Chen
2015-04-02
1
-2
/
+37
*
intel/baytrail: Spelling fixes
Martin Roth
2014-12-08
1
-1
/
+1
*
baytrail/rambi: S3 support and other updates
Kein Yuan
2014-10-22
1
-0
/
+6
*
baytrail: utilize reg_script_run_on_dev()
Aaron Durbin
2014-05-10
1
-9
/
+2
*
baytrail: pcie: Root port initialization
Aaron Durbin
2014-05-07
1
-0
/
+230