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path: root/src/soc/intel/cannonlake
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* soc/intel: Remove unused <string.h>Elyes HAOUAS2022-01-051-1/+0
* soc/intel/cannonlake/acpi: Replace Multiply(a,b) with ASL 2.0 syntaxFelix Singer2022-01-012-2/+2
* soc/intel/cannonlake/acpi: Replace Add(a,b) with ASL 2.0 syntaxFelix Singer2021-12-313-4/+3
* soc/intel/cannonlake/acpi: Replace Add(a,b,c) with ASL 2.0 syntaxFelix Singer2021-12-312-2/+2
* soc/intel/cannonlake/acpi: Replace Subtract(a,b,c) with ASL 2.0 syntaxFelix Singer2021-12-302-9/+9
* soc/intel/cannonlake/acpi: Replace LAnd() with ASL 2.0 syntaxFelix Singer2021-12-303-12/+10
* soc/intel/{skl,cnl}: Guard USB macro parametersAngel Pons2021-12-261-1/+1
* soc/intel/cannonlake: Configure common FSP memory settings only onceFelix Singer2021-12-131-2/+2
* soc/intel/cannonlake: Rename SA_DEV_SLOT_DSPFelix Singer2021-12-122-5/+5
* soc/intel/{skylake/cannonlake}: Fix bug in vr_configAngel Pons2021-12-101-1/+1
* soc/intel/common/thermal: Refactor thermal block to improve reusabilitySubrata Banik2021-11-251-1/+1
* soc/intel/cannonlake: Fix PEG1 _PRT generationArthur Heymans2021-11-221-0/+6
* Rename ECAM-specific MMCONF KconfigsShelley Chen2021-11-101-1/+1
* ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki2021-11-091-1/+0
* soc/intel: drop Kconfig `PM_ACPI_TIMER_OPTIONAL`Michael Niewöhner2021-11-081-1/+0
* cpu/x86: Introduce and use `CPU_X86_LAPIC`Felix Held2021-10-261-1/+0
* cpu,soc/x86: always include cpu/x86/mtrr on x86 CPUs/SoCsFelix Held2021-10-251-1/+0
* arch/x86/ioapic: Select IOAPIC with SMPKyösti Mälkki2021-10-221-1/+0
* cpu/x86/mp_init: move printing of failure message into mp_init_with_smmFelix Held2021-10-221-2/+2
* cpu/x86/mp_init: use cb_err as mp_init_with_smm return typeFelix Held2021-10-211-1/+2
* soc/intel: Constify `soc_get_cstate_map()`Angel Pons2021-10-191-1/+1
* soc/intel/*/acpi.c: Don't copy structs with `memcpy()`Angel Pons2021-10-191-1/+1
* soc/intel: transition full control over PM Timer from FSP to corebootMichael Niewöhner2021-10-171-1/+8
* soc/intel/{skl,cnl,dnv}: disable PM ACPI timer if chosenMichael Niewöhner2021-10-171-0/+9
* soc/intel: deduplicate acpi_fill_soc_wakeMichael Niewöhner2021-10-171-15/+0
* soc/intel/cannonlake: Enable Energy/Performance Bias controlAngel Pons2021-10-151-0/+1
* soc/intel/cannonlake: Lock PKG_CST_CONFIG_CONTROL MSRAngel Pons2021-10-121-1/+2
* soc/intel/*/cpu.c: Add missing space in commentAngel Pons2021-10-121-1/+1
* soc/intel/cannonlake: Enable x86_64 supportPatrick Rudolph2021-10-071-0/+1
* src/soc to src/superio: Fix spelling errorsMartin Roth2021-10-051-1/+1
* soc/intel/cannonlake: Guard acpi_fill_ssdt assignment with HAVE_ACPI_TABLESTim Wawrzynczak2021-09-291-2/+4
* soc/intel: Drop unnecessary `select REG_SCRIPT`Angel Pons2021-09-291-1/+0
* soc/intel/{cnl,jsl,tgl,ehl,adl}: rename PMC device init/enable callbacksMichael Niewöhner2021-09-291-4/+4
* soc/intel/cannonlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak2021-09-103-3/+11
* soc/intel/cannonlake: Switch PMC to use device callbacksTim Wawrzynczak2021-09-105-43/+34
* cpu/x86/tsc: Deduplicate Makefile logicAngel Pons2021-09-081-1/+0
* soc/intel/cannonlake: Lock PAM registers in finalizeTim Wawrzynczak2021-09-052-0/+10
* soc/intel/cannonlake: Fix PCH-H IRQ constraintsAngel Pons2021-08-251-0/+6
* soc/intel/cannonlake: Unbreak some short linesNico Huber2021-08-201-6/+3
* Revert "src/soc/intel/cannonlake: Update C-state latency control limits"Nico Huber2021-08-192-12/+17
* soc/intel/cannonlake: Clean up FSP chipset lockdown configurationFelix Singer2021-08-121-27/+12
* Move post_codes.h to commonlib/console/Ricardo Quesada2021-08-041-3/+3
* soc/intel/cannonlake: Allow to configure maximum package C stateNico Huber2021-08-042-2/+21
* soc/intel/cannonlake: Disable `TccOffsetClamp` if no offset is givenNico Huber2021-08-041-0/+1
* soc/intel/cannonlake/vr_config: Print configured valuesNico Huber2021-08-041-0/+14
* soc/intel/cannonlake/vr_config: Add TDC values for CFL-H 6+2Nico Huber2021-08-041-0/+4
* soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes2021-08-031-2/+5
* src/*: Specify type of `CBFS_SIZE` onceAngel Pons2021-07-261-1/+0
* soc/intel/cannonlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik2021-07-171-1/+1
* src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons2021-07-021-1/+0
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