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* src/soc/intel: Add include <types.h>Elyes HAOUAS2020-07-261-1/+1
* soc/intel/common: Only touch Time Window Tau bits in supported SoCsTim Wawrzynczak2020-07-031-1/+9
* soc/intel/common/cpu: Don't set any TCC settings if offset is 0Tim Wawrzynczak2020-07-011-1/+6
* soc/intel/common: add TCC activation functionalitySumeet R Pawnikar2020-06-281-0/+21
* drivers/intel/fsp2_0: decouple FSP_PEIM_TO_PEIM_INTERFACE from FSP 2.1Jonathan Zhang2020-06-251-1/+1
* arch/x86: Remove NO_FIXED_XIP_ROM_SIZEKyösti Mälkki2020-06-151-1/+0
* src: Remove unused 'include <cpu/x86/mtrr.h>'Elyes HAOUAS2020-06-063-3/+0
* soc/intel/tigerlake: Add CPU ID for TGL B0Jamie Ryu2020-06-061-0/+1
* soc/intel/common/block: Remove unused headersAngel Pons2020-06-011-4/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-116-6/+0
* treewide: replace GPLv2 long form headers with SPDX headerPatrick Georgi2020-05-061-12/+1
* treewide: Move "is part of the coreboot project" line in its own commentPatrick Georgi2020-05-061-2/+1
* acpi: Move ACPI table support out of arch/x86 (3/5)Furquan Shaikh2020-05-021-1/+1
* src: Remove unused 'include <cpu/x86/cache.h>'Elyes HAOUAS2020-05-011-1/+0
* soc/intel/common: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-065-68/+10
* soc: Remove copyright noticesPatrick Georgi2020-03-186-8/+0
* soc/intel/cpu: Select NO_FIXED_XIP_ROM_SIZEArthur Heymans2020-03-041-0/+1
* soc/intel/common: Update Jasper Lake Device IDsMeera Ravindranath2020-02-251-0/+1
* soc/intel: Remove duplicate CPUID entrySubrata Banik2020-02-041-1/+0
* soc/intel/common: Add Elkhartlake Device IDsTan, Lean Sheng2020-01-221-0/+1
* src/soc/intel: Add Cometlake-S and CMP-H skusGaggery Tsai2019-12-021-1/+3
* soc/intel/common: Make alignment proper for commentsSubrata Banik2019-11-151-1/+1
* arch/x86/car.ld: Rename suffix _start/_endArthur Heymans2019-11-121-1/+1
* soc/intel/common: Make native and FSP-T CAR init mutually exclusiveArthur Heymans2019-11-061-7/+7
* soc/intel/common: Include Tigerlake device IDsRavi Sarawadi2019-11-051-0/+1
* soc/intel/common: Don't link CAR teardown in romstageArthur Heymans2019-11-051-1/+0
* soc/intel/sgx: convert SGX and PRMRR devicetree options to KconfigMichael Niewöhner2019-11-042-0/+42
* soc/intel/common: add common function to set LT_LOCK_MEMORYMichael Niewöhner2019-10-311-1/+6
* soc/intel: Rename <intelblocks/chip.h>Kyösti Mälkki2019-09-291-1/+1
* arch/x86: Restrict use of _car_global[start|end]Kyösti Mälkki2019-09-111-3/+3
* soc/*: mp_run_on_all_cpus: Remove configurable timeoutPatrick Rudolph2019-08-151-1/+1
* soc/intel/common: Fix typo mistake in cache_as_ram.SSubrata Banik2019-08-121-1/+1
* soc/intel/cannonlake: Add new PCI IDsFelix Singer2019-07-301-0/+1
* soc/intel/cannonlake: Add device Ids for new CFL SKUs supportLean Sheng Tan2019-07-171-0/+2
* soc/intel/block/cpu: remove unused USE_COREBOOT_NATIVE_MP_INITArthur Heymans2019-07-101-12/+1
* soc/intel: Remove unused pointer argument in mca_configure()Subrata Banik2019-05-211-1/+1
* soc/intel: Geminilake Refresh feature request supportJohn Zhao2019-05-131-0/+1
* src: Add missing include 'console.h'Elyes HAOUAS2019-04-231-0/+1
* cpu/x86: Move checking for MTRR's as a proxy for proper CPU resetArthur Heymans2019-04-212-15/+3
* soc/intel/cpulib: Remove redundent enable/disable functionsSubrata Banik2019-04-131-30/+16
* soc/intel/cpulib: Factor out IA32_PERF_CTL (0x199) MSR codeSubrata Banik2019-04-131-12/+12
* src: Use include <delay.h> when appropriateElyes HAOUAS2019-04-061-1/+0
* src: Use include <reset.h> when appropriateElyes HAOUAS2019-03-291-1/+0
* soc/intel/common: Remove common chip config use_fsp_mp_initSubrata Banik2019-03-241-2/+2
* soc/intel/common: Add Kconfig option to choose desired MP Init for platformSubrata Banik2019-03-241-0/+27
* coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)Julius Werner2019-03-082-10/+10
* arch/io.h: Drop unnecessary includeKyösti Mälkki2019-03-042-2/+0
* soc/intel/common: Include cometlake CPU IDsRonak Kanabar2019-02-241-0/+4
* soc/intel/common: Add whiskeylake celeron v-0 supportLijian Zhao2019-02-191-0/+1
* soc/intel/cpulib: Add debug message to mca_configure()Nico Huber2019-02-051-0/+2
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