Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device | Tim Wawrzynczak | 2020-07-15 | 1 | -0/+1 |
* | soc/intel/common/block: Add new block DTT | Tim Wawrzynczak | 2020-07-07 | 3 | -0/+31 |
index : coreboot.git | ||
Coreboot firmware sources | coreboot |
summaryrefslogtreecommitdiffstats |
Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | PCI IDs: Add PCI ID for JSL DPTF/DTT PCI device | Tim Wawrzynczak | 2020-07-15 | 1 | -0/+1 |
* | soc/intel/common/block: Add new block DTT | Tim Wawrzynczak | 2020-07-07 | 3 | -0/+31 |