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intel
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common
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block
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pcie
Commit message (
Expand
)
Author
Age
Files
Lines
*
soc/intel: Rename 200-series PCH device IDs
Angel Pons
2021-04-28
1
-24
/
+24
*
soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC
Rizwan Qureshi
2021-04-21
1
-1
/
+1
*
acpi/acpigen.h: Add more intuitive AML package closing functions
Jakub Czapiga
2021-03-22
1
-1
/
+0
*
pciexp_device: Rewrite LTR configuration
Nico Huber
2021-03-15
1
-6
/
+4
*
device: Give `pci_ops.set_L1_ss_latency` a proper name
Nico Huber
2021-03-12
1
-2
/
+2
*
soc/intel/commmon: Include Alder Lake device IDs
Varshit Pandya
2021-01-22
1
-0
/
+10
*
soc/intel/common/pcie: Allow pcie_rp_group table to be non-contiguous
Furquan Shaikh
2021-01-18
2
-6
/
+8
*
soc/intel/common/pcie: Add helper function for getting mask of enabled ports
Furquan Shaikh
2021-01-12
2
-0
/
+43
*
soc/intel/common: Add PCIe Runtime D3 driver for ACPI
Duncan Laurie
2020-11-20
6
-0
/
+363
*
soc/intel/common: Include Alder Lake device IDs
Subrata Banik
2020-08-05
1
-0
/
+40
*
src: Never set ISA Enable on PCI bridges
Angel Pons
2020-07-28
1
-3
/
+2
*
soc/intel/common/block/pcie: Select ASPM on mainboard basis
Christian Walter
2020-07-12
1
-2
/
+10
*
treewide: Remove "this file is part of" lines
Patrick Georgi
2020-05-11
2
-2
/
+0
*
soc/intel/common: Use SPDX for GPL-2.0-only files
Angel Pons
2020-04-06
2
-26
/
+4
*
soc: Remove copyright notices
Patrick Georgi
2020-03-18
2
-2
/
+0
*
soc/intel/common: Update Jasper Lake Device IDs
Meera Ravindranath
2020-02-25
1
-8
/
+8
*
soc/intel/common: Add Elkhartlake Device IDs
Tan, Lean Sheng
2020-01-22
1
-0
/
+7
*
soc/intel/common: Add PCI device IDs for CMP-H
Gaggery Tsai
2019-12-13
1
-0
/
+24
*
soc/intel/common: Add Jasperlake Device IDs
rkanabar
2019-12-10
1
-0
/
+8
*
soc/intel: Implement PCIe RP devicetree update based on LCAP
Nico Huber
2019-11-16
2
-0
/
+178
*
soc/intel/common: Include Tigerlake device IDs
Ravi Sarawadi
2019-11-05
1
-0
/
+16
*
intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL
Kyösti Mälkki
2019-10-01
1
-1
/
+2
*
soc/intel/skylake: Add Lewisburg family PCH support
Maxim Polyakov
2019-09-06
1
-0
/
+40
*
device/pciexp_device: Convert LTR non-snoop/snoop value into common macro
Subrata Banik
2019-03-27
1
-6
/
+2
*
{northbridge, soc, southbridge}/intel: Make use of generic set_subsystem()
Subrata Banik
2019-03-21
1
-10
/
+1
*
Fix 'unsigned int' to bare use of 'unsigned'
Subrata Banik
2019-03-19
1
-1
/
+1
*
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
Julius Werner
2019-03-08
1
-1
/
+1
*
soc/intel/common: Include cometlake PCH IDs
Ronak Kanabar
2019-02-26
1
-0
/
+16
*
soc/intel/{common, skylake}: Make ASPM enabling as common PCH feature
Subrata Banik
2018-11-19
1
-0
/
+4
*
soc/intel/common: Include Icelake device IDs
Aamir Bohra
2018-11-07
1
-0
/
+16
*
soc/intel/cannonlake: Add new cannon lake PCH-H support
praveen hodagatta pranesh
2018-10-17
1
-1
/
+25
*
soc/intel/common/block: Don't use device_t in ramstage
Elyes HAOUAS
2018-09-18
1
-1
/
+1
*
pci: Move inline PCI functions to pci_ops.h
Patrick Rudolph
2018-04-20
1
-0
/
+1
*
soc/intel/common/block: Add option to have subsystem_id in common pci driver
Subrata Banik
2017-12-13
1
-0
/
+10
*
soc/intel/common: Add Cannonlake pci ids for common
Lijian Zhao
2017-08-04
1
-0
/
+16
*
soc/intel/common: Add Intel PCIe common code
Aamir Bohra
2017-05-22
3
-0
/
+161