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coreboot.git
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4.10_branch
4.11_branch
4.12_branch
4.14_branch
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4.18_branch
4.19_branch
4.2
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4.22_branch
4.3
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path:
root
/
src
/
soc
/
intel
/
tigerlake
/
Makefile.inc
Commit message (
Expand
)
Author
Age
Files
Lines
*
soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot
Brandon Breitenstein
2021-03-05
1
-1
/
+1
*
soc/intel: Factor out common smmrelocate.c
Angel Pons
2021-03-03
1
-1
/
+0
*
soc/intel: Drop `bootblock_cpu_init()` function
Angel Pons
2021-03-01
1
-1
/
+0
*
soc/intel/tigerlake: Add CrashLog implementation for intel TGL
Francois Toguo
2021-02-22
1
-0
/
+1
*
soc/intel/tigerlake: Add code for early tcss
Brandon Breitenstein
2020-11-13
1
-0
/
+1
*
soc/intel/tigerlake: Log PM event from an internal device
Karthikeyan Ramasubramanian
2020-11-10
1
-0
/
+2
*
soc/intel/{tgl,jsl}: Enable logging of wake sources for S0ix
Furquan Shaikh
2020-11-03
1
-0
/
+1
*
soc/intel/gma: Implement fsp_soc_get_igd_bar() in common code
Nico Huber
2020-05-27
1
-1
/
+0
*
soc/intel/tigerlake: Provide SoundWire controller properties
Duncan Laurie
2020-05-22
1
-0
/
+1
*
soc/intel/tigerlake: Move pmc_soc_set_afterg3_en to pmutil
Tim Wawrzynczak
2020-05-20
1
-1
/
+0
*
soc/intel/tigerlake: Remove eMMC/SD support
Duncan Laurie
2020-04-17
1
-1
/
+0
*
soc/intel/{icl,tgl}: Make use of print_me_fw_version() from CSE lib
Krishna Prasad Bhat
2020-04-14
1
-0
/
+1
*
soc/intel/tigerlake: Remove Jasper Lake SoC references
Aamir Bohra
2020-04-01
1
-13
/
+7
*
soc/intel/{tgl,jsl}: Use soc/intel/jasperlake for Jasper Lake SoC
Aamir Bohra
2020-04-01
1
-1
/
+1
*
soc/intel: Enable GPIO functions in verstage
Bora Guvendik
2020-03-20
1
-0
/
+1
*
soc/intel/tigerlake: Add Jasper lake GPIO support
Ronak Kanabar
2020-03-03
1
-4
/
+8
*
src/soc/tigerlake: Add memory configuration support for Jasper Lake
Meera Ravindranath
2020-03-03
1
-0
/
+1
*
soc/intel/tigerlake: add memory configuration support
Nick Vaccaro
2020-02-09
1
-0
/
+1
*
soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig
Maulik V Vaghela
2020-01-13
1
-1
/
+2
*
soc/intel/tigerlake: Change compilation based on TIGERLAKE_BASE
Maulik V Vaghela
2019-12-02
1
-1
/
+1
*
soc/intel/tigerlake: Do initial SoC commit till ramstage
Subrata Banik
2019-11-09
1
-0
/
+58