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path: root/src/soc/intel/tigerlake/romstage
Commit message (Expand)AuthorAgeFilesLines
* soc/intel: Drop `romstage_pch_init()` functionAngel Pons2021-03-013-13/+3
* soc/intel/tigerlake: Add CrashLog implementation for intel TGLFrancois Toguo2021-02-221-0/+6
* soc/intel/tigerlake: Disable Internal Gfx based on SOC_INTEL_DISABLE_IGDBora Guvendik2021-01-251-5/+6
* soc/intel/tigerlake: Enable CSE Lite driver for TGL platform in romstageSridhar Siricilla2020-12-141-1/+12
* soc/intel: remove duplicate weak versions of mainboard_get_dram_part_num()Nick Vaccaro2020-10-051-6/+0
* mb, soc: change mainboard_get_dram_part_num() prototypeNick Vaccaro2020-10-051-5/+8
* soc/intel/tigerlake: Set TME upd param based on configPratik Prajapati2020-09-301-0/+3
* soc/intel: rename get_prmrr_sizeMichael Niewöhner2020-09-211-1/+1
* soc/intel/tigerlake: Skip GPIO configuration from FSPSrinidhi N Kaushik2020-09-081-0/+3
* soc/intel/tigerlake: Rename pch_init() codeAlexey Buyanov2020-08-262-2/+2
* soc/intel/tigerlake: Fix IPU and Vtd configRavi Sarawadi2020-08-241-4/+15
* soc/intel/tigerlake: Simplify is-device-enabled checksFelix Singer2020-07-281-42/+18
* soc/intel/tigerlake: Disable CPU PCIe in FSPShaunak Saha2020-07-261-0/+4
* soc/intel/tigerlake: Disable VT-d and no DMAR table for pre-QS platformJohn Zhao2020-07-261-13/+27
* soc/intel/tigerlake: Move tco_configure to bootblockTim Wawrzynczak2020-07-121-4/+0
* mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik2020-07-091-1/+2
* soc/intel/tigerlake: Add CpuReplacementCheck to chip optionsJamie Ryu2020-06-301-0/+3
* soc/intel/tigerlake: Add CmdMirror option in chip.hDavid Wu2020-06-221-0/+3
* soc/intel/tigerlake: Configure TcssDma0En and TcssDma1EnJohn Zhao2020-05-301-2/+11
* soc/intel/tigerlake: Add FSP UPD TcssDma0En and TcssDma1EnJohn Zhao2020-05-181-1/+5
* soc/intel/tigerlake: Add PchHdaIDispCodecDisconnect overrideEric Lai2020-05-181-0/+1
* src: Remove leading blank lines from SPDX headerElyes HAOUAS2020-05-181-3/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-115-5/+0
* src/: Replace GPL boilerplate with SPDX headersPatrick Georgi2020-05-091-9/+1
* src/soc/tigerlake: Update SerialIoDebugMode UPD in FSP-MSrinidhi N Kaushik2020-05-041-0/+1
* soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understa...Subrata Banik2020-05-011-1/+1
* soc/intel/tigerlake: Update iDisp Link UPD settingsSrinidhi N Kaushik2020-04-201-3/+0
* soc/intel/tigerlake: Merge the recent change from other platformsWonkyu Kim2020-04-201-16/+22
* soc/intel/tigerlake: Allow mainboard to override DRAM part numberMarco Chen2020-04-071-2/+23
* soc/intel/tigerlake: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-064-52/+8
* soc/intel/tigerlake: Remove Jasper Lake SoC referencesAamir Bohra2020-04-013-147/+1
* soc/intel/tigerlake: Configure HyperthreadingWonkyu Kim2020-03-251-2/+3
* soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBTBrandon Breitenstein2020-03-181-0/+23
* soc: Remove copyright noticesPatrick Georgi2020-03-186-6/+0
* soc/intel/tigerlake: Support ISHli feng2020-03-161-0/+7
* soc/intel/tigerlake: Update Cpu Ratio settingsSrinidhi N Kaushik2020-03-151-0/+12
* soc/intel/tigerlake: Configure Vmx support using KconfigJohn Zhao2020-03-151-0/+3
* soc/intel/tigerlake: Enable VT-d and generate DMAR ACPI tableJohn Zhao2020-03-121-0/+14
* soc/intel/tigerlake: Enable HDA through dev_enabledSrinidhi N Kaushik2020-03-121-1/+8
* soc/intel/tigerlake: Save DIMM info by available nodesJamie Ryu2020-03-111-33/+40
* soc/intel/tigerlake: Correct FSP log interfaceRonak Kanabar2020-03-111-1/+11
* soc/intel/tigerlake: Avoid NULL pointer dereferenceJohn Zhao2020-03-071-1/+5
* soc/tigerlake: Correct FSP log interfaceWonkyu Kim2020-03-021-1/+2
* soc/intel/{icl,jsl,tgl}: Enable PlatformDebugConsent by KconfigSubrata Banik2020-03-012-2/+2
* soc/intel/tigerlake: Add display related UPD configs for Jasper LakeAamir Bohra2020-02-271-0/+7
* soc/intel/tigerlake: Update FSP params for Jasper LakeMaulik V Vaghela2020-02-272-11/+105
* soc/intel/tigerlake: Enable Audio on TGLSrinidhi N Kaushik2020-02-171-0/+13
* soc/intel/tigerlake: Configure TCSS xHCI and xDCIWonkyu Kim2020-02-011-1/+5
* soc/intel/tigerlake: Disable image clocksWonkyu Kim2020-01-291-0/+3
* soc/intel/tigerlake: Enable DP ports according to board designWonkyu Kim2020-01-281-0/+18
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