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* soc/mediatek: Move common definitions to dramc_soc_common.hRex-BC Chen2022-08-031-16/+2
| | | | | | | | | | | | | | Some definitions are the same in dramc_soc.h for MT8192, MT8195 and MT8186, so we move them to dramc_soc_common.h TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I3095333e62abf98de1f2d27033baeeba7a4cad79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66276 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay settingRex-BC Chen2022-07-291-1/+2
| | | | | | | | | | | | | | | MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move common definitions from rtc.h to rtc_reg_common.hRex-BC Chen2022-07-291-126/+1
| | | | | | | | | | | | | | | Move the common definitions to rtc_reg_common.h, so we can reuse those definitions on MT8188. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move struct mtk_auxadc_regs to auxadc_common.hRex-BC Chen2022-07-291-11/+0
| | | | | | | | | | | | | | The AUXADC register definitions are the same for all MediaTek SoCs, so we move struct mtk_auxadc_regs to auxadc_common.h. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move wdt_set_req() to common folderBo-Chen Chen2022-07-061-0/+14
| | | | | | | | | | | | | | | | | | | There are more and more variables which are SoC-specific, so add soc/wdt.h for each SoC and rename common/wdt.h to common/wdt_common.h. wdt_set_req() is almost the same for mt8192, mt8195 and mt8186, so move it to a common file wdt_req.c. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7a334b3e7cd4f24a848dd31aca546dc7236d5fb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65636 Reviewed-by: Yidi Lin <yidilin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Enlarge CBFS_MCACHE to 16KYu-Ping Wu2022-05-051-16/+22
| | | | | | | | | | | | | | | | | | | | | | | The per-file hash for CBFS_VERIFICATION, stored as a CBFS file attribute, would increase the total RO metadata size by 75% (3796->6656 for corsola). Therefore, in order to make RO metadata cache fit into CBFS_MCACHE, enlarge it from 8K to 16K. Adjust the memlayout by decreasing the DRAM_INIT_CODE from 196K to 184K (only 160K needed for now), and moving VBOOT2_WORK region to L2C. Also shuffle the regions in SRAM with better comments. BUG=b:229670703 TEST=emerge-corsola coreboot TEST=Enabled CBFS_VERIFICATION and booted kingler into kernel BRANCH=none Change-Id: I8e07eb9fae1644a0fbfbdc599ca0a0e11bbe54b5 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/mediatek/mt8186: Prevent early USB wakeupRex-BC Chen2022-05-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MT8186 platform fails to suspend due to premature wakeup by USB. In MT8186, we use low level latch to keep USB wakeup signal. However, hardware could latch a wrong signal if it debounces more than one time. As a result, it would enable wakeup function too early. To prevent this issue, we do the following modification: - Delay about 100 us to enable wakeup function in kernel drivers [1]. - To guarantee 100 us is enough, we need to disable the USB debounce by default in coreboot. According to section register 0x404 and 0x420 in "(CODA) MT8169_PERICFG_REG.xls" which is only for MediaTek internal use: The current default value of debounce register for MT8186 USB IP0 and IP1 is incorrect. The reason we add in coreboot is that the default value should be correct when SoC is booting up. This modification is only for MT8186. The subsequent SoCs will adjust the wakeup function to correct register value by default. [1]: 0d8cfeeef3f5 (usb: xhci-mtk: fix random remote wakeup) TEST=after stress test, not found premature wakeup by USB BUG=b:228773975 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I296c4491c5959670a39fa8bd6ef987557bbc459f Reviewed-on: https://review.coreboot.org/c/coreboot/+/63858 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Disable unused powerRex-BC Chen2022-04-071-0/+1
| | | | | | | | | | | | | | To save the power consumption, we disable the unused power of optional components in coreboot. BUG=none TEST=the value of power consumption is as expected. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic0c7c2d1b6a4c26980a3029b60051ab1406406ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/63247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Fix pmif setting for low power modeZhiyong Tao2022-03-292-0/+17
| | | | | | | | | | | | | | | | | | | | | The current pmif register setting for low power mode is incorrect, which is causing suspend failure. The issue of suspend failure is that SRCLKENA0 will not be pulled down. EC will not be informed AP is suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode() to correct the setting. This implementation is based on chapter 3.7 in MT8186 Functional Specification. BUG=b:215639203 TEST=test of suspend and resume pass. Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com> Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/mediatek/mt8186: Add GPIO driving functionsGuodong Liu2022-03-091-0/+13
| | | | | | | | | | | | | | | | | | | | | Add GPIO driving functions to adjust pin driving. The value of drive strength is different for each SoC, so we define GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA in MT8186. This implementation is according to chapter 5.1 in MT8186 Functional Specification. BUG=b:218775654, b:216462313, b:212375511 TEST=build pass Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62471 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Set RTC capid to 0xC0 to pass XTAL 26 MHz testRex-BC Chen2022-03-021-0/+1
| | | | | | | | | | | | | | | | | | | The XTAL 26MHz test failed on krabby, so we adjust RTC capid from default value 0x88 to 0xC0 for MT8186. We also add a new log message to show the capid value which is read from MT6366. This implementation is according to chapter 5.13 in MT8186 Functional Specification. BUG=b:218439447 TEST=set capid to 0xc0. TEST=XTAL 26MHz test passed. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I16ab46a5697d304e8001de231ffc9b7b7a2f9282 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* src/mediatek: Refactor dramc_param to share more structuresXi Chen2022-02-231-71/+0
| | | | | | | | | | | | | The ddr_base_info struct, which stores basic DDR information, should be platform independent. Currently the struct is defined in each SoC's dramc_parah.h. To prevent code duplication, move it as well as other related structs and enums to a common header. Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Support DRAM fast calibration using blobXi Chen2022-02-092-13/+34
| | | | | | | | | | | | | | | | | | | | | For most MediaTek SoCs (MT8183, MT8192, MT8195) we rely on an external program (e.g., the "DRAM blob") to do the full DRAM calibration first, then store and and apply the generated parameters to the reference "fast DRAM calibration" in the vendor/mediatek folder for normal system boot. Starting with MT8186 the implementation of fast calibration may need to be changed, and a "DRAM blob" only path is introduced for devices that have to do both full and fast calibration using the external blob. TEST=fast calibration pass on kingler/krabby BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: If25a7dd6aa6261ecff79a1b4df8b1f2e53d896dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/61133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Use BIT() macro for arbiter enable bitRex-BC Chen2022-01-261-20/+20
| | | | | | | | | | | | | | Replace (1 << x) with BIT(x) in pmic_wrap.h. BUG=none TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I463589f02065a228a8af74447b4586e5b54e0b3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61351 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Update PWRAP arbiter enable bitRex-BC Chen2022-01-261-13/+22
| | | | | | | | | | | | | | | There is no wakeup source when we test function of suspend and resume. The root cause is that the monitor enable bit of PWRAP is not configured correctly. BUG=b:213255218, b:214978483 TEST=receive wakeup source from MT6366 successfully Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I324d18fa5d3cd745c35fcf0f207e1b444b5e898b Reviewed-on: https://review.coreboot.org/c/coreboot/+/61330 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Extract dramc_param_header to a common headerXi Chen2022-01-241-12/+1
| | | | | | | | | | | | | | | | To be shared with different SOCs, move the dramc_param_header struct as well DRAMC_PARAM_FLAG and DRAMC_PARAM_CONFIG enums to a common header file dramc_param_common.h. TEST=fast calibration pass BUG=b:204226005 Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com> Change-Id: I087971799803e47e34c30063b2b0bd0cfc5795ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/61132 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: fix incorrect devapc settingsRunyang Chen2022-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | | We need to protect debugsys for firmware image without serial console. Original settings for protecting debugsys is wrong which will cause some hardware modules to fail to set their registers correctly. We move the setting from MM_AO_APC to INFRA_AO_APC because the setting of debugsys is defined in INFRA_AO_APC and set the debugsys index to correct value of 94. BUG=b:213125558 TEST=all modules work normally using image without serial console. Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: Ibce626386ac1f8de42f8717c4ad9ba403640b3ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60833 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: initialize DFDRex-BC Chen2022-01-071-0/+12
| | | | | | | | | | | | | | | | DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values can be shown for debugging using MTK internal parsing tools. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I7b711755022b5d9767019611151fea65e71edc66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60828 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Increase CBFS_MCACHE size to 8KiBRex-BC Chen2022-01-061-7/+7
| | | | | | | | | | | | | | | | | | The current CBFS mcache size (roughly 7KiB) is insufficient for mt8186, so we need to increase it by 1KiB (and decrease the stack by 1KiB). Error logs: CBFS ERROR: mcache overflow, should increase CBFS_MCACHE size! CBFS: mcache @0x0010e004 built for 63 files, used 0xde4 of 0xdfc bytes BUG=b:202871018 TEST=no cbfs error logs. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I1e627ede3774665575006f752f89101e3c5bde9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/60529 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Add support for regulator VRF12/VCN33Rex-BC Chen2022-01-011-0/+6
| | | | | | | | | | | | | | To provide power to PS8640, the eDP bridge IC on krabby, add control of VRF12 and VCN33 to set voltage from MT6366. TEST=measure 1.2V from VRF12 and 3.3V from VCN33. BUG=b:210806060 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I55a9ca16e1e335e9355d0a1b30c278a9969db197 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add DSI driverRex-BC Chen2021-12-291-0/+60
| | | | | | | | | | | | | Enable DSI for display. BUG=b:209930699 TEST=Firmware display looked good Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Idb6bd3a1d32ac96a9d1a2553b8a70db4e59eec16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add DDP driverRex-BC Chen2021-12-292-0/+271
| | | | | | | | | | | | | | Add DDP (display controller) driver that supports main path to eDP panel. The output goes to display interface DSI. BUG=b:209930699 TEST=saw firmware display Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ic4fb40832b5dc7a815b37266259b2e3281ee79f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add header files to support DRAM calibrationRyan Chuang2021-12-293-15/+203
| | | | | | | | | | | | | | | Remove emi.h because emi.h is defined in common/include/soc. Add dramc_param.h and dramc_soc.h to prepare for implementation of DRAM full calibration. TEST=build pass. BUG=b:202871018 Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> Change-Id: If8662ed43088ea5aa1fe6cb5b2c4bda2338c4387 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60385 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Add devapc basic driversRunyang Chen2021-12-281-0/+93
| | | | | | | | | | | | | | | | | | | | | | | | Add basic devapc (device access permission control) drivers. DAPC driver is used to set up bus fabric security and data protection among hardwares. DAPC driver groups the master hardwares into different domains and gives secure and non-secure property. The slave hardware can configure different access permissions for different domains via DAPC driver. 1. Initialize devapc. 2. Set master domain and secure side band. 3. Set default permission. BUG=b:202871018 TEST=build pass Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com> Change-Id: I5dad4f342eef3136c24c38259ad176dc86b7c0d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Adjust usage of SRAM L2CRex-BC Chen2021-12-281-5/+11
| | | | | | | | | | | | | | | | | | | We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before DRAM calibration. When we check cbmem, we found the content of this memory is unreadable. The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM has configured only half of L2/L3 cache as SRAM. Therefore, decrease the size of each SRAM region to fit into the first half of the cache. BUG=b:207725851 TEST=Bootblock log looked good in `cbmem -c` Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add tracker dumpRex-BC Chen2021-12-142-0/+9
| | | | | | | | | | | | | | | | | | Tracker is a debugging tool, and MT8186 only supports AP tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debugging. This function will be triggered only when it encounters the bug hanging issue. BUG=b:202871018 TEST=range of registers are dumped as expected. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ie023de2a6f7421a16b2516baa0bf0bf6fff589e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Correct SPI_HZ for PLLRex-BC Chen2021-12-081-2/+2
| | | | | | | | | | | | | The SPI speed is 218.4MHz, so correct the value of SPI_HZ. BUG=b:202871018 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I6e8ba10a851e1507405cdd41939a176462734487 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59939 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add support for regulator VPROC12/VSRAM_PROC12Rex-BC Chen2021-11-261-0/+8
| | | | | | | | | | | | | To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add RTC and clkbuf driversYuchen Huang2021-11-171-0/+240
| | | | | | | | | | | | | Add support for RTC and clkbuf. TEST=boot to kernel and check log ok BUG=b:202871018 Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add mtcmos init supportChun-Jie Chen2021-11-171-1/+17
| | | | | | | | | | | | | Add mtcmos to support display and audio. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Ib9d41d47f235376f524c3ff78f1fcc069cbc60cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add SPM loaderRex-BC Chen2021-11-171-0/+325
| | | | | | | | | | | | | | | | | This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. TEST=program counter of SPM is correct value(0x250) after booting up BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59341 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: initialize SSPMRex-BC Chen2021-11-171-0/+2
| | | | | | | | | | | | | | | SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Enable DCMEdward-JW Yang2021-11-171-0/+15
| | | | | | | | | | | | | | DCM (dynamic clock management) can dynamically slow down or gate clocks during CPU or bus idle. Enable DCM settings on the MT8186 platform. TEST=build pass and check register ok BUG=b:202871018 Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/59338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add I2C driver supportHousong Zhang2021-11-171-0/+70
| | | | | | | | | | | | | Add I2C controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Housong Zhang <housong.zhang@mediatek.corp-partner.google.com> Change-Id: Ia3800e3a30b0796a64213d3b1ab688580c6ddbca Reviewed-on: https://review.coreboot.org/c/coreboot/+/59296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add support for regulator VMCH and VMCRex-BC Chen2021-11-151-0/+8
| | | | | | | | | | | | | Add support for VMCH and VMC of MT6366. TEST=measure voltage 3.3V for VMCH and VMC BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Id8d98b6d827abd4713ee5c216941a9621422c7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/59254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add AUXADC driver supportGuodong Liu2021-11-152-0/+45
| | | | | | | | | | | | | Add AUXADC controller driver code. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: I9fb7fd4903d67a2804c31ff404bc0486983c742f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add GIC pre-initialization functionRex-BC Chen2021-11-151-0/+13
| | | | | | | | | | | | | | | | | GIC (generic interrupt controller) defines architectural requirements for handling all interrupt sources and common interrupt controller programming interface. GIC needs to be pre-initialized on MT8186, so we add this initialize function. TEST=build pass BUG=b:202871018 Change-Id: I6bf439d0d9e1ca7130a69b9006b957afca8b133c Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59252 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: add USB supportRex-BC Chen2021-11-152-2/+33
| | | | | | | | | | | | | | | 1. Enable and setup USB drivers. 2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset the hub via GPIO149. TEST=boot kernel from USB ok BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add SPM register definitionsRex-BC Chen2021-11-151-0/+533
| | | | | | | | | | | | | Add SPM register definitions so that other drivers can use them. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iec2b493e464be9d617226cc8a9875ee3ddb759de Reviewed-on: https://review.coreboot.org/c/coreboot/+/59248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Enable mmu operation for L2C SRAM and DMARex-BC Chen2021-11-151-1/+1
| | | | | | | | | | | | | | | | | | | 1. Turn off L2C SRAM and reconfigure as L2 cache Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready. After DRAM is ready, we should invoke disable_l2c_sram to reconfigure the L2C SRAM as L2 cache. 2. Configure DMA buffer in DRAM Set DRAM DMA to be non-cacheable to load blob correctly. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add support for PMIC MT6366James Lo2021-11-153-0/+497
| | | | | | | | | | | | | Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add SPI driver supportRuwen Liu2021-11-081-1/+16
| | | | | | | | | | | | | Add SPI controller drivers. TEST=build pass BUG=b:202871018 Signed-off-by: Ruwen Liu <ot_ruwen.liu@mediatek.com> Change-Id: I59a885c4fa31b6e2921698eaa3b97dbdc3144946 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add PLL and clock init supportChun-Jie Chen2021-11-053-0/+1981
| | | | | | | | | | | | | | Add PLL and clock init code, frequency meter and APIs for raising little CPU/CCI frequency. TEST=build pass BUG=b:202871018 Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Change-Id: Id46d0708e7ba0c1a4043a5dce33ef69421cb59c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: add NOR-Flash GPIO setting in soc folderRex-BC Chen2021-11-051-0/+8
| | | | | | | | | | | | | | | The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so we have to provide an init function in SoC for the mainboard to select right configuration. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8186: Add NOR-Flash supportRex-BC Chen2021-11-041-0/+10
| | | | | | | | | | | | | | Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If51d765e1fd4895f97898710ec6fa1374e1048fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58837 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Add GPIO driversGuodong Liu2021-11-032-0/+650
| | | | | | | | | | | | | | Add GPIO drivers to let other module control GPIOs. TEST=build pass BUG=b:202871018 Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> Change-Id: Ice342ab94397db8bc0fbbeb8fb5ee7e19de871ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/58836 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8186: Add a stub implementation of the MT8186 SoCRex-BC Chen2021-11-036-0/+196
Add new folder and basic drivers for Mediatek SoC 'MT8186'. Difference of modules including in this patch between MT8186 and existing SoCs: Timer: Similar to MT8195, MT8186 uses v2 timer. EMI/PLL/SPI: Different from existing SoCs. TEST=boot from SPI-NOR and show uart log on MT8186 EVB BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I579f79c15f4bf5e1daf6b35c70cfd00a985a0b81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58640 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 18:01:11 +0000