summaryrefslogtreecommitdiffstats
path: root/src/soc/sifive/fu540/clock.c
Commit message (Expand)AuthorAgeFilesLines
* Replace some ENV_ROMSTAGE with ENV_RAMINITKyösti Mälkki2022-06-071-2/+2
* soc/sifive: Drop unneeded empty linesElyes HAOUAS2020-08-241-2/+0
* treewide: Remove "this file is part of" linesPatrick Georgi2020-05-111-1/+0
* soc/sifive: Use SPDX for GPL-2.0-only filesAngel Pons2020-04-051-13/+2
* soc: Remove copyright noticesPatrick Georgi2020-03-181-1/+0
* soc/{samsung,sifive}: Fix typosElyes HAOUAS2020-02-241-1/+1
* soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>Elyes HAOUAS2019-12-191-1/+0
* Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner2019-12-041-7/+7
* src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet ControllerXiang Wang2019-03-181-0/+35
* device/mmio.h: Add include file for MMIO opsKyösti Mälkki2019-03-041-1/+1
* soc/sifive/fu540: Add helper function to get tlclk frequencyJonathan Neuschäfer2018-12-051-0/+11
* soc/sifive/fu540: Load PLL settings from a structJonathan Neuschäfer2018-12-041-84/+72
* soc/sifive/fu540: Simplify UART refclk calculationJonathan Neuschäfer2018-12-031-0/+1
* soc/sifive/fu540: Document #if ENV_ROMSTAGE lineJonathan Neuschäfer2018-09-261-3/+2
* soc/sifive/fu540: Switch clock to 1GHz in romstagePhilipp Hug2018-09-141-16/+44
* soc/sifive/fu540: Get SDRAM controller out of resetPhilipp Hug2018-09-131-0/+34
* soc/sifive/fu540: Update clock settings according SiFive bootloaderPhilipp Hug2018-09-131-8/+30
* soc/sifive/fu540: Initialize PLL and clockPhilipp Hug2018-09-121-0/+180
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-18 20:34:06 +0000