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* vc/intel/fsp/mtl: Update header files from 3424_88 to 3471.85Kulkarni, Srinivas2024-01-071-2/+9
| | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3471_85, previous version being 3424_88. FSPM: 1. Add 'DisplayGpioPinMux' UPDs 2. Address offset changes BUG=b:318772151 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I11c39fc2e3099d93a488e71d571ac1af02345fbd Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79829 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/intel/fsp/mtl: Add UPDs for Acoustic Noise MitigationSubrata Banik2023-12-201-50/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | Acoustic noise in PCBs is a common problem and be caused by a variety of factors, including: Mechanical vibrations, Electromagnetic interference (EMI) and/or Thermal expansion. This patch adds the UPDs to FSPM header file for mitigating the acoustic noise. FSPM: 1. AcousticNoiseMitigation 2. FastPkgCRampDisable 3. SlowSlewRate BUG=b:312405633 TEST=Able to build and boot google/rex. Change-Id: Iea0bfa2f92bb82e722ffc1a0b2f1e374b32e4ebc Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79301 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
* vc/intel/fsp/mtl: Update header files from 3323_86 to 3424_88Kilari Raasi2023-12-112-70/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3424_88, previous version being 3323_86. FSPM: 1. Add `MarginLimitCheck` UPD 2. Add pre-memory graphics UPDs i.e `LidStatus`, `VgaInitControl`,`VbtPtr`,`VbtSize`,`VgaMessage` 3. Address offset changes FSPS: 1. Add `Usb4CmMode` UPD 2. Address offset changes BUG=b:310108425 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I3f71cd739a607318fda06fa50d4a379d64857458 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78997 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/intel/fsp/mtl: Add Psi[1-3]Threshold UPDs to FSP-M header fileJeremy Compostella2023-10-281-2/+23
| | | | | | | | | | | | Export Power State Current 1, 2 and 3 Threshold configuration entries. BUG=b:308002192 Change-Id: Iff4467720541efbdedace12431cd1f6f66fca8e6 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/intel/fsp/mtl: Update header files from 3323.84 to MTL.3323.86Subrata Banik2023-09-231-46/+74
| | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3323.86, previous version being 3323.84. FSPM: 1. Added new UPDs - AcLoadline - DcLoadline - LowerBasicMemTestSize 2. Address offset changes BUG=b:301441204 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I6c2f7f588874b37c52e3926c02e381ceff14f5af Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78065 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
* vc/intel/fsp/mtl: Update header files from 3292.83 to 3323.84Subrata Banik2023-09-012-7/+10
| | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform from 3292.83 to 3323.84. The patch changess only a few spacing alignment for FSP-M header and added few PPR (Post Package Repair) related variable for MemInfoHob header. BUG=b:297965979 TEST=Able to build and boot google/rex. Change-Id: I65c6e05256a2ae9516449dbce62affd040cb0e56 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77561 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/mtl: Add PsysPmax FspmUpdKilari Raasi2023-08-211-46/+56
| | | | | | | | | | | | | | | | | | | | This patch adds the PsysPmax Upd to FSPM header file. FSPM: 1. Add 'PsysPmax' UPD 2. Address offset changes BUG=b:295126631 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I892b8c2d75e58a42d3f85006237827da01426ea7 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77244 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp/mtl: Update header files from 3223.80 to 3292.83Dinesh Gehlot2023-08-182-6/+4
| | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3292.83, previous version being 3223.80. The patch doesn't include any function changes, only a few comments and headers have been changed. BUG=b:295126631 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I27f88732bfafd4732ea39bf9c54e18341dd26cf9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* vc/intel/fsp/mtl: Update the MemInfoHob header to FSP version 3251.81Subrata Banik2023-07-141-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the MemInfoHob header file as per Meteor Lake version 3251.81. Changes include: 1. Drop DimmDFE structure variable 2. Drop unused macro MAX_COPY_DIMM_DFE_TAPS BUG=b:290898626 TEST=Able to build and boot google/rex. w/o this patch: cbmem -c -1 | grep DIMM [ERROR] No DIMMs found w/ this patch: cbmem -c -1 | grep DIMM [DEBUG]  8 DIMMs found Change-Id: I8eed410831399bb4835244f48c14d5ed9e701e68 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76433 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/mtl: Update header files from 3194_81 to 3223.80Kilari Raasi2023-07-062-29/+66
| | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3223_80, previous version being 3194_81. FSPM: 1. Add 'ROWHAMMER','RhSelect','McRefreshRate','Lfsr0Mask','Lfsr1Mask' UPDs 2. Add 'TmeExcludeBase','TmeExcludeSize','GenerateNewTmeKey' UPDs 3. Address offset changes BUG=b:287890130 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I4b8d0a3a87be7dc0d899298eb8e4e48905090e71 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75916 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp/fsp20/meteorlake: Add VR config entriesSubrata Banik2023-06-141-46/+74
| | | | | | | | | | | | | | | | | | This patch adds UPD entries into the FSP header file to configure VRs (IA, GT and SA). - `IccLimit` : VR Fast Vmode ICC Limit support - `EnableFastVmode` : Enable/Disable VR FastVmode - `CepEnable` : Enable/Disable CEP (Current Excursion Protection BUG=b:286809233 TEST=Able to build google/rex. Change-Id: I477ab7e4c07156759962bd2eab9dff28a0a3f006 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75761 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
* vc/intel/fsp/mtl: Update header files from 3165_81 to 3194_81Kilari Raasi2023-06-042-4/+88
| | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3194_81, previous version being 3165_81. FSPM: 1. Add 'PchPcieRpEnableMask' UPD 2. Address offset changes Add "FspProducerDataHeader.h" file to support MRC version Info BUG=b:284803304 TEST=Able to build and boot google/rex to ChromeOS. Change-Id: I43f276e9b8e46edc76dc7749d2a610cfa836a718 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75519 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/intel/fsp/fsp20/meteorlake: Add `SaGvWpMask`Subrata Banik2023-05-251-74/+77
| | | | | | | | | | | | | | | | | This patch adds `SaGvWpMask` UPD into the FSP header. This information is required to set the SaGv work endpoint. BUG=b:283746904 TEST=Able to build google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If39da58c927cc7b28b46063576f8e246ef9596d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75361 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
* vc/intel/fsp/mtl: Update header files from 3084_85 to 3165_81Kilari Raasi2023-05-112-787/+784
| | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3165_81, previous version being 3084_85. FSPM: 1. Change UPD name from 'GtExtraTurboVoltage' to 'GtAdaptiveVoltage' 2. Change UPD name from 'CoreVoltageAdaptive' to 'CoreAdaptiveVoltage' 3. Change UPD name from 'RingVoltageAdaptive' to 'RingAdaptiveVoltage' 4. Address offset changes FSPS: 1. Remove deprecated UPD 'PcieDpc' 2. Address offset changes BUG=b:280005256 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I67939ecf71166fca4f3d2d6cd4622215bebc5718 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* vc/intel/fsp/mtl: Update header files from 3064_81 to 3084_85Kilari Raasi2023-03-293-251/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3084_85, previous version being 3064_81. FirmwareVersionInfo.h: 1. Define INTEL_FVI_SMBIOS_TYPE macro FSPM: 1. Remove deprecated UPD `BclkSource` 2. Address offset changes FSPS: 1. Add `CnviWifiCore` UPD 2. Address offset changes BUG=b:274051289 TEST=Able to build and boot google/rex to ChromeOS. Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I24dea1a31dbb592f9dea4246a3d490e5d23dca9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp/mtl: Add tCCD_L_WR to MemInfoHob as per FSP v3064Subrata Banik2023-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This patch updates the Memory Hob Info data structure as per FSP v3064 source code change. BUG=b:273894357 TEST=Able to see `smbios type 17` table while booting google/rex. Without this patch: [DEBUG] 0 DIMM found With this patch: [DEBUG] 8 DIMM found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3885fa7143cecc0b56e20278b69951c548ac451b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73755 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* vc/intel/fsp/mtl: Update header files from 2523_80 to 3064_81Kilari Raasi2023-03-083-978/+1012
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 3064_81, previous version being 2523_80.. FSPM: 1. Addition of new UPDs SocTraceHubMode,SocTraceHubMemReg0Size SocTraceHubMemReg1Size. 2. Remove depricated UPD RDODTT. 3. Address offset changes. FSPS: 1. Address offset changes. FspUpd.h: 1.Corrected UPD signatures. BUG=b:TBD Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Change-Id: I73764d471295ad1a969ae562fe8a9fb7a25c5b2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* vc/intel/fsp/mtl: Update header files from 2473_86 to 2523_80Kilari Raasi2023-02-172-788/+809
| | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2523_80, previous version being 2473_86. FSPM: 1. Rename DMI UPDs 2. Address offset changes FSPS: 1. Address offset changes BUG=b:266499304 Change-Id: Ib4b8478bc3558ef863b6b52e685f981a5891e4a9 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72591 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
* vc/intel/fsp/mtl: Update header files from 2431_80 to 2473_86Kulkarni, Srinivas2023-01-242-526/+518
| | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2473_86, previous version being 2431_80. FSPM: 1. Removed deprecated UPD PcieMultipleSegmentEnabled 2. Address offset changes FSPS: 1. Removed deprecated UPD ForcMebxSyncUp 2. Address offset changes BUG=b:261150757 Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.corp-partner.google.com> Change-Id: Ie396ad7ef4da2d1c52d37477bbb0815d2d650841 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
* vc/intel/fsp/mtl: Update header files from 2404_00 to 2431_80Subrata Banik2022-12-142-1803/+927
| | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2431_80, previous version being 2404_00. FSPM: 1. Address offset changes FSPS: 1. Address offset changes Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id192598e2ef57b9d7dacfbfd086a67593a2cd12e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* vc/intel/fsp/mtl: Remove deprecated header FirmwareVersionInfoHob.hSaurabh Mishra2022-12-121-68/+0
| | | | | | | | | | | | | | | | | Changes include: - FirmwareVersionInfoHob.h is removed to use new header file FirmwareVersionInfo.h. BUG=b:260183604 TEST=Verified Google/Rex0 build with all the patch in relation chain and verified the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: I06fd89f201e9e4100524e58033086327ad4ffc7b Reviewed-on: https://review.coreboot.org/c/coreboot/+/69884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* vc/intel/fsp/mtl: Add new header file FirmwareVersionInfo.hSaurabh Mishra2022-12-121-0/+60
| | | | | | | | | | | | | | | | | Changes include: - Add header file FirmwareVersionInfo.h BUG=b:260183604 BRANCH=None TEST=Verified Google/Rex0 build with all the patch in relation chain and verified the version output prints no junk data. Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Change-Id: Ib5c843bb0dccd5db92f74148df3a17037988392c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69882 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp/mtl: Update header files from 2364_00 to 2404_00vjadeja-intel2022-11-172-201/+1083
| | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2404_00, previous version being 2364_00. FSPM: 1. Address offset changes 2. Rename `PlatformDebugConsent` to `PlatformDebugOption` FSPS: 1. Address offset changes Additionally, incorporate the UPD name change for MTL romstage. BUG=b:255481471 TEST=Able to build and boot Google, Rex to ChromeOS. Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp/mtl: Update header files from 2344_00 to 2364_00Subrata Banik2022-10-202-430/+435
| | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2364_00, previous version being 2344_00. FSPM: 1. Address offset changes FSPS: 1. Address offset changes BUG=b:251733481 TEST=emerge-rex intel-mtlfsp Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8e4f62890b812f68dffe215e51c433510fca018f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vc/intel/fsp/mtl: Update header files from 2304_01 to 2344_00Srinidhi N Kaushik2022-09-222-748/+708
| | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2344_00, previous version being 2304_01. FSPM: 1. Address offset changes FSPS: 1. Deprecated CstateLatencyControlTimeUnit UPDs 2. Deprecated HybridStorageMode 3.Address offset changes BUG=b:245167089 TEST=emerge-rex intel-mtlfsp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Iaee5c66811c340d12921ff9247461df36de4739a Reviewed-on: https://review.coreboot.org/c/coreboot/+/67429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp/mtl: Update header files from 2253_00 to 2304_01Srinidhi N Kaushik2022-08-052-950/+977
| | | | | | | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2304_01, previous version being 2253_00. FSPM: 1. Removed CpuCrashLogDevice 2. Address offset changes FSPS: Includes below new UPDs 1. VpuEnable 2. SerialIoI3cMode 3. ThcAssignment 4. PchIshI3cEnable BUG=b:240665069 TEST=emerge-rex intel-mtlfsp Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I9740e5877af745124d573425da623e814d8df5d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66289 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vc/intel/fsp2_0: Update partial headers to MTL.FSP2253.00Kapil Porwal2022-07-133-343/+4490
| | | | | | | | | | | | Update partial headers to MeteorLake FSP v2253.00 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: If2d6c80bd35afd68588fef57e38064c5b1e1a888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp2_0: Add UPDs into the FSP partial header version 2222Subrata Banik2022-07-032-4537/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds below UPDs into the existing FSP partial header v2222.1 FSP-M UPD: DisableMc0Ch0 DisableMc0Ch1 DisableMc0Ch2 DisableMc0Ch3 DisableMc1Ch0 DisableMc1Ch1 DisableMc1Ch2 DisableMc1Ch3 DdrFreqLimit GpioOverride SerialIoUartDebugMode SerialDebugMrcLevel SmbusDynamicPowerGating WdtDisableAndLock SaIpuEnable SkipCpuReplacementCheck TcssDma0En TcssDma1En VtdBaseAddress CpuCrashLogDevice CpuCrashLogEnable LCT TdcEnable TdcTimeWindow Lp5CccConfig RMTBIT RmtPerTask RMTLoopCount MrcFastBoot EnCmdRate SaGvGear TAT PchHdaVcType BdatTestType RdEnergyMc0Ch0Dimm1 RdEnergyMc0Ch0Dimm0 CorePllVoltageOffset RdEnergyMc1Ch1Dimm1 RdEnergyMc1Ch1Dimm0 DciEn PchPort80Route ActEnergyMc0Ch1Dimm1 ActEnergyMc0Ch1Dimm0 HeciCommunication2 PcdSerialDebugBaudRate HeciTimeouts ThrtCkeMinDefeatLpddr PchPcieHsioRxSetCtle BdatEnable DisableCpuReplacedPolling PchSataHsioRxGen1EqBoostMagEnable CoreVoltageOffset PchPcieHsioTxGen1DownscaleAmp PchHdaDspUaaCompliance VddVoltage WRVC1D PreBootDmaMask tWR RingVoltageAdaptive PchSataHsioTxGen3DeEmphEnable PchPcieHsioRxSetCtleEnable RingPllVoltageOffset OcSupport WrEnergyMc0Ch0Dimm1 PdEnergyMc1Ch1Dimm1 PdEnergyMc1Ch1Dimm0 DmiGen3ProgramStaticEq SmramMask tRAS PerCoreHtDisable IdleEnergyMc1Ch0Dimm0 IdleEnergyMc1Ch0Dimm1 Gen3LtcoEnable tWTR RCVET DmiGen3UsPresetEnable tCWL PwdwnIdleCounter WRTC1D CLKTCO PrimaryDisplay DisableMessageCheck tFAW PchSataHsioTxGen2DeEmphEnable SerialIoUartDebugRtsPinMux GtExtraTurboVoltage TXTCO PchSataHsioTxGen3DownscaleAmp CpuRatioOverride PostCodeOutputPort DmiHweq CoreVfPointCount NModeSupport Ddr4DdpSharedZq RdEnergyMc1Ch0Dimm0 RdEnergyMc1Ch0Dimm1 PchSataHsioTxGen2DownscaleAmp DebugInterfaceEnable WrEnergyMc0Ch1Dimm0 WrEnergyMc0Ch1Dimm1 SaPllVoltageOffset DmiGen3EndPointPreset PchSataHsioRxGen2EqBoostMag VDDQT PvdRatioThreshold CoreVfPointOffsetMode DmiGen3DsPortRxPreset BclkRfiFreq SmbusArpEnable PowerDownMode DebugInterfaceLockEnable RingVoltageOffset EnableExtts SerialIoUartDebugCtsPinMux PchPcieHsioTxGen2DownscaleAmpEnable Avx2VoltageScaleFactor GearRatio GtVoltageOverride EccSupport RingMaxOcRatio TrainTrace EnablePwrDn IsTPMPresence OcLock DmaBufferSize SOT CoreVfPointRatio PchPcieHsioTxGen2DownscaleAmp TjMaxOffset CoreMaxOcRatio RingDownBin PchSataHsioRxGen1EqBoostMag BiosAcmSize tRFC PchPcieHsioTxGen1DownscaleAmpEnable PdEnergyMc0Ch1Dimm0 PdEnergyMc0Ch1Dimm1 RDMPRT TxtLcpPdBase CMDVC SerialIoUartDebugBaudRate PchTraceHubMemReg1Size CoreVoltageOverride McPllVoltageOffset PdEnergyMc1Ch0Dimm0 PdEnergyMc1Ch0Dimm1 GttMmAdr PchPcieHsioTxGen1DeEmphEnable ApStartupBase CoreVoltageAdaptive GtVoltageMode PcieImrRpSelection TxtLcpPdSize PchPcieHsioTxGen2DeEmph3p5 ThrtCkeMinTmr RealtimeMemoryTiming UserBudgetEnable PchPcieHsioTxGen3DownscaleAmpEnable GmAdr PchSataHsioTxGen1DeEmphEnable CrashLogGprs tRTP RMC PchSataHsioTxGen3DownscaleAmpEnable RDODTT RDVREFDC PerCoreRatio IdleEnergyMc0Ch1Dimm1 tRCDtRP DidInitStat SerialIoUartDebugRxPinMux SerialIoUartDebugMmioBase BiosSize MmioSizeAdjustment PchTraceHubMode DmiGen3Ltcpre CoreVoltageMode DmiGen3UsPortTxPreset Gen3EqPhase3Bypass BclkSource KtDeviceEnable DciUsb3TypecUfpDbg CoreVfPointOffset Gen3RtcoRtpoEnable TotalFlashSize BclkAdaptiveVoltage TvbRatioClipping EnablePwrDnLpddr WRTC2D RankInterleave PchSataHsioRxGen3EqBoostMag IdleEnergyMc0Ch0Dimm1 IdleEnergyMc0Ch0Dimm0 Ratio JWRL Avx3RatioOffset Avx2RatioOffset RDVC1D DCC PchSataHsioTxGen2DeEmph ExitOnFailure IdleEnergyMc1Ch1Dimm1 IdleEnergyMc1Ch1Dimm0 RingVoltageOverride SpdProfileSelected ScramblerSupport SaGvFreq WRVC2D DmiGen3EqPh3Method CMDSR RdEnergyMc0Ch1Dimm0 RdEnergyMc0Ch1Dimm1 UserThresholdEnable ThrtCkeMinDefeat DmiGen3EqPh2Enable tRRD ChHashEnable BistOnReset ChHashInterleaveBit RemapEnable RDVC2D DIMMRONT WrEnergyMc0Ch0Dimm0 DmiAspm PchPcieHsioTxGen2DeEmph6p0Enable PchSataHsioTxGen1DeEmph RDEQT TxtDprMemoryBase WrEnergyMc1Ch0Dimm1 WrEnergyMc1Ch0Dimm0 DmiGen3EndPointHint CleanMemory PchSmbAlertEnable SaOcSupport PchSataHsioTxGen3DeEmph TxtImplemented CoreVfPointOffsetPrefix PchHdaTestPowerClockGating DmaControlGuarantee DIMMODTT ERDMPRTC2D RootPortIndex SkipStopPbet VtdIopEnable DmiGen3DsPortTxPreset ActiveCoreCount PchLpcEnhancePort8xhDecoding GtVoltageOffset DisPgCloseIdleTimeout ActEnergyMc1Ch0Dimm1 ActEnergyMc1Ch0Dimm0 Idd3n Idd3p PchSataHsioTxGen1DownscaleAmpEnable BClkFrequency ActEnergyMc0Ch0Dimm0 ActEnergyMc0Ch0Dimm1 DdrFreqLimit Gen3EqPhase23Bypass WrEnergyMc1Ch1Dimm0 DmiGen3DsPresetEnable PcieImrSize EWRTC2D IbeccOperationMode VtdBaseAddress TvbVoltageOptimization DciDbcMode HobBufferSize PchHdaSdiEnable PcieImrEnabled IdleEnergyMc0Ch1Dimm0 SerialIoUartDebugAutoFlow tCL PdEnergyMc0Ch0Dimm1 PdEnergyMc0Ch0Dimm0 RDTC2D ERDTC2D SerialIoUartDebugParity PchPcieHsioTxGen2DeEmph3p5Enable PchPcieHsioTxGen1DeEmph DmiGen3Ltcpo PchSmbusIoBase RaplPwrFlCh1 RaplPwrFlCh0 EnhancedInterleave PchPcieHsioTxGen2DeEmph6p0 MemTestOnWarmBoot Ibecc PanelPowerEnable BiosAcmBase DmiGen3UsPortRxPreset DmiAspmL1ExitLatency CmdMirror PchSataHsioTxGen2DownscaleAmpEnable tREFI CpuBclkOcFrequency CridEnable EpgEnable SmbusSpdWriteDisable DdrSpeedControl PchSataHsioRxGen2EqBoostMagEnable GtMaxOcRatio DmiMaxLinkSpeed PchSataHsioRxGen3EqBoostMagEnable PcieImrRpLocation CmdRanksTerminated SkipMbpHob SerialIoUartDebugTxPinMux PchSataHsioTxGen1DownscaleAmp PchPcieHsioTxGen3DownscaleAmp PerCoreRatioOverride PchHdaAudioLinkDmicClockSelect SerialIoUartDebugDataBits SrefCfgEna Avx512VoltageScaleFactor MmioSize SaVoltageOffset SaIpuEnable ActEnergyMc1Ch1Dimm0 ActEnergyMc1Ch1Dimm1 ProbelessTrace VtdIgdEnable ALIASCHK PchTraceHubMemReg0Size DIMMODTCA TgaSize EWRDSEQ SerialIoUartDebugStopBits RDTC1D CMDNORM RingVoltageMode EnableAbove4GBMmio WrEnergyMc1Ch1Dimm1 Txt PcieMultipleSegmentEnabled CnviDdrRfim FSP-S UPD: CpuMpPpi LidStatus ITbtConnectTopologyTimeoutInMs D3HotEnable D3ColdEnable PchLockDownGlobalSmi PchLockDownBiosInterface PchUnlockGpioPads RtcMemoryLock SkipPamLock EndOfPostMessage CpuUsb3OverCurrentPin PcieRpHotPlug SerialIoUartAutoFlow TccActivationOffset VmdEnable Enable8254ClockGating Enable8254ClockGatingOnS3 HybridStorageMode PcieRpHotPlug Hwp Cx PsOnEnable EnergyEfficientTurbo PchPmDisableEnergyReport UfsEnable FspEventHandler GnaEnable VbtSize PcieComplianceTestMode CStatePreWake SerialIoUartDataBits SataPortsExternal CstateLatencyControl0TimeUnit SataP0Tinact PmcV1p05PhyExtFetControlEn ApIdleManner SataPortsSpinUp DisableProcHotOut ITbtPcieTunnelingForUsb4 SerialIoUartDmaEnable SaPcieItbtRpNonSnoopLatencyOverrideMode SaPcieItbtRpSnoopLatencyOverrideMode MlcSpatialPrefetcher PchXhciOcLock PmcPowerButtonDebounce TccOffsetClamp LogoPixelWidth AvxDisable Custom1PowerLimit1 Custom1PowerLimit2 PmcCpuC10GatePinEnable PchPmSlpStrchSusUp IshI2cSdaPadTermination Custom2PowerLimit1Time RtcBiosInterfaceLock WatchDogTimerBios SataP1TDisp PchPciePort8xhDecodePortIndex PcieRpImrSelection TcCstateLimit PchS0ixAutoDemotion PchFivrExtV1p05RailEnabledStates PcieRpSlotPowerLimitScale IshUartCtsPinMuxing PcieRpSnoopLatencyOverrideMode TTCrossThrottling PsysPowerLimit1 SataRstInterrupt IshSpiClkPadTermination PcieEnablePeerMemoryWrite SataP1T2M ChipsetInitBinPtr LogoPixelHeight PsysPowerLimit1Time HwpInterruptControl DevIntConfigPtr IshUartRtsPadTermination PsysPowerLimit1Power EnergyEfficientTurbo Custom3TurboActivationRatio PcieDpc TurboMode PchFivrExtVnnRailSupportedVoltageStates ITbtDmaLtr IshSpiClkPinMuxing PchSbAccessUnlock PcieRpSystemErrorOnCorrectableError PcieRpSlotPowerLimitValue SendEcCmd SataSpeedLimit SataRstPcieEnable PchUsb3HsioCtrlAdaptOffsetCfg SataP0T2M PchHdaVerbTableEntryNum DmiTS1TW DmiTS2TW PcieRpImrEnabled GpioIrqRoute SataPortsSolidStateDrive RaceToHalt PcieRpNonSnoopLatencyOverrideMultiplier PcieRpUnsupportedRequestReport AesEnable PchFivrExtVnnRailSxVoltage SataP1Tinact PkgCStateUnDemotion SataPortsZpOdd PchSerialIoI2cPadsTermination PchFivrExtV1p05RailSupportedVoltageStates PchUsbLtrLowIdleTimeOverride IshSpiMosiPinMuxing PchProtectedRangeLimit SaPcieItbtRpNonSnoopLatencyOverrideValue SataP1T3M PchPmWoWlanEnable IshUartRtsPinMuxing SataLedEnable VmdGlobalMapping PcieRpEnableCpm IshGpGpioPadTermination PchDmiCwbEnable ForcMebxSyncUp FspEventHandler PchFivrExtVnnRailIccMax PchPmMeWakeSts DisableD0I3SettingForHeci PcieRpNonSnoopLatencyOverrideMode PmgCstCfgCtrlLock PchUsbLtrHighIdleTimeOverride Usb3HsioTxRate2UniqTran SiNumberOfSsidTableEntry IshSpiMisoPadTermination IshUartRxPadTermination PcieRpSlotImplemented PchUsbOverCurrentEnable EndOfPostMessage SaPcieItbtRpSnoopLatencyOverrideValue EnableHwpAutoEppGrouping SerialIoUartDbg2 ConfigTdpLock EsataSpeedLimit PchTsnEnable PowerLimit3DutyCycle TTSuggestedSetting PchEnableDbcObs IehMode VmdPort PchFivrExtVnnRailCtrlRampTmr PchPmSlpAMinAssert CstateLatencyControl5TimeUnit ProcessorTraceEnable ChipsetInitBinLen PchTemperatureHotLevel Usb3HsioTxRate3UniqTranEnable NumberOfEntries Custom2ConfigTdpControl PowerLimit3Lock SiCustomizedSsid PchUsb3HsioFilterSelP DisableVrThermalAlert PchIoApicEntry24_119 SmbiosType4MaxSpeedOverride PowerLimit3Time C1StateUnDemotion PchDmiAspmCtrl PchUsb3HsioFilterSelN PchTTEnable PcieRpNoFatalErrorReport Custom1ConfigTdpControl PmcC10DynamicThresholdAdjustment PchFivrVccinAuxRetToLowCurModeVolTranTime BiProcHot VmdPortFunc PchUsb3HsioFilterSelNEnable PchHdaVerbTablePtr TurboPowerLimitLock PcieRpSystemErrorOnNonFatalError PmcUsb2PhySusPgEnable PcieRpSystemErrorOnFatalError PchProtectedRangeBase VccSt PchFivrExtVnnRailSxEnabledStates EnableHwpAutoPerCorePstate CstateLatencyControl1TimeUnit SaPcieItbtRpSnoopLatencyOverrideMultiplier PchPmSlpS4MinAssert PcieRpTransmitterHalfSwing Usb3HsioTxRate3UniqTran RenderStandby ProcessorTraceOutputScheme SkipFspGop PchHdaPme EcCmdProvisionEav BgpdtHash Usb3HsioTxRate0UniqTran UsbOverride PkgCStateDemotion EnableAllThermalFunctions PchPmWolEnableOverride IshSpiCsPinMuxing PchIshSpiCsEnable IshUartCtsPadTermination PmcV1p05IsExtFetControlEn MaxRingRatioLimit PchIshPdtUnlock IshUartTxPinMuxing PchFivrExtV1p05RailIccMax BiosGuardAttr LogoPtr CpuBistData ShowSpiController PchPmWolOvrWkSts SataP0T1M CstCfgCtrIoMwaitRedirection TcoIrqEnable PchHdaLinkFrequency ITbtForcePowerOnTimeoutInMs SerialIoSpiCsEnable VmdMemBar2Base TStates SiSkipSsidProgramming TccOffsetTimeWindowForRatl AmtSolEnabled PchUsb3HsioCtrlAdaptOffsetCfgEnable PchFivrExtVnnRailIccMaximum PchEspiLgmrEnable SkipPamLock IshGpGpioPinMuxing PchUsb3HsioFilterSelPEnable PchFivrExtVnnRailVoltage SataPortsDevSlpResetConfig ProcHotLock PchDmiTsawEn SerialIoSpiCsPolarity PkgCStateLimit EnableRsr PmcDbgMsgEn PchPmPwrCycDur NumOfDevIntConfig SerialIoSpiDefaultCsOutput PchPmPciePllSsc PxRcConfig CstateLatencyControl4TimeUnit PcieRpPmSci ConfigTdpBios PmcPdEnable PchT1Level PmcModPhySusPgEnable DisableTurboGt EnableTcoTimer IshSpiMisoPinMuxing IshI2cSclPinMuxing PcieRpCorrectableErrorReport C1StateAutoDemotion PchEspiLockLinkConfiguration PchFivrExtV1p05RailCtrlRampTmr SataRstPcieStoragePort PchFivrExtV1p05RailVoltage PchPmSlpSusMinAssert PchHotEnable PcieRpNonSnoopLatencyOverrideValue TcoIrqSelect PcieRpCompletionTimeout FwProgress StateRatioMax16 ConfigTdpLevel IshI2cSdaPinMuxing PcieRpPhysicalSlotNumber SerialIoUartParity TxtEnable PchLegacyIoLowLatency PchUsbLtrMediumIdleTimeOverride PchPmPmeB0S5Dis SerialIoUartPowerGating PcieRpSnoopLatencyOverrideValue PchPmSlpLanLowDc PchT2Level CstateLatencyControl2TimeUnit PchPmSlpS3MinAssert PchUsb3HsioOlfpsCfgPullUpDwnResEnable MonitorMwaitEnable Usb3HsioTxRate1UniqTran Eist IshSpiMosiPadTermination PowerLimit4Lock Custom3PowerLimit1Time PcieEnablePort8xhDecode DualTauBoost WatchDogEnabled MaxRatio Custom2TurboActivationRatio PchFivrExtVnnRailEnabledStates ApplyConfigTdp IshI2cSclPadTermination PowerLimit2Power ThermalMonitor CpuUsb3OverCurrentPin PchTTLock Custom1PowerLimit1Time PchEspiHostC10ReportEnable Usb3HsioTxRate2UniqTranEnable SataPortsInterlockSw EnablePerCorePState PsysPowerLimit2Power UfsEnable PchPmDisableNativePowerButton VmdVariablePtr Custom3PowerLimit2 PchPmDisableEnergyReport Custom3PowerLimit1 DmiTS3TW EnforceEDebugMode CstateLatencyControl3TimeUnit VmdCfgBarBase DmiSuggestedSetting SataPortsEnableDitoConfig SerialIoUartBaudRate Usb3HsioTxRate1UniqTranEnable SataPortsHotPlug MachineCheckEnable Custom1TurboActivationRatio Custom2PowerLimit1 Custom2PowerLimit2 VmdMemBar1Base SaPcieItbtRpLtrConfigLock SataP0TDispFinit PchFivrExtVnnRailSxIccMaximum PchTsnLinkSpeed SataThermalSuggestedSetting SaPcieItbtRpLtrEnable TimedMwait PchTsnMultiVcEnable PcieRpFunctionSwap PcieEqOverrideDefault SataP1T1M PsysPowerLimit2 PchLanLtrEnable SerialIoUartStopBits SciIrqSelect C1e PchFivrExtVnnRailSxIccMax PowerLimit3 PowerLimit2 PowerLimit1 MeUnconfigOnRtcClear PcieRpPcieSpeed PchUsbLtrOverrideEnable UsbPdoProgramming Custom3ConfigTdpControl SataP1TDispFinit PchFivrDynPm VmdPortDev EnableItbm MinRingRatioLimit PcieRpFatalErrorReport MctpBroadcastCycle EcCmdLock StateRatio PchPmVrAlert DmiTS0TW LogoSize PchIoApicId SaPcieItbtRpForceLtrOverride PcieRpSnoopLatencyOverrideMultiplier IshUartTxPadTermination PchCrid SataRstPcieDeviceResetDelay ProcHotResponse BltBufferSize MlcStreamerPrefetcher PcieRpLtrConfigLock SiSsidTablePtr SataP0TDisp PchUsb3HsioOlfpsCfgPullUpDwnRes BltBufferAddress PcieRpDetectTimeoutMs PpinSupport SataRstRaidDeviceId PchPmLatchEventsC10Exit IshUartRxPinMuxing PpmIrmSetting EnergyEfficientPState PchFivrExtV1p05RailIccMaximum PortResetMessageEnable PchReadProtectionEnable BiosGuardModulePtr PchWriteProtectionEnable AmtEnabled PchHdaCodecSxWakeCapability SiCustomizedSvid PcieEdpc TccOffsetLock PchPmPwrBtnOverridePeriod SaPcieItbtRpNonSnoopLatencyOverrideMultiplier WatchDogTimerOs PchTTState13Enable PowerLimit1Time PchT0Level IshSpiCsPadTermination SataP0T3M Usb3HsioTxRate0UniqTranEnable SataTestMode PmcOsIdleEnable PowerLimit4 PcieRpAcsEnabled PavpEnable UsbTcPortEn Additionally, optimize the `reserved` fields across header files. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I976a5762701711fbf000c43c5ff05f9bd93f688f Reviewed-on: https://review.coreboot.org/c/coreboot/+/65455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* vc/intel/fsp/mtl: Update header files from 2173_00 to 2222_01 for MTLSrinidhi N Kaushik2022-06-232-1208/+1270
| | | | | | | | | | | | | | | | | | | | | | Update header files for FSP for Meteor Lake platform to version 2222_01, previous version being 2173_00. FSPM: Includes below 2 UPDs 1. TdcEnable 2. TdcTimeWindow FSPS: Address Offset changes. BUG=b:234701164 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I529118c35fa9f851ee2b5f23712ac70e2a5b53c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64878 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* vc/intel/fsp/fsp2_0/mtl: Add FSP header files (2173_00) for Meteor LakeSrinidhi N Kaushik2022-06-095-0/+6805
Add header files generated from FSP 2173_00 source build for Meteor Lake platform. BUG=b:234701164 TEST=util/abuild/abuild -p none -t google/rex -a -c max Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: I8b1caa4bc09f09005859e6c8853d14b8f96a26ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/64883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-23 07:58:44 +0000