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* soc/intel/skylake: Add option to control microcode update inclusionWim Vervoorn2019-12-062-0/+34
| | | | | | | | | | | | | | | | | | | | | | On embedded boards the cpu mounted on the board is known. So it is not required to include microcode for all possible Sky Lake and Kaby Lake cpus. This patch provides the possibility to only support the versions required. By default all microcode updates will be included and the versions not required can be removed using Kconfig. BUG=N/A TEST=build Change-Id: Iaa36c2846b2279a2eb2b61e6c97d6c89d0736f55 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* console,monotonic_timer: Avoid calls from APsKyösti Mälkki2019-12-061-3/+3
| | | | | | | | | | | | | | The code in cpu/x86/lapic/apic_timer.c for timer_monotonic_get() is not SMP safe as LAPIC timers do not run as synchronised as TSCs. The times reported for console for boot_states does not accumulate from APs now. Also remove console time tracking from ENV_SMM. Change-Id: I1ea2c1e7172f8ab3692b42dee3f669c5942d864a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37398 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.Philipp Hug2019-12-066-25/+14
| | | | | | | | | | TEST=Set MAX_CPUS=2 and run qemu with -smp 2 Signed-off-by: Philipp Hug <philipp@hug.cx> Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
* nb/i945: Fix typoElyes HAOUAS2019-12-061-1/+1
| | | | | | | | Change-Id: I082ac2c1c13cbe6835a02d703f8651e837a43f37 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* endian: Replace explicit byte swapping with compiler builtinJulius Werner2019-12-061-0/+6
| | | | | | | | | | | | | | | gcc seems to have some stupid problem with deciding when to inline byte swapping functions (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=92716). Using the compiler builtin instead seems to solve the problem. (This doesn't yet solve the issue for the read_be32()-family of functions, which we should maybe just get rid of at some point?) Change-Id: Ia2a6d8ea98987266ccc32ffaa0a7f78965fca1cd Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* superio/smsc/lpc47n207: Remove unused <stdint.h>Elyes HAOUAS2019-12-061-2/+0
| | | | | | | | Change-Id: I9e6b2548ff7eb7224b15ffa2541922790816c947 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37509 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* superio/nsc/pc87417: Remove unused <stdint.h>Elyes HAOUAS2019-12-061-1/+0
| | | | | | | | Change-Id: Icacf2806702a868a807080e1e2d14b1ee4ed4f90 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37507 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* src/superio/via: Remove unused superio chipsElyes HAOUAS2019-12-061-16/+0
| | | | | | | | | Change-Id: I248608361fcdc51ff435222d37c5bbc736b1947e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* superio/fintek: Fix typoElyes HAOUAS2019-12-062-5/+5
| | | | | | | | | | Change-Id: If5c0921e20b26ce558f542f405cf62ae8d4a8101 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* vboot: Clear secdata change flags after factory initJulius Werner2019-12-062-7/+9
| | | | | | | | | | | | | | | | | | | | factory_initialize_tpm() calls secdata_xxx_create() (for both firmware and kernel space) and then immediately writes those spaces out to the TPM. The create() functions make vboot think it just changed the secdata (because it reinitialized the byte arrays in the context), so we also need to clear the VB2_CONTEXT_SECDATA_xxx_CHANGED flags again, otherwise vboot thinks it still needs to flush the spaces out to the TPM even though we already did that. Also clean up some minor related stuff (VB2_CONTEXT_SECDATA_CHANGED notation is deprecated, and secdata space intialization should use the same write-and-readback function we use for updates). Change-Id: I231fadcf7b35a1aec3b39254e7e41c3d456d4911 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37471 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* vboot: update VbExNvStorageWrite functionJoel Kitching2019-12-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Going forwards, vb2ex_commit_data will be used to flush both nvdata and secdata. The patch that is circularly dependent on this lies between a patch that makes vboot no longer build and the patch that fixes that, so we have to pull the whole thing in at once to sort out the mess. Updating from commit id 1c4dbaa0: 2019-11-18 Julius Werner Makefile: Fix typo for MOCK_TPM to commit id 695c56dc: 2019-12-04 Julius Werner Makefile: Make loop unrolling fully controllable by the caller BUG=b:124141368, chromium:1006689 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ia2612da0df101cd3c46151dbce728633a39fada1 Signed-off-by: Joel Kitching <kitching@google.com> Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* hatch: Fix FPMCU pwr/rst gpio handlingCraig Hesling2019-12-0510-22/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. No gpio control in bootblock 2. Disable power and assert reset in ramstage gpio 3. Power on and then deassert reset at the end of ramstage gpio 4. Disable power and assert reset when entering S5 On "reboot", the amount of time the power is disabled for is equivalent to the amount of time between triggering #4 and wrapping around to #3, which is about 400ms on Kohaku. Since #2 forces power off for FPMCU, S3 resume will still not work properly. Additionally, we must ensure that GPP_A12 is reconfigured as an output before going to any sleep state, since user space could have configured it to use its native3 function. See https://review.coreboot.org/c/coreboot/+/32111 for more detail. The control signals have been validated on a Kohaku in the following scenarios: 1. Cold startup 2. Issuing a "reboot" command 3. Issuing a "halt -p" and powering back on within 10 seconds 4. Issuing a "halt -p" and powering back on after 10 seconds 5. Entering and leaving S3 (does not work properly) 6. Entering and leaving S0iX BRANCH=hatch BUG=b/142751685 TEST=Verify all signals as mentioned above TEST=reboot flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on within 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin TEST=halt -p # power back on after 10 seconds flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* mb/intel/coffeelake_rvp: Switch to overridetree setupGaggery Tsai2019-12-057-301/+171
| | | | | | | | | | | | | | This patch moves the common devicetree settings into baseboard and creates overridetree.cb for each variant. For PCIe root port settings, SATA, eMMC, I2Cs and GBe, they are in overridetree. TEST=build an image for each variant Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36794 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/qualcomm/sc7180: Adapt to recent API changesPatrick Georgi2019-12-052-17/+17
| | | | | | | | | | | | | | | | | Definitions were moved so that now device/mmio.h needs to be included instead of arch/mmio.h. Also, don't use le32 conversion. This follows the activities of commit 55009af42 (Change all clrsetbits_leXX() to clrsetbitsXX()) and commit 1c371572188 (mmio: Add clrsetbitsXX() API in place of updateX()). Change-Id: Ie3af0d4f0b3331fe5572fc56915952547b512db7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37534 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/braswell: Use common sb code for SPI lockdown configurationArthur Heymans2019-12-056-194/+22
| | | | | | | | | | | | This removes the weakly linked function to configure the SPI lockdown. Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/intel/icelake_rvp: Remove nested variant header referencesAamir Bohra2019-12-0514-797/+7
| | | | | | | | Change-Id: I11b2d75dc0d4ff180b03324e5ce3d5590c8169a5 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
* arm64: Print a char to UART early in exception handlerJulius Werner2019-12-051-2/+8
| | | | | | | | | | | | | | | | | | | | | Over time our printk() seems to acquire more and more features... which is nice, but it also makes it a little less robust when something goes wrong. If the wrong global is trampled by some buffer overflow, it suddenly doesn't print anymore. It would be nice to have at least some way to tell that we triggered a real exception in that case. With this patch, arm64 exceptions will print a '!' straight to the UART before trying any of the more fancy printk() stuff. It's not much but it should tell the difference between an exception and a hang and hopefully help someone dig in the right direction sooner. This violates loglevels (which is part of the point), but presumably when you have a fatal exception you shouldn't care about that anymore. Change-Id: I3b08ab86beaee55263786011caa5588d93bbc720 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37465 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* arm64: Bump exception stack size to 2KBJulius Werner2019-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | | To avoid trampling over interesting exception artifacts on the real stack, our arm64 systems switch to a separate exception stack when entering an exception handler. We don't want that to use up too much SRAM so we just set it to 512 bytes. I mean it just prints a bunch of registers, how much stack could it need, right? Quite a bit it turns out. The whole vtxprintf() call stack goes pretty deep, and aarch64 generally seems to be very generous with stack space. Just the varargs handling seems to require 128 bytes for some reason, and the other stuff adds up too. In the end the current implementation takes 1008 bytes, so bump the exception stack size to 2K to make sure it fits. Change-Id: I910be4c5f6b29fae35eb53929c733a1bd4585377 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* arm64: Correctly unmask asynchronous SError interruptsJulius Werner2019-12-055-129/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arm CPUs have always had an odd feature that allows you to mask not only true interrupts, but also "external aborts" (memory bus errors from outside the CPU). CPUs usually have all of these masked after reset, which we quickly learned was a bad idea back when bringing up the first arm32 systems in coreboot. Masking external aborts means that if any of your firmware code does an illegal memory access, you will only see it once the kernel comes up and unmasks the abort (not when it happens). Therefore, we always unmask everything in early bootblock assembly code. When arm64 came around, it had very similar masking bits and we did the same there, thinking the issue resolved. Unfortunately Arm, in their ceaseless struggle for more complexity, decided that having a single bit to control this masking behavior is no longer enough: on AArch64, in addition to the PSTATE.DAIF bits that are analogous to arm32's CPSR, there are additional bits in SCR_EL3 that can override the PSTATE setting for some but not all cases (makes perfect sense, I know...). When aborts are unmasked in PSTATE, but SCR.EA is not set, then synchronous external aborts will cause an exception while asynchronous external aborts will not. It turns out we never intialize SCR in coreboot and on RK3399 it comes up with all zeroes (even the reserved-1 bits, which is super weird). If you get an asynchronous external abort in coreboot it will silently hide in the CPU until BL31 enables SCR.EA before it has its own console handlers registered and silently hangs. This patch resolves the issue by also initializing SCR to a known good state early in the bootblock. It also cleans up some bit defintions and slightly reworks the DAIF unmasking... it doesn't actually make that much sense to unmask anything before our console and exception handlers are up. The new code will mask everything until the exception handler is installed and then unmask it, so that if there was a super early external abort we could still see it. (Of course there are still dozens of other processor exceptions that could happen which we have no way to mask.) Change-Id: I5266481a7aaf0b72aca8988accb671d92739af6f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* trogdor: Add mainboard USB supportT Michael Turney2019-12-052-1/+25
| | | | | | | | Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7 Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* sc7180: Add USB supportT Michael Turney2019-12-055-0/+886
| | | | | | | | | | | This includes USB QUSB2,QMP Phy and Controller support And libpayload support for USB Change-Id: I0651fc28dc227efbeb23eeefe9b96a3b940ae995 Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35503 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* sc7180: Add AOP firmware supportRavi Kumar Bokka2019-12-057-2/+85
| | | | | | | | | | | Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85 Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: Ashwin Kumar <ashk@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* sc7180: Add SPI-NOR supportAkash Asthana2019-12-056-3/+452
| | | | | | | | | | | | | | This implements the SPI-NOR driver for the Qualcomm QSPI core. Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/27483/58 Change-Id: I2eb8cf90aa4559541ba293b3fd2870896bed20b7 Signed-off-by: Akash Asthana <akashast@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35501 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* superio/fintek/f81866d: capitalize 'TODO'Elyes HAOUAS2019-12-051-1/+1
| | | | | | | | Change-Id: I2879a8739012863837e23e60fed5eb6ee209dea0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37504 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* superio/serverengines/pilot: Fix typoElyes HAOUAS2019-12-051-1/+1
| | | | | | | | | Change-Id: Ic7cd93150252b2e5235c82c8c63540059b68d22b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* superio/smsc/lpc47n2{17,27}: Fix typoElyes HAOUAS2019-12-052-2/+2
| | | | | | | | | Change-Id: I29a42908af5699200216b7a0082e1417c90c95a6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* superio/ite/it8528e: Fix typoElyes HAOUAS2019-12-051-1/+1
| | | | | | | | | Change-Id: I40035bf622fea2ff7aed74dce125cbf6265afa6e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* superio/{aspeed,nuvoton}: Fix typoElyes HAOUAS2019-12-052-4/+4
| | | | | | | | | Change-Id: I7772fadc756ceeef5988e4b1ecf8f93ad3605a84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/asrock/h110m: disable CLKREQ to use onboard LANMaxim Polyakov2019-12-051-4/+2
| | | | | | | | | | | | | | | | | The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in order to send clock signal to it. However, this logic is not required for the Realtek LAN device, since this chip is soldered to the board and always uses clocking. The chipset can't receive the clock request signal (most likely this pin isn't connected) and doesn't enable the CLK. For this reason, the device is broken during the initialization phase. The patch disables clock request logic for the PCH PCIe port 6 to initialize the onboard LAN device correctly. Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36377 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "mb/google/hatch: Enable PchPmSlpS0Vm075VSupport for hatch"Kane Chen2019-12-051-2/+0
| | | | | | | | | | | | | | | | This reverts commit 0bc35af93326ec3232ec73c9b1334241b85f0252. Reason for revert: This change breaks runtime s0ix. BRANCH=hatch BUG=b:141831197 TEST=Check slp_s0 residency increased when system is idle. Change-Id: Ida80f55b56de7129ed629eb29bd14f2ef300126f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
* sc7180: Add clock driverTaniya Das2019-12-055-1/+448
| | | | | | | | | | | | | Add support for clock driver for SC7180 Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/31083/6 Change-Id: I3f39252c887c36e8af43bc49289795000e4638d8 Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* sb/amd/cimx/sb800: add C bootblock southbridge initializationMichał Żygowski2019-12-042-4/+23
| | | | | | | | | | | TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ie81198f5034a84d319ee7143aa032433f82be254 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37329 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* sb/amd/{agesa,pi}/hudson: add southbridge C bootblock initializationMichał Żygowski2019-12-048-18/+177
| | | | | | | | Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaba5443d8770473c4abe73ec2a91f8d6a52574af Reviewed-on: https://review.coreboot.org/c/coreboot/+/37168 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Change all clrsetbits_leXX() to clrsetbitsXX()Julius Werner2019-12-04107-2023/+2020
| | | | | | | | | | | | | | | | | | | This patch changes all existing instances of clrsetbits_leXX() to the new endian-independent clrsetbitsXX(), after double-checking that they're all in SoC-specific code operating on CPU registers and not actually trying to make an endian conversion. This patch was created by running sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g' across the codebase and cleaning up formatting a bit. Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mmio: Add clrsetbitsXX() API in place of updateX()Julius Werner2019-12-044-53/+21
| | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the recently added update8/16/32/64() API and replaces it with clrsetbits8/16/32/64(). This is more in line with the existing endian-specific clrsetbits_le16/32/64() functions that have been used for this task on some platforms already. Rename clrsetbits_8() to clrsetbits8() to be in line with the new naming. Keep this stuff in <device/mmio.h> and get rid of <mmio.h> again because having both is confusing and we seem to have been standardizing on <device/mmio.h> as the standard arch-independent header that all platforms should include already. Also sync libpayload back up with what we have in coreboot. (I'm the original author of the clrsetbits_le32-definitions so I'm relicensing them to BSD here.) Change-Id: Ie4f7b9fdbdf9e8c0174427b4288f79006d56978b Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37432 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/octopus: Create Lick variantHash.Hung2019-12-048-0/+234
| | | | | | | | | | | | | | | | | | | Create new variant for Lick that is copied from phaser variant. Remove unnecessary code, due to not support touchscreen and stylus. Set to default_override_table. Remove variant.c. BUG=b:145181137 BRANCH=octopus TEST=./util/abuild/abuild -p none -t google/octopus -x -a Change-Id: If732d94194defb9f5ee9c847ee93dd58aef01174 Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37247 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/drallion/variants/drallion: Adjust all I2C CLK to meet specJohn Su2019-12-041-6/+6
| | | | | | | | | | | | | | | | | | After adjustment on Drallion Touch Pad CLK: 393 KHz Touch Screen CLK: 381 KHz H1 CLK: 391 KHz BUG=b:144245601 BRANCH=master TEST=emerge-drallion coreboot chromeos-bootimage measure by scope with drallion. Change-Id: Id669d7199bc6ed4b55d7542f095c6c8baf00f984 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37230 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/kohaku: Adjust I2C clock frequencySeunghwan Kim2019-12-041-2/+4
| | | | | | | | | | | | | | | | | | | | | | All serial I2C bus frequencies should not be over 400KHz in kohaku, but the measurement showed frequencies of I2C1 and I2C4 were over 400KHz. (b:144885961) This change adjusts I2C speed settings to limit that frequencies to 400KHz. The new setting values have been from other projects using same I2C components, and verified I2C1 and I2C4 frequencies < 400MHz internally. BUG=b:144885961 BRANCH=firmware-hatch-12672.B TEST=Verified I2C1 and I2C4 frequency not over 400KHz Change-Id: I9614fb39b6e55cb2ce1b0879a9f5204e55002f8d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/hatch/var/akemi: tune DPTF for AkemiPeichao Wang2019-12-041-37/+42
| | | | | | | | | | | | | | | Tune DPTF to ensure compliance with Akemi thermal design requirements BUG=b:144195069 TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec chromeos-bootimage Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ie0e6d93e1fc0c684e067d1450eb119a53cfefaed Reviewed-on: https://review.coreboot.org/c/coreboot/+/36716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* AGESA: Reduce S3_DATA_SIZEKyösti Mälkki2019-12-041-1/+1
| | | | | | | | | | | Make some room for C environment bootblock. The S3 resume feature needs less than 2 KiB. Change-Id: Ic49c313d492f1d18f59d61e84f81f106e3b41fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
* amdblocks/acpimmio: add common functions for AP entryMichał Żygowski2019-12-047-53/+18
| | | | | | | | | | | | | Move the stoneyridge implementation of get/set AP entry to the common block. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I9c73940ffe5f735dcd844911361355c384f617b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
* amdblocks/acpimmio: Unify BIOSRAM usageMichał Żygowski2019-12-0415-198/+72
| | | | | | | | | | | | | | | | | | | | All AMD CPU families supported in coreboot have BIOSRAM space. Looking at the source code, every family could have the same API to save and restore cbmem top or UMA base and size. Unify BIOSRAM layout and add implementation for cbmem top and UMA storing. Also replace the existing implementation of cbmem top and UMA with the BIOSRAM access. TEST=boot PC Engines apu1 and apu2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I69a03e4f01d7fb2ffc9f8b5af73d7e4e7ec027da Reviewed-on: https://review.coreboot.org/c/coreboot/+/37402 Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/common/block/acpimmio: fix ACPIMMIO decode enable functionMichał Żygowski2019-12-045-14/+33
| | | | | | | | | | | | | | | | | | | According to BKDGs for families 15h 60-6fh or newer and families 16h the ACPI MMIO decode enable bit is the second LSB, not the first LSB. Additionally create another enable function for older families where the register and bit is different. It does not seem to impact any current board, but may be crucial for incoming C bootblock implementations when this bit will need to be set very early. Most likely this bit is set by AGESA right now. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iaa31abc3dbdf77d8513fa83c7415b9a1b7fd266f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37178 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* binaryPI: Fix failing AP startupKyösti Mälkki2019-12-043-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix regression with commit 5639736 binaryPI: Drop CAR teardown without POSTCAR_STAGE Occassionally (maybe 1 boot in 10) SMP lapic_cpu_init() fails with following errors in the logs of pcengines/apu2: CPU 0x03 would not start! CPU 0x03 did not initialize! The CPU number is sometimes 0x02, never seen 0x01. Work-around also suggests something to do with cache coherency and MTRRs that is really at fault. As a work-around return the BSP CAR teardown to use wbinvd instead of invd. These platforms do not support S3 resume so this is the easy work-around for the time being. Change-Id: I3dac8785aaf4af5c7c105ec9dd0b95156b7cca21 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lib/imd_cbmem: Rename imd_cbmem into imd, use directlyPatrick Georgi2019-12-031-39/+22
| | | | | | | | | Change-Id: I70e9d9f769831087becbf42dcfb774d8f2638770 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lib/imd_cbmem: Remove the indirections that hide imd_cbmemPatrick Georgi2019-12-031-63/+10
| | | | | | | | | Change-Id: Ie68c6e2ebe56a5902a7665bf62119302146f5928 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37362 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/imd_cbmem: Eliminate unnecessary NULL checkPatrick Georgi2019-12-031-10/+1
| | | | | | | | | | &imd_cbmem is never NULL, so remove that path Change-Id: Ib9a9c88d6cd4842df447f046bc0abaa7ef5032c7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* hatch: Create stryke variantDtrain Hsu2019-12-038-0/+412
| | | | | | | | | | | | | | (Auto-Generated by create_coreboot_variant.sh version 1.0.0). BUG=b:145101696 TEST=util/abuild/abuild -p none -t google/hatch -x -a make sure the build includes GOOGLE_STRYKE Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* src: Add missing include <stdlib.h>Elyes HAOUAS2019-12-035-0/+5
| | | | | | | | Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* mb/google/drallion: Disable GPIO dynamic PM configurationSubrata Banik2019-12-033-19/+21
| | | | | | | | | | | BUG=b:144002424 TEST=Ensured no TPM time out issue and system can boot to OS Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37320 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-10 10:31:46 +0000