summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* cpu/x86: Clean up includesElyes Haouas2022-10-2610-9/+18
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I01c6651079333686cb0eb68e89e56d7907868124 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* cpu/intel: Clean up includesElyes Haouas2022-10-264-10/+12
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ie760711916c49d275ca49d94b9597fd24b5e7628 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* src/commonlib: Clean up includesElyes Haouas2022-10-262-0/+2
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ieba5a5291209e50dc8b3816efb25bb5b2515fa6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/68201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* arch/x86: Clean up includesElyes Haouas2022-10-267-9/+16
| | | | | | | | Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id2db229dec2ed44333faaa8c53f3a2f9d66d52e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/amd/mendocino: Add GSVCD rangeKarthikeyan Ramasubramanian2022-10-262-0/+25
| | | | | | | | | | | | | | Add region/range of SPI ROM to be verified by Google Security Chip (GSC). BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Change-Id: If8a766d9a7ef26f94e3ab002a9384ba9d444dd1f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/mendocino: Update build rules for PSP BIOS imageKarthikeyan Ramasubramanian2022-10-261-0/+6
| | | | | | | | | | | | | | | | Do not compress PSP BIOS image when CBFS verification is enabled. Otherwise when a file is added to CBFS, cbfstool is not able to find the metadata hash anchor magic in the compressed PSP BIOS image. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled for both x86 and PSP verstage. Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* soc/amd/mendocino: Reserve more space for metadataKarthikeyan Ramasubramanian2022-10-261-2/+2
| | | | | | | | | | | | | | | | With CBFS verification enabled, CBFS file header + file name + metadata consumes more than 64 bytes. Hence reserve additional space aligned to the next 64 bytes. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Change-Id: I2b7346e2150835443425179048415f3b27d89d89 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66944 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd: Add amdfw.rom in coreboot.preKarthikeyan Ramasubramanian2022-10-265-20/+12
| | | | | | | | | | | | | | | | This change ensures that amdfw.rom binary containing metadata hash anchor is added before any file is added to CBFS. This will allow to verify all the CBFS files that are not excluded from verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 and PSP verstages. Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/cbfstool: Check for metadata hash in verstageKarthikeyan Ramasubramanian2022-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | Metadata Hash is usually present inside the first segment of BIOS. On board where vboot starts in bootblock, it is present in bootblock. On boards where vboot starts before bootblock, it is present in file containing verstage. Update cbfstool to check for metadata hash in file containing verstage besides bootblock. Add a new CBFS file type for the concerned file and exclude it from CBFS verification. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 and PSP verstages. Change-Id: Ib4dfba6a9cdbda0ef367b812f671c90e5f90caf8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66942 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd: Add an optional unsigned section in PSP verstageKarthikeyan Ramasubramanian2022-10-261-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | To enable RO CBFS verification in AMD platforms with PSP verstage, metadata hash for RO CBFS is kept as part of verstage. This means any updates to RO CBFS, before WP is enabled, requires updating the metadata hash in the verstage. Hence keep the metadata hash outside the signed range of PSP verstage. This means the metadata hash gets loaded as part of loading PSP verstage while still being excluded from the verification of PSP verstage. This change keeps the metadata hash outside the PSP footer data. This will help to keep it outside the signed range of PSP verstage & aligned to 64 bytes. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled with both x86 and PSP verstage. Change-Id: I308223be8fbca1c0bec8c2e1c86ed65d9f91b966 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68135 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lib/metadata_hash: Include metadata_hash in verstageKarthikeyan Ramasubramanian2022-10-261-0/+4
| | | | | | | | | | | | | | | | | On boards where vboot starts before bootblock, build metadata_hash in verstage. This will allow to enable CBFS verification for such platforms. BUG=b:227809919 TEST=Build and boot to OS in Skyrim with CBFS verification enabled using x86 verstage and PSP verstage. Change-Id: I4269069b66ed66c7b1a47fdef2fd0a8054b2e6a1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68134 Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Add build rules for amdfwreadKarthikeyan Ramasubramanian2022-10-261-0/+4
| | | | | | | | | | | | | | Add build rules to build amdfwread tool. Also mark this as a dependency either while building tools or amdfw.rom. BUG=None TEST=Build and boot to OS in Skyrim with CBFS verification enabled. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* coreboot_tables: Drop uart PCI addrArthur Heymans2022-10-2616-40/+0
| | | | | | | | | | | | | | | Only edk2 used this to fill in a different struct but even there the entries go unused, so removing this struct element from coreboot has no side effects. Change-Id: Iadd2678c4e01d30471eac43017392d256adda341 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKEDavid Wu2022-10-261-0/+1
| | | | | | | | | | | | | | | | | | | | | Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as kano is using a converged firmware image. BUG=b:253337338 BRANCH=firmware-brya-14505.B TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", disable hardware write protect and software write protect, flash and boot kano in end-of-manufacturing mode to kernel. Cq-Depend: chrome-internal:5046060, chromium:3967356 Change-Id: I75da3af530e0eafdc684f19ea0f6674f6dc10f01 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/prodrive/atlas: Disable S3Maximilian Brune2022-10-261-1/+0
| | | | | | | | | | | | | The Atlas board has currently the problem that suspending the System causes the System to freeze. Therefore disable S3, until the cause is figured out and fixed. Change-Id: I5b28787df9b01683fcd4a1de8267840a80bb4fe6 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68591 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Move `DRIVERS_INTEL_USB4_RETIMER` configSubrata Banik2022-10-262-1/+1
| | | | | | | | | | | | | | | | This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake SoC to Rex mainboard to maintain the symmetry with previous generation ChromeOS devices (Brya and Volteer). BUG=none TEST=Able to build and boot to Google/Rex with USB4 functionality remaining intact. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* cpu/x86/Kconfig: Enable LAPIC remap mitigation on likely affect NBArthur Heymans2022-10-261-3/+3
| | | | | | | | | | | | | Pre-sandy bridge hardware is likely affected by the sinkhole vulnerability. Intel sandy bridge and newer has hardware mitigations against this attack according to https://github.com/xoreaxeaxeax/sinkhole. Change-Id: I52cb20e0edac62475597b31696f38d0ffc6080de Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* soc/amd: Add framework for Glinda SoCMartin Roth2022-10-2558-0/+5419
| | | | | | | | | | | | | | This adds the initial framework for the Glinda SoC, based on what's been done for Morgana already. I believe that there's more that can be made common, but that work will continue as both platforms are developed. Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
* soc/intel/alderlake: Add Raptor Lake device IDsLawrence Chang2022-10-257-0/+10
| | | | | | | | | | | | | | | | Add system agent ID for RPL QDF# Q271 TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is gone Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kane Chen <kane.chen@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/skyrim/var/frostflow: Update devicetree settingFrank Wu2022-10-251-1/+118
| | | | | | | | | | | | | | | | | | Update devicetree based on the schematic_20221014. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Ia03962b0e01394ddcd4971cbe0172ef5bd913e15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68482 Reviewed-by: Chao Gui <chaogui@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
* mb/google/kahlee/liara/devicetree: move Raydium touchscreen to baseboardFelix Held2022-10-252-14/+12
| | | | | | | | | | | | | | | | | | Move the Raydium touchscreen to the baseboard devicetree. Since only the liara variant uses a level IRQ as I2C devices are supposed to, all other board variants still override this to use an edge IRQ which were added as a workaround to make the touchscreen work on the other devices. Right now it's unclear to me if that edge IRQ workaround was only needed temporarily and can now be removed, so I'll keep it as it was for now. If this turns out to be no longer needed on the other variants, the overrides can be dropped in the future. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic621c1a5856e9e280a25b0668010a1ee5bbb61e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68770 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* console: Add an SoC-specific post-code callMartin Roth2022-10-252-0/+4
| | | | | | | | | | | Add a post-code call that SoCs can hook to output or save in any way that is specific to that SoC. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0369e4362840d7506d301105d8e1e2fd865919f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68545 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* soc/intel/common: Clean up includesElyes Haouas2022-10-2516-7/+34
| | | | | | | | | Change-Id: I0081fcf3c842d8772a7045f8dc5754a2e6c039b8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68702 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/intel/tigerlake: Clean up includesElyes Haouas2022-10-2512-4/+18
| | | | | | | | Change-Id: I9c75e900d05d16de830c750f074df84bb17f64dc Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
* ec/google/wilco/superio: Fix PS2K under WindowsMatt DeVillier2022-10-251-0/+3
| | | | | | | | | | | | | | PS2K device needs to be under PCI0, not LPCB, for Windows to recognize it. Same change was made to ChromeEC previously. Test: Boot Win11 on Drallion, verify built-in keyboard functional. Change-Id: I12019592dfa1d869ba57c1ff6c25ac6bdeb7a300 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68463 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
* soc/intel/xeon_sp: Add functions to store/restore uart state in smmTim Chu2022-10-251-0/+43
| | | | | | | | | | | | | | | When CONFIG_DEBUG_SMI is enabled SMM handler performs console hardware initialization that may interfere with OS. Here we store the state before console initialization and restore state before SMM exit. Tested=On not public yet system, after exiting smm, uart console can still work well. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
* src/drivers/uart: Add definition of FIFO enabled in IIRTim Chu2022-10-251-0/+1
| | | | | | | | | | | | | Interrupt Identification Register (IIR) is a I/O read-access register. Add definition of FIFO enabled for this register so that we can check whether FIFO is enabled or not. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I12e8566822693004418cf83cae466dc3e2d612c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68566 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/elkhartlake: Fix incorrect divider for MDIO clockWerner Zeh2022-10-252-3/+3
| | | | | | | | | | | | | | | | | | After some measurements it turned out that Elkhart Lake uses a higher CSR clock internally from which the MDIO clock is derived. In order to stay compliant with the specification, the MDIO clock needs to be lower than 2.5 MHz. Therefore, the divider needs to be 102 and not 62. This patch changes the define to match the new divider value and uses this new define at the appropriate place. Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz. Change-Id: Idf498c3547530dfa395f54488ef244e787062e34 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* mb/siemens/mc_ehl1: Disable L1 prefetcherWerner Zeh2022-10-251-0/+3
| | | | | | | | | | | | | | | The highly real time driven application executed on mc_ehl1 has shown that the L1 prefetcher on Elkhart Lake is too aggressive which in the end leads to an increased number of cache misses. Disabling the L1 prefetcher boosts up the performance (in some cases by more than 10 %) in this specific use case. Change-Id: Id09a7f8f812707cd05bd5e3b530e5c3ad8067b16 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68668 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
* soc/intel/eklhartlake: Provide an option to disable the L1 prefetcherWerner Zeh2022-10-252-0/+11
| | | | | | | | | | | | | | | | Depending on the real workload that is executed on the system the L1 prefetcher might be too aggressive and will populate the L1 cache ahead with data that is not really needed. In the end, this will result in a higher cache miss rate thus slowing down the real application. This patch provides a devicetree option to disable the L1 prefetcher if needed. This can be requested on mainboard level if needed. Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: replace SPDX identifiers to GPL-2.0-only OR MITRex-BC Chen2022-10-251-1/+1
| | | | | | | | | | | | For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so replace "GPL-2.0-only" with "GPL-2.0-only OR MIT". Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Configure firmware display for eDP panelBo-Chen Chen2022-10-256-0/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add eDP panel power-on sequences and initialize the display in the ramstage. eDP panel in MT8188 EVB: "IVO R140NWF5 RH". Panel spec name: R140NWF5 RH Product Specification Firmware display eDP panel logs: configure_display: Starting display initialization SINK DPCD version: 0x11 SINK SUPPORT SSC! Extracted contents: header: 00 ff ff ff ff ff ff 00 serial number: 26 cf 7d 05 00 00 00 00 00 1e version: 01 04 basic params: 95 1f 11 78 0a chroma info: 76 90 94 55 54 90 27 21 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a extensions: 00 checksum: fb Manufacturer: IVO Model 57d Serial Number 0 Made week 0 of 2020 EDID version: 1.4 BUG=b:244208960 TEST=see firmware display using eDP panel in MT8188 EVB. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I67e0699c976c6f85e69d40d77154420c983b715e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68490 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Update mtcmos settings for display and audioBo-Chen Chen2022-10-255-21/+34
| | | | | | | | | | | | | | | | | | | - For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are required. - For audio, it requires powering on adsp_ao_pwr_con, adsp_infra_pwr_con and audio_pwr_con. - Add new power domain data `ext_buck_iso_bits` for buck isolation control. BUG=b:244208960 TEST=access display registers successfully. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Add eDP support for firmware displayBo-Chen Chen2022-10-253-0/+17
| | | | | | | | | | | | | | MT8188 supports eDP as internal display interface. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6441a36557b097e041bc081b907eb60b56c9fbe6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* soc/mediatek/mt8188: Add ddp driver to support eDP outputNathan Lu2022-10-254-0/+461
| | | | | | | | | | | | | | | | | Add DDP (display data path) driver that supports overlay, read/write DMA, etc. The output goes to display interface DP_INTF0 directly. Add ddp gclast and output_clamp settings to MT8188 to support multi-layer display. BUG=b:244208960 TEST=emerge-geralt coreboot. Signed-off-by: Nathan Lu <nathan.lu@mediatek.com> Change-Id: Icc0a878c609818fedd298c141bb39469fd2f6388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68487 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Rename SPM registerBo-Chen Chen2022-10-253-4/+4
| | | | | | | | | | | | | | | | | The SPM register at offset 0x0 is often named as poweron_config_set in previous MediaTek SoCs. To use common driver, we rename it from poweron_config_en to poweron_config_set. BUG=none TEST=emerge-geralt coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Add support for input 1P mode of dp_intfRex-BC Chen2022-10-254-32/+48
| | | | | | | | | | | | | | | | | MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct member `input_mode` is added to `struct mtk_dpintf` for differentiation. We also move SoC-specific data `dpintf_data` to soc folder. BUG=b:244208960 TEST=emerge-cherry coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
* soc/mediatek: Move DP drivers to commonBo-Chen Chen2022-10-258-13/+14
| | | | | | | | | | | | | | | DP drivers can be shared for both MT8195 and MT8188, so move them to common folder. BUG=b:244208960 TEST=emerge-cherry coreboot. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/clevo/tgl-u: Avoid indirect includesElyes Haouas2022-10-242-0/+2
| | | | | | | | Change-Id: I51ab987420e592ac2f841c2d7761c0adcc43124e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/google/kahlee: always detect ELAN touchpadFelix Held2022-10-245-32/+1
| | | | | | | | | | | | Always detecting the presence of the ELAN touchpad doesn't affect the functionality, but allows dropping the override for all variants that have multiple touchpad options. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id5d14eedd5d95dd0990ae56775daed9284c03717 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68672 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* mb/google/kahlee: use override devicetrees for variantsFelix Held2022-10-2410-576/+204
| | | | | | | | | | | This helps with deduplicating the identical parts of the variants' devicetrees. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie050c4624327b904e8cb0959b40421339e43f825 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* arch/x86: x86_64 implies SSE2 supportPatrick Rudolph2022-10-241-0/+5
| | | | | | | | | | | | | | | | | | | | | | Enable SSE2 (and SSE) when compiling for x86_64. Compilers often assume SSE2 is present and enabled when targeting x86_64. This fixes: - lzma decompression code is compiled with the -Ofast flag - 'everything' when compiling with clang. This mostly affects qemu targets, which did not have this flag selected yet. TESTED on qemu. Change-Id: I3cdc584c97016e15513df663a54a7bdb549a73e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44869 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
* mb/Kconfig: Add a prompt string for MAINBOARD_PART_NUMBERSam McNally2022-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | For some nissa variants, there are build configurations that need to use different blobs, but otherwise are identical. Currently, they use the same choice of board config and configure blob paths appropriately. This avoids duplication within the Kconfig file, but the resulting firmware images can be difficult to distinguish, since they report the same FRID. Add a prompt string for MAINBOARD_PART_NUMBER so it can be overridden and round-tripped through make oldconfig, allowing customisation of the reported FRID and other MAINBOARD_PART_NUMBER-derived values with minimal overhead. BUG=b:253966060 BRANCH=None TEST=CL:3960290 MAINBOARD_PART_NUMBER configs apply successfully Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I3497d7fa1c04c8fa2592025c771d9dbc65632e6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* soc/amd/mendocino: Add STB Spill-to-DRAM enumMartin Roth2022-10-231-0/+1
| | | | | | | | | | | | This is the enum value to initialize the Smart Trace Buffer's Spill-to-DRAM feature. More information on how this is used is available in the STB Linux kernel driver. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
* soc/amd/morgana/mca: Update for morganaFred Reitberger2022-10-221-8/+53
| | | | | | | | | | Update the MCA bank names for morgana per PPR #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/brask/var/kuldax: Revise PsysPL2 to 150W for Pentium CPUDavid Wu2022-10-222-1/+24
| | | | | | | | | | | | | | Pentium CPU will use 150W adaptor, this change revises PsysPL2 to 150W based on fw_config. BUG=b:253542746 TEST=Check CPU PsysPL2=150W in AP log with Pentium CPU. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I63b2a9d79454b20b60ba1317a8eebb3c10eff9d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/brya: Enable SaGv for brask variantsDerek Huang2022-10-224-0/+6
| | | | | | | | | | | | | | | SaGv is enabled for all brya variants, so it should be harmless to enable it for brask variants to save some power. BUG=254374912 TEST=Build and boot to Chrome OS Signed-off-by: Derek Huang <derekhuang@google.com> Change-Id: Ib5d1e39b3f901606e2f1449e4ed40d53696562ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/68646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
* mb/google/skyrim/var/baseboard: Update gpio setting for touchscreen IRQFrank Wu2022-10-221-1/+1
| | | | | | | | | | | | | | | | The touchscreen IRQ has been configured as LEVEL_LOW in skyrim projects. Therefore, update the gpio.c to be consistent with the configuration. BUG=b:253506651, b:251367588 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iccfe5b01f10899c43151762e4730a05990afa602 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
* payloads/edk2: Disable the CPU Timer Lib unless supportedSean Rhodes2022-10-2210-0/+10
| | | | | | | | | | | | | | | | | | For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp Counter Frequence. For CPUs that do not support this instruction, EDK2 must include a different library which is the reason why this must be configured at build time. If this is enabled, and the CPU doesn't support 0x15, it will fail to boot. If is not enabled, and the CPU does support 0x15, it will still boot but without support for the leaf. Consequently, disabled it by default. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
* soc/intel/systemagent: Rewrite using new resource APIArthur Heymans2022-10-221-14/+5
| | | | | | | | | | | | | Working with resources in KB is tedious and the base_k / size_k variable naming was simply wrong in one case. Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-30 18:34:04 +0000