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* sb/intel/bd82x6x/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-5/+5
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I4e219bea8df64db1d49beb8534f0f37fee0df5b6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/intel/i82801ix/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-4/+4
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: Ifffd21a663739f72a5584e26b79b0627dd532d9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/intel/i82801jx/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-4/+4
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I3aebd29bba285229979b79867c881018f61e2060 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc/intel/common/sata: Add APL and GLK SATA PCI IDsSean Rhodes2022-07-291-0/+2
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0ae8c6624b79ce6c269244bd1435900d4d7f997a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/nissa/var/joxer: Correct i2c address for touchscreenMark Hsieh2022-07-281-1/+1
| | | | | | | | | | | | | set i2c address to 0x14 for Goodix touchscreen BUG=b:239180430 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFFTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | When the dGPU is entering GCOFF, the link should first be placed into L2/L3 as appropriate for the design, then when exiting, the link should be placed back into L0. This patch fixes that oversight. BUG=b:239719056 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Modify GPP_A8 programmingTim Wawrzynczak2022-07-281-1/+1
| | | | | | | | | | | | | | | | The EEs noticed this pin was misbehaving; it was accidentally set to a low output, but should be open-drain (NC). This patch fixes that. BUG=b:237837108 TEST=verified by EEs Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Modify GPP_F14 programmingTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | For some yet unknown reason, when this GPIO is locked, there is an interrupt storm for IRQ #9 apparently caused by GPE 0x66. GPP_F14 is set to GPE 0x64 on the ADL platform, so this doesn't quite make sense. This patch removes the lock and fixes this IRQ storm, but the root cause is not identified yet. BUG=b:236997604 TEST=`grep ' 9:' /proc/interrupts` shows a reasonable value now Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3d1c66fac80a173798ae33e48b1776d9f4fb5eaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Optimize dGPU GCOFF entryTim Wawrzynczak2022-07-282-4/+1
| | | | | | | | | | | | | | | | | | | | | After staring at lots of scope shots, the EE has determined that a few modifications to the GCOFF sequence can be made: - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion - Remove delay after ramping down FBVDD This patch implements these minor changes. BUG=b:240199017 TEST=verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Update ASPM settings for dGPUTim Wawrzynczak2022-07-282-5/+1
| | | | | | | | | | | | | | | | | | After some debugging, it has been determined that the ASPM L0s substate is functional, but there is still some problem with ASPM L1 substates, so this patch updates ASPM status for the dGPU from disabled to L0s only. BUG=b:240390998 TEST=tested with nvidia tools Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Add support for more CPU PCIe RP UPDsTim Wawrzynczak2022-07-281-0/+6
| | | | | | | | | | | | | | | | | | | There are 3 more CPU PCIe RP UPDs that are the current code is not setting, and some boards may want to set these, so this patch adds support to set these UPDs. The default values for any existing boards using these UPDs should not change with this patch. The UPDs are: - CpuPcieRpDetectTimeoutMs - CpuPcieRpAspm - CpuPcieRpSlotImplemented Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id48019f984e8e53ff3ce0c3c23e02dab65112c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66197 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/anahera{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-286-2/+6
| | | | | | | | | | | | | | Generate SPD id for hynix H54G68CYRBX248 BUG=b:239899929 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I96babe340678ca9b82b06d3193b93a7676f23fef Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-286-2/+6
| | | | | | | | | | | | | | Generate SPD id for Hynix H54G68CYRBX248 BUG=b:239888704 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/ghost: Correct CNVi pinsEric Lai2022-07-281-11/+11
| | | | | | | | | | | | | | | | GPP_F0 to GPP_F4 is for CNVi and should be NF1. GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=CNVi wifi can get probed in kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* soc/intel/alderlake: Enable LPIT supportJeremy Soller2022-07-282-0/+3
| | | | | | | | | | | Add SLP_S0 residency register and enable LPIT support. Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Set Energy Perf Bias appropriate default valueJeremy Compostella2022-07-281-2/+3
| | | | | | | | | | | | | | | | | | | | | | | The current "normal" EPB (six) setting resulted in the desired out of box power and performance for several CPU generations. However, a power and performance analysis on Alder Lake and Raptor Lake CPUs demonstrates that this value results in undesirable higher uncore power and that seven is a more appropriate value. Note: the Linux kernel "4ecc933b x86: intel_epb: Allow model specific normal EPB value" patch sets the EPB to 7 for Alder Lake. BRANCH=firmware-brya-14505.B BUG=b:239853069 TEST=verify that EPB is set by coreboot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I5784656903d4c58bedc5063ee3ef310a99711050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66059 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Enable Energy/Performance Bias controlJeremy Compostella2022-07-281-1/+2
| | | | | | | | | | | | | | | | | | | | | According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL must be set to be able to set the Energy/Performance Bias using MSR IA32_ENERGY_PERF_BIAS. Note that since this bit was not set until this patch, the `set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in `soc_core_init()` was systematically failing. BRANCH=firmware-brya-14505.B BUG=b:239853069 TEST=verify that EPB is set by coreboot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* google/trogdor: Add new variant Pazquel360Yunlong Jia2022-07-282-0/+5
| | | | | | | | | | | | | | | This patch adds a new variant called Pazquel360 \ that is identical to Pazquel for now. BUG=b:239987191 TEST=make Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I0a9ca4a59fb44256d0d8fcdbdf2a7db533c84412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Bob Moragues <moragues@google.com>
* commonlib: compiler.h: Use non-concise comment stylePaul Menzel2022-07-281-15/+23
| | | | | | | | | | | The concise multi-line comment style is for inside function bodies to save space. Outside of it, use non-concise style. Change-Id: I34d9ec6984b598a37c438fa3c395b5478207e31d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/rex: Initial setup for ramstage/early gpio configTarun Tuli2022-07-281-19/+417
| | | | | | | | | | | | | | | This adds the initial gpio configuration for the rex initial variant. BUG=b:238165977 TEST=Boots and no errors on simics Change-Id: I55ab31c7943e22df9cec8db4a9f0c3ab6f065ae1 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65952 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/meteorlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik2022-07-281-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO reset types in Meteor Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - Global Reset for GPP - (Value 11) Also, dropped the need for having dedicated reset type for GPIO community 3. As per the MTL EDS, all GPIO communities have the same reset type. BUG=b:213293047 TEST=Able to build and boot Google/Rex without below error msg. [ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id7ea16d89b6f01b00a7b7c52945f6e01e8db6cbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Will Kim <norwayforest92@gmail.com>
* soc/intel/gpio: Add new macro for GPP PAD reset type as `Global Reset`Subrata Banik2022-07-281-0/+5
| | | | | | | | | | | | | | | This patch introduces a new macro for GPP PAD reset type as `Global Reset` as documented in Alder Lake EDS doc 630603. BUG=b:213293047 TEST=Able to build Google/Kano with this change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I39428911babc393dd10750801522a00d0b26d3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/sabrina: Disable CCP DMA and HW MODEXPKarthikeyan Ramasubramanian2022-07-272-7/+2
| | | | | | | | | | | | | | | Enabling them causes firmware keyblock/preamble and/or body verification failure. Hence disabling them to use software based verification. Re-enable them once the issue is root-caused. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e259ae5d790977d08afcb0a77f8d4f38c85f39e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66134 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/sabrina: Do not pass SHA operation modeKarthikeyan Ramasubramanian2022-07-272-2/+1
| | | | | | | | | | | | | Currently only SHA_GENERIC is used and does not need to be passed. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP and x86 verstage. Change-Id: Id705b1361fffaf940c51515e7f77d7fb0677fc4a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/brya/crota: Remove MAC address passthru supportFranklin Lin2022-07-272-54/+0
| | | | | | | | | | | | | | | ChromeOS connection manager (shill) already has support for dock MAC address passthrough, therefore remove the code to pass a dock's MAC address in ACPI. BUG=b:235045188 TEST=build coreboot Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com> Change-Id: I78320a7c6b0fd5392e24b63bff234229a3f4b9bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66040 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/ghost: Update memory DQ mapEric Lai2022-07-271-21/+21
| | | | | | | | | | | | | | | | | | Follow latest schematic 6/27 to update the DQ map. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8d0de04a001cab53a245185707ebc9da7a501ec4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66122 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* drivers/wifi/generic: Revert changes to generate missing SSDT for PCIeReka Norman2022-07-272-28/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | wifi This reverts commit 5e6fd360de7fe92f1e8b1b3eb20241809e2a6aff. On nereid, the SSDT entry for the PCIe wifi device is missing, causing wake-on-WLAN not to work since the _PRW is missing. It seems like when commit 5e6fd360de changed the SSDT generation logic for CNVi and PCIe wifi, it broke the PCIe case. `wifi_pcie_ops` are never assigned to any device, so `parent && parent->ops == &wifi_pcie_ops` always returns false, and the `wifi_cnvi_ops` are used even for PCIe devices. Undo the changes in that CL. This allows both the CNVi and PCIe cases to work. That CL was meant to fix an issue with the CNVi _PRW containing garbage, but I can't reproduce this when the change is undone. It was also meant to fix the following error on CNVi devices, but I don't see any errors with this change: [ERROR] NONE missing set_resources BUB=b:233325709 TEST=On both nivviks (CNVi) and nereid (PCIe), check that the SSDT contains the correct wifi device entries (below), including a _PRW containing the correct GPE, and check that wake-on-WLAN works. nivviks: ``` Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { <snip> } } ``` nereid: ``` Device (\_SB.PCI0.RP01.WF00) { Name (_UID, 0x923ACF1C) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x0000000000000000) // _ADR: Address } Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { <snip> } } ``` Fixes: 5e6fd360de ("drivers/wifi/generic: Fix properties in generic-under-PCI device case") Change-Id: I100c5ee3842997c50444e5ce68d583834ed3a8ad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66063 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/craask: Add DPTF passive and critical policiesTyler Wang2022-07-271-0/+61
| | | | | | | | | | | | | | Add critical, passive policy, and pl values from thermal team. BUG=b:239495499 TEST=Build and test on MB, system can boot to OS. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I8beb3b57ff56c6fe413bb0e3dd43d693aee08e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66125 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/meteorlake: Use coreboot native event handler for FSP-SSrinidhi N Kaushik2022-07-271-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beginning FSP 2.2 specifications Fsps Config Upd "FspEventHandler" was moved to Fsps Arch Upd. Hence we were not seeing Fsps Debug log was not using coreboot debug library. This change assigns Fspd Arch Upd FspEventHandler with coreboot ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. Before: Dumping FSPS_UPD - Size: 0x00001510 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 0x00 0x00 0x00000010: 0x00 With the fix: [SPEW ] Dumping FSPS_UPD - Size: 0x00001528 [SPEW ] 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 [SPEW ] 0x00000010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 [SPEW ] 0x00000020: 0x01 0x00 0x00 0x00 0x20 0x00 0x00 0x00 0xAA [SPEW ] 0x00000030: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 [SPEW ] 0x00000040: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 BUG=b:237263080 TEST=Able to build and boot MTL RVP, verified the FSP-S debug log is using coreboot debug library. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie63258f6427b3da7927a866bc3767f548b16e3e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/nissa/var/pujjo: Enable PCIe port 4 for WLANLeo Chou2022-07-271-0/+20
| | | | | | | | | | | | | Pujjo support WLAN device, enable PCIe port 4 for WLAN device BUG=b:239899932 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Skip PCIe ops for eMMC SKUsYu-Ping Wu2022-07-271-2/+7
| | | | | | | | | | | | | | | | | To avoid unnecessary PCIe early initialization for non-NVMe devices (which would take about 150ms on dojo), skip setting PCIe ops when initializing mt8195 SoC. BUG=b:238850212 TEST=emerge-cherry coreboot TEST=Dojo SKU1 (eMMC) boot time <= 1s BRANCH=cherry Change-Id: I8945890ba422c0c4eb42683935220b7afbb80dfd Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/cherry: Introduce mainboard_needs_pcie_initYu-Ping Wu2022-07-272-0/+31
| | | | | | | | | | | | | | | | | | Implement mainboard_needs_pcie_init() for cherry as a callback for mt8195 SoC to determine whether to initialize PCIe. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:238850212 TEST=emerge-cherry coreboot BRANCH=cherry Change-Id: I2ed0ceeb37d2924ca16485fb2d130959a7eff102 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/brask/var/kuldax: correct Type-A USB3 port0/1 tx_de_empDavid Wu2022-07-261-0/+17
| | | | | | | | | | | | | | | | 1. Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. 2. Disable unused USB port. BUG=b:238230292 TEST=build FW and check Type-A USB3 port0/port1 RX pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I8356ca30a965e5774a1556c5cb81e1586c55496c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/nissa/var/joxer: Configure descriptor for eMMC or UFSReka Norman2022-07-263-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | Joxer will have both eMMC and UFS SKUs, which require different settings in the descriptor. So update the descriptor at run-time based on fw_config. By default, the descriptor is configured for UFS. This configuration still boots fine on eMMC SKUs, it just might cause problems with S0ix. This is a temporary workaround. It will be removed once we've implemented a proper solution for configuring the descriptor differently for different SKUs. BUG=b:238234376 TEST=Make an identical change for nivviks. On both nivviks (eMMC) and nirwen (UFS), check that it boots and that the logs show the descriptor being configured as expected. Change-Id: I14232eb773936f2ecd183687208d332136935601 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/mediatek/mt8188: Initialize SSPMRex-BC Chen2022-07-264-1/+13
| | | | | | | | | | | | | | | | | | | | | SSPM is "Secure System Power Manager" that provides power control in secure domain. The initialization flow is to load SSPM firmware to its SRAM space and then enable. It takes 21 ms to load sspm.bin. coreboot logs: CBFS: Found 'sspm.bin' @0x21680 size 0xa815 in mcache @0xffffeac4 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137348 bytes) TEST=we can see the sspm logs. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ib6443b64734048c1d71eeac650f36d7c4ac709cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/66067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek/mt8188: Initialize MCUPMRex-BC Chen2022-07-264-0/+24
| | | | | | | | | | | | | | | | | | | Load MCUPM firmware and boot up MCUPM in ramstage. It takes 41 ms to load mcupm.bin. coreboot logs: CBFS: Found 'mcupm.bin' @0x12580 size 0xf0c6 in mcache @0xffffead0 mtk_init_mcu: Loaded (and reset) mcupm.bin in 41 msecs (122184 bytes) TEST=we can see the mcupm logs after reset releases. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Id1e62d9d6ede1c453e03eeda0d9b16fafa9e2372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/rex: Set GPIO Tier-1 GPEs in devicetreeKapil Porwal2022-07-251-0/+5
| | | | | | | | | | | | | | | | | Set GPE route as GPE0_DW0 -> GPP_A GPE0_DW1 -> GPP_E GPE0_DW2 -> GPP_F BUG=b:224325352 TEST=Verified in emulator that there is no regression Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5e3e09cfc06d2556ea32cca23b3dae114a510498 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* Revert "soc/intel/meteorlake: Align TCSS functions through SBI"Subrata Banik2022-07-251-2/+2
| | | | | | | | | | | | | | | | | | | | This reverts commit b57d172fbb5265d632c031532fcc2aec156e065a. Reason for revert: Results into hard hang with serial debug msg as below: `[EMERG] Unable to unhide the P2SB device!` Intel team is working towards to fix this issue. BUG=b:239806774 TEST=Able to boot the Intel/MTLRVP with this revert. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic6be37c000afdf4f0c6c22497c233aa0bbc49d48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65500 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/rex: Override LP5 CCC configSubrata Banik2022-07-251-1/+3
| | | | | | | | | | | | | | | | This patch overrides `Lp5CccConfig` UPD as per the CCC mapping data captured from the Rex schematics dated 07/16. BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia1d9e3665cff74a803e730c76f62773996efb3dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66049 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/meteorlake: Choose PCR write to lock GPIO PADSubrata Banik2022-07-251-0/+1
| | | | | | | | | | | | | | Set the SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR config on Meteor Lake to instruct Pad Configuration Lock. BUG=b:211573253, b:211950520, b:213596994 TEST=Able to perform GPIO lock programming without error on MTLRVP. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icd123adb02716149fa51c9e4c987c281f9de2f43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* mb/starlabs/lite: Add support for VBOOTSean Rhodes2022-07-254-0/+44
| | | | | | | | | | | Add the required files to support VBOOT for when it is enabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I083107b21c23f42193fc88aa174ec22850f45bc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65705 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* arch/x86: Fix MAX_CPUS check proper for late X2APIC configSubrata Banik2022-07-251-1/+1
| | | | | | | | | | | | | | | | The X2APIC_LATE_WORKAROUND kconfig allows bringing APs in XAPIC mode initially hence, it won't work if LAPIC ID is > 0xff. This patch ensures the MAX_CPUS logic is appropriate while selecting X2APIC_LATE_WORKAROUND kconfig from SoC. BUG=b:219061518, b:219053812 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I466e6cc568024a9dea80af21e0ebf3572e74a1f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* mb/google/nissa/var/pujjo: Add new supported memory partLeo Chou2022-07-253-0/+3
| | | | | | | | | | | | | | | | | Add pujjo new supported memory parts in mem_parts_used.txt. Generate SPD id for this part. Micron MT62F1G32D4DR-031 WT:B BUG=b:239776504 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I95eb194ecbd5d39f66eb566132e75af056899325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66039 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/intel/gpio: Update GPIO Lock configuration recommendationSubrata Banik2022-07-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the GPIO lock configuration recommendation kconfig string to ensure the SoC user can select the correct config as applicable for the SoC. Note: From MTL onwards GPIO lock config can be performed using PCR write (MMIO write) and the GPIO team has confirmed this. BUG=b:213596994 TEST=Able to fix below GPIO lock config error msg on MTL with `SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_PCR` kconfig enabled. [INFO ] Locking pad configuration using SBI [INFO ] gpio_pad_config_lock_using_sbi: Locking pad 73 configuration [ERROR] SBI Failure: Transaction Status = 1 [ERROR] Failed to lock GPIO PAD, response = 1 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icab1e4849b8e08ee1c695c924599f1513774178f Reviewed-on: https://review.coreboot.org/c/coreboot/+/66113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/rex: Add memory configuration board strapsSubrata Banik2022-07-252-2/+15
| | | | | | | | | | | | | | | | This patch reads various memory configuration GPIOs to fill in below details: 1. variant_memory_sku() 2. variant_is_half_populated() BUG=b:224325352 TEST=Able to build Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I23bad8c78523cb56008e6d67e7776e57e42fbeb9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66041 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* soc/intel/meteorlake: Debug consent is set to 3 (USB3 DbC)Subrata Banik2022-07-251-1/+1
| | | | | | | | | | | | | | This patch ensures the debug consent value is matching with the inline comment. TEST=Able to build the Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Icf72eb2aa4064fd78f4f99570a4cf44e41932ec3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66008 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo: Integrate W541 into haswell mainboardFelix Singer2022-07-2420-321/+14
| | | | | | | | | | | Lots of code from lenovo/haswell can be reused for lenovo/w541. Thus, integrate it into lenovo/haswell and make it a variant. Change-Id: If99d842cff777fe27ff63baabc447e69b9d0333c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63514 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* mb/lenovo/haswell: Make INT15 support T440p specificFelix Singer2022-07-244-2/+2
| | | | | | | | | | | In preparation to CB:63514, make the INT15 support specific for the T440p variant since the W541 doesn't support it currently. Change-Id: I8dfcc061e1b8a831f75bf9a8035770cb678a85d4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66106 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/lenovo/haswell: Hook up variants MakefileFelix Singer2022-07-241-0/+2
| | | | | | | | Change-Id: I36091118d98f71dc4141aca4e45858a22d519a9b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* intel/common/block/ipu: Add MTL IPU device idWonkyu Kim2022-07-241-0/+1
| | | | | | | | | | TEST=Build mtlrvp and check IPU0 ACPI ojbect from ssdt Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib5c3d455d272af0e753c775a5fd3f19851b7937d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66056 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 08:08:38 +0000