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* mb/google/rex: Add LP5 RAM IDsTarun Tuli2022-07-293-0/+6
| | | | | | | | | | | | | | | | | | Create RAM IDs for: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D2DS-026 WT:B 1 (0001) MT62F2G32D4DS-026 WT:B 2 (0010) BUG=b:240289148 TEST=emerge-rex coreboot Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Ib24e07bca363984db3484aa500f7d6ea4817e517 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* soc/mediatek/mt8188: Add SPI supportLiya Li2022-07-293-1/+102
| | | | | | | | | | | | | | | | The gpios and the tick delay register are different between MT8188 and previous MediaTek SoCs, so we need to add this patch to support SPI. TEST=build pass BUG=b:236331724 Signed-off-by: Liya Li <ot_liya.li@mediatek.corp-partner.google.com> Change-Id: I6065b9d285dfd36c191f274f500fdb694920276e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66185 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Create GET_TICK_DLY_REG macro for SPI tick delay settingRex-BC Chen2022-07-296-8/+13
| | | | | | | | | | | | | | | MT8188 SPI tick delay setting is moved to `spi_cmd_reg` register which is different from previous SoCs, so we define a macro to get the designated register. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia30e94a8688c0e1c1d4b3d15206f28e5bd8c9bd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66184 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/geralt: Initialize RTC and clk_buf in romstageRex-BC Chen2022-07-291-0/+4
| | | | | | | | | | | | TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I869c0879d09e00cf66882adb728c9ccb6ac57e03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66183 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add clk_buf support in romstageSong Fan2022-07-291-0/+1
| | | | | | | | | | | | TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: Ic300b70a38ac204b098ca9ab15cf7045b66fd76d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66182 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add RTC supportSong Fan2022-07-292-0/+94
| | | | | | | | | | | | | | Add RTC header file for SoC-specific settings. Add RTC support in romstage. TEST=build pass. BUG=b:233720142 Signed-off-by: Song Fan <ot_song.fan@mediatek.corp-partner.google.com> Change-Id: I38115ce0c9a4e1c1b2b7c8e6d40f47e99f7f86b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66181 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek: Move common definitions from rtc.h to rtc_reg_common.hRex-BC Chen2022-07-295-528/+163
| | | | | | | | | | | | | | | Move the common definitions to rtc_reg_common.h, so we can reuse those definitions on MT8188. TEST=build pass BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: Ia1d916a88b7cb875b35ee5813b7b52d9e98f5009 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66180 Reviewed-by: Yidi Lin <yidilin@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8188: Add AUXADC supportHui Liu2022-07-293-0/+35
| | | | | | | | | | | TEST=get voltage as 340mV for channel 0 in MTK EVB. BUG=b:233720142 Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com> Change-Id: Idd1edcce6cb62fcf6991bb9342c409150989c5ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/66121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* soc/mediatek: Move struct mtk_auxadc_regs to auxadc_common.hRex-BC Chen2022-07-295-44/+11
| | | | | | | | | | | | | | The AUXADC register definitions are the same for all MediaTek SoCs, so we move struct mtk_auxadc_regs to auxadc_common.h. TEST=build pass. BUG=b:233720142 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Change-Id: I48978a93137a7de42f8ea2873be3130cb8f534f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* mb/google/rex: Enable CNVi BT CoreSubrata Banik2022-07-291-0/+3
| | | | | | | | | | This patch override `CnviBtCore` FSP UPD. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I90c9b360969aada0b0e031d62b48476fac5cee0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* mb/google/brya/var/ghost: Enable CS42L42 codecEric Lai2022-07-293-2/+21
| | | | | | | | | | | | | | | Add CS42L42 support in device tree. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=Check cs42l42 driver can probe successfully in kernel. cs42l42 i2c-10134242:00: Cirrus Logic CS42L42, Revision: B1 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I861f47c12f4cebb016a4cfbe225f97d34d55e233 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya/var/ghost: Update all I2C buses speed to fastEric Lai2022-07-291-23/+5
| | | | | | | | | | | | | | | Remove the parameter and set I2C bus speed to fast. Will fill the tuning value after real tuning. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Iba7fe4551959617ecfa49719c1124bf85d624c31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66220 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* mb/google/brya: Create gaelin variantRaymond Chung2022-07-295-0/+28
| | | | | | | | | | | | | | | | | | Create the gaelin variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:239514438 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GAELIN Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I7f1ff8690c7c57f8960e004d0490d5cede8667f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
* soc/intel/alderlake: Add missing TDP and Power Limits for ADL-SMichał Żygowski2022-07-292-1/+53
| | | | | | | | | | | | | Add TDP and Power Limit settings for ADL-S 8+8 150W, 4+0 and 2+0. The System Agent PCI IDs were not present in older 2.1 revision of DOC #619501. Now that the mapping of these IDs to SKUs is known, fill the missing TDPs and Power Limit settings based on DOC #626343. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I23dd8478e60bcc81a1048f2f6e6717dd281d1a69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/intel/alderlake: Set VccIn Aux Imon IccMax for ADL-S 4+0 and 2+0Michał Żygowski2022-07-291-0/+2
| | | | | | | | | | | | Add missing System Agent PCI IDs for ADL-S 4+0 and 2+0 to configure VccIn Aux Imon IccMax. They were not present in older 2.1 revision of DOC #619501. Based on DOC #619501 rev 2.6. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Idfd57ce9b63db5d5fcc9d4efb8aa27ed7cc6222d Reviewed-on: https://review.coreboot.org/c/coreboot/+/66052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* soc/intel/alderlake/vr_config.c: Add VR params for ADL-SMichał Żygowski2022-07-291-0/+60
| | | | | | | | | | Based on DOC #619501, #634885, #626343. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ib50db521e4d127a773f903b45d4bec5c5cc180d4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* intel/pmclib: Avoid PMC ABASE read of SLP_TYP and STATUS in ramstageHarsha B R2022-07-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch updates platform_is_resuming() API such that platform resume state is determined from the saved state (CBMEM) instead of checking PMC registers (PM1_STS & PM1_CNT) as they are getting cleared (before/early) ramstage. coreboot sends DISCONNECT IPC command which times out during resume (S3) if system has servoV4 connected on port0. The issue occurs only during the first cycle of resume (S3) test cycle after cold boot due to side effect of platform_is_resuming() API that is not determining the resume (S3) state correctly in ramstage. PM1_STS and PM1_CNT register gets cleared at the start of ramstage. platform_is_resuming() function was checks the cleared register value and fails the condition of resume (S3) resulting in sending DISCONNECT IPC command. Checking the platform resume state from the CBMEM saved state using acpe_get_sleep_type() function helps cross verify the system previous state at the later part of ramstage. localhost ~ # cbmem -c | grep ERROR [ERROR] EC returned error result code 3 [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:0 to initial state [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0x200a7 failed [ERROR] pmc_send_ipc_cmd failed [ERROR] Failed to setup port:1 to initial state [ERROR] GENERIC: 0.0 missing read_resources [ERROR] PMC IPC timeout after 1000 ms [ERROR] PMC IPC command 0xd0 failed [ERROR] PMC: Failed sending PCI Enumeration Done Command BUG=b:227289581 TEST=Verified system boots to OS and verified below tests on Redrix (ADL-P) and Nivviks (ADL-N) 1. coreboot doesn't send the DISCONNECT during S3 resume 2. suspend S3 passes with both suzyq and servoV4 connected 3. After S3 resume, system detects the pen drive with Superspeed 4. After system resumes from S3, hot-plug the pen drive, system detects the pen drive Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I353ab49073bc4b5288943e19a75efa04bd809227 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66126 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/dedede/var/drawcia: Enable weida touchscreenShon Wang2022-07-291-0/+14
| | | | | | | | | | | | | | | Add weida touchscreen support for drawcia. BRANCH=dedede TEST=Build and verify that touchscreen works on drawcia. Change-Id: Ic76f3529771c6eeeafef7ca50fc400065aac2211 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65471 Reviewed-by: Ivan Chen <yulunchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* sb/intel/bd82x6x/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-5/+5
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I4e219bea8df64db1d49beb8534f0f37fee0df5b6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/intel/i82801ix/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-4/+4
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: Ifffd21a663739f72a5584e26b79b0627dd532d9e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60667 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* sb/intel/i82801jx/acpi: Replace LEqual(a,b) with ASL 2.0 syntaxFelix Singer2022-07-292-4/+4
| | | | | | | | | | | Replace `LEqual(a, b)` with `a == b`. Change-Id: I3aebd29bba285229979b79867c881018f61e2060 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
* soc/intel/common/sata: Add APL and GLK SATA PCI IDsSean Rhodes2022-07-291-0/+2
| | | | | | | | Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0ae8c6624b79ce6c269244bd1435900d4d7f997a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* mb/google/nissa/var/joxer: Correct i2c address for touchscreenMark Hsieh2022-07-281-1/+1
| | | | | | | | | | | | | set i2c address to 0x14 for Goodix touchscreen BUG=b:239180430 TEST=USE="project_joxer emerge-nissa coreboot" Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I11a2d9c684bc511b3942f88f74a2495e796bc3c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
* mb/google/brya/acpi: Add L23 entry/exit sequences during dGPU GCOFFTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | When the dGPU is entering GCOFF, the link should first be placed into L2/L3 as appropriate for the design, then when exiting, the link should be placed back into L0. This patch fixes that oversight. BUG=b:239719056 TEST=build Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia3bdfe5641216675e06ebe82ffe58bf8c049b26b Reviewed-on: https://review.coreboot.org/c/coreboot/+/66200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Modify GPP_A8 programmingTim Wawrzynczak2022-07-281-1/+1
| | | | | | | | | | | | | | | | The EEs noticed this pin was misbehaving; it was accidentally set to a low output, but should be open-drain (NC). This patch fixes that. BUG=b:237837108 TEST=verified by EEs Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ie76a951320c49b9fbc1f23b96f04c9f86ad44d42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Modify GPP_F14 programmingTim Wawrzynczak2022-07-281-0/+2
| | | | | | | | | | | | | | | | | | For some yet unknown reason, when this GPIO is locked, there is an interrupt storm for IRQ #9 apparently caused by GPE 0x66. GPP_F14 is set to GPE 0x64 on the ADL platform, so this doesn't quite make sense. This patch removes the lock and fixes this IRQ storm, but the root cause is not identified yet. BUG=b:236997604 TEST=`grep ' 9:' /proc/interrupts` shows a reasonable value now Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I3d1c66fac80a173798ae33e48b1776d9f4fb5eaa Reviewed-on: https://review.coreboot.org/c/coreboot/+/66201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
* mb/google/brya/var/agah: Optimize dGPU GCOFF entryTim Wawrzynczak2022-07-282-4/+1
| | | | | | | | | | | | | | | | | | | | | After staring at lots of scope shots, the EE has determined that a few modifications to the GCOFF sequence can be made: - Remove delay between PERST# assertion and GPU_ALLRAILS_PG deassertion - Remove delay after ramping down FBVDD This patch implements these minor changes. BUG=b:240199017 TEST=verified by EE Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I7d492b3e65a231bc5f64fe9c3add60b5e72eb072 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/brya/var/agah: Update ASPM settings for dGPUTim Wawrzynczak2022-07-282-5/+1
| | | | | | | | | | | | | | | | | | After some debugging, it has been determined that the ASPM L0s substate is functional, but there is still some problem with ASPM L1 substates, so this patch updates ASPM status for the dGPU from disabled to L0s only. BUG=b:240390998 TEST=tested with nvidia tools Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I584bdbf26eda20246034263446492bf4daf5f3b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
* soc/intel/alderlake: Add support for more CPU PCIe RP UPDsTim Wawrzynczak2022-07-281-0/+6
| | | | | | | | | | | | | | | | | | | There are 3 more CPU PCIe RP UPDs that are the current code is not setting, and some boards may want to set these, so this patch adds support to set these UPDs. The default values for any existing boards using these UPDs should not change with this patch. The UPDs are: - CpuPcieRpDetectTimeoutMs - CpuPcieRpAspm - CpuPcieRpSlotImplemented Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id48019f984e8e53ff3ce0c3c23e02dab65112c99 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66197 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/anahera{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-286-2/+6
| | | | | | | | | | | | | | Generate SPD id for hynix H54G68CYRBX248 BUG=b:239899929 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I96babe340678ca9b82b06d3193b93a7676f23fef Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/redrix{4es}: Add H54G68CYRBX248 supportWisley Chen2022-07-286-2/+6
| | | | | | | | | | | | | | Generate SPD id for Hynix H54G68CYRBX248 BUG=b:239888704 BRANCH=firmware-brya-14505.B TEST=run part_id_gen to generate SPD id Change-Id: I9412b988bcdb0c744e016f3add6dacda8185d6db Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* mb/google/brya/var/ghost: Correct CNVi pinsEric Lai2022-07-281-11/+11
| | | | | | | | | | | | | | | | GPP_F0 to GPP_F4 is for CNVi and should be NF1. GPP_F5 is for CNVi CLK_REQ, and should be NF3 CRF_XTAL_CLKREQ. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=CNVi wifi can get probed in kernel. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ice3fde3a457f6f5c058c0a7d3ca2e63775bda96c Reviewed-on: https://review.coreboot.org/c/coreboot/+/66175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* soc/intel/alderlake: Enable LPIT supportJeremy Soller2022-07-282-0/+3
| | | | | | | | | | | Add SLP_S0 residency register and enable LPIT support. Change-Id: I45e1fc9df3e782cdaac810af3189c5797b1fe413 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* soc/intel/alderlake: Set Energy Perf Bias appropriate default valueJeremy Compostella2022-07-281-2/+3
| | | | | | | | | | | | | | | | | | | | | | | The current "normal" EPB (six) setting resulted in the desired out of box power and performance for several CPU generations. However, a power and performance analysis on Alder Lake and Raptor Lake CPUs demonstrates that this value results in undesirable higher uncore power and that seven is a more appropriate value. Note: the Linux kernel "4ecc933b x86: intel_epb: Allow model specific normal EPB value" patch sets the EPB to 7 for Alder Lake. BRANCH=firmware-brya-14505.B BUG=b:239853069 TEST=verify that EPB is set by coreboot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: I5784656903d4c58bedc5063ee3ef310a99711050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66059 Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/intel/alderlake: Enable Energy/Performance Bias controlJeremy Compostella2022-07-281-1/+2
| | | | | | | | | | | | | | | | | | | | | According to document 619503 ADL EDS Vol2, bit 18 of MSR_POWER_CTL must be set to be able to set the Energy/Performance Bias using MSR IA32_ENERGY_PERF_BIAS. Note that since this bit was not set until this patch, the `set_energy_perf_bias(ENERGY_POLICY_NORMAL);' call in `soc_core_init()` was systematically failing. BRANCH=firmware-brya-14505.B BUG=b:239853069 TEST=verify that EPB is set by coreboot Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ic24abdd7f63f4707b8996da4755a26be148efe4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/66058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* google/trogdor: Add new variant Pazquel360Yunlong Jia2022-07-282-0/+5
| | | | | | | | | | | | | | | This patch adds a new variant called Pazquel360 \ that is identical to Pazquel for now. BUG=b:239987191 TEST=make Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I0a9ca4a59fb44256d0d8fcdbdf2a7db533c84412 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Bob Moragues <moragues@google.com>
* commonlib: compiler.h: Use non-concise comment stylePaul Menzel2022-07-281-15/+23
| | | | | | | | | | | The concise multi-line comment style is for inside function bodies to save space. Outside of it, use non-concise style. Change-Id: I34d9ec6984b598a37c438fa3c395b5478207e31d Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* mb/google/rex: Initial setup for ramstage/early gpio configTarun Tuli2022-07-281-19/+417
| | | | | | | | | | | | | | | This adds the initial gpio configuration for the rex initial variant. BUG=b:238165977 TEST=Boots and no errors on simics Change-Id: I55ab31c7943e22df9cec8db4a9f0c3ab6f065ae1 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65952 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/intel/meteorlake: Fix GPIO reset mapping as per GPIO BWGSubrata Banik2022-07-281-8/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the documentation discrepancy of GPIO reset type between PCH EDS and GPIO BWG. As per GPIO BWG, there are four GPIO reset types in Meteor Lake as below: - Power Good - (Value 00) - Deep - (Value 01) - Host Reset/PLTRST - (Value 10) - Global Reset for GPP - (Value 11) Also, dropped the need for having dedicated reset type for GPIO community 3. As per the MTL EDS, all GPIO communities have the same reset type. BUG=b:213293047 TEST=Able to build and boot Google/Rex without below error msg. [ERROR] gpio_pad_reset_config_override: Logical to Chipset mapping not found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id7ea16d89b6f01b00a7b7c52945f6e01e8db6cbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/66155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Will Kim <norwayforest92@gmail.com>
* soc/intel/gpio: Add new macro for GPP PAD reset type as `Global Reset`Subrata Banik2022-07-281-0/+5
| | | | | | | | | | | | | | | This patch introduces a new macro for GPP PAD reset type as `Global Reset` as documented in Alder Lake EDS doc 630603. BUG=b:213293047 TEST=Able to build Google/Kano with this change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I39428911babc393dd10750801522a00d0b26d3e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
* soc/amd/sabrina: Disable CCP DMA and HW MODEXPKarthikeyan Ramasubramanian2022-07-272-7/+2
| | | | | | | | | | | | | | | Enabling them causes firmware keyblock/preamble and/or body verification failure. Hence disabling them to use software based verification. Re-enable them once the issue is root-caused. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I7e259ae5d790977d08afcb0a77f8d4f38c85f39e Reviewed-on: https://review.coreboot.org/c/coreboot/+/66134 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/amd/sabrina: Do not pass SHA operation modeKarthikeyan Ramasubramanian2022-07-272-2/+1
| | | | | | | | | | | | | Currently only SHA_GENERIC is used and does not need to be passed. BUG=b:217414563 TEST=Build and boot to OS in Skyrim with PSP and x86 verstage. Change-Id: Id705b1361fffaf940c51515e7f77d7fb0677fc4a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* mb/google/brya/crota: Remove MAC address passthru supportFranklin Lin2022-07-272-54/+0
| | | | | | | | | | | | | | | ChromeOS connection manager (shill) already has support for dock MAC address passthrough, therefore remove the code to pass a dock's MAC address in ACPI. BUG=b:235045188 TEST=build coreboot Signed-off-by: Franklin Lin <franklin_lin@wistron.corp-partner.google.com> Change-Id: I78320a7c6b0fd5392e24b63bff234229a3f4b9bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/66040 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/brya/var/ghost: Update memory DQ mapEric Lai2022-07-271-21/+21
| | | | | | | | | | | | | | | | | | Follow latest schematic 6/27 to update the DQ map. BUG=b:240006200 BRANCH=firmware-brya-14505.B TEST=build passed. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I8d0de04a001cab53a245185707ebc9da7a501ec4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66122 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* drivers/wifi/generic: Revert changes to generate missing SSDT for PCIeReka Norman2022-07-272-28/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | wifi This reverts commit 5e6fd360de7fe92f1e8b1b3eb20241809e2a6aff. On nereid, the SSDT entry for the PCIe wifi device is missing, causing wake-on-WLAN not to work since the _PRW is missing. It seems like when commit 5e6fd360de changed the SSDT generation logic for CNVi and PCIe wifi, it broke the PCIe case. `wifi_pcie_ops` are never assigned to any device, so `parent && parent->ops == &wifi_pcie_ops` always returns false, and the `wifi_cnvi_ops` are used even for PCIe devices. Undo the changes in that CL. This allows both the CNVi and PCIe cases to work. That CL was meant to fix an issue with the CNVi _PRW containing garbage, but I can't reproduce this when the change is undone. It was also meant to fix the following error on CNVi devices, but I don't see any errors with this change: [ERROR] NONE missing set_resources BUB=b:233325709 TEST=On both nivviks (CNVi) and nereid (PCIe), check that the SSDT contains the correct wifi device entries (below), including a _PRW containing the correct GPE, and check that wake-on-WLAN works. nivviks: ``` Scope (\_SB.PCI0.CNVW) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x6D, 0x03 }) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { <snip> } } ``` nereid: ``` Device (\_SB.PCI0.RP01.WF00) { Name (_UID, 0x923ACF1C) // _UID: Unique ID Name (_DDN, "WIFI Device") // _DDN: DOS Device Name Name (_ADR, 0x0000000000000000) // _ADR: Address } Scope (\_SB.PCI0.RP01.WF00) { Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake { 0x23, 0x03 }) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { <snip> } } ``` Fixes: 5e6fd360de ("drivers/wifi/generic: Fix properties in generic-under-PCI device case") Change-Id: I100c5ee3842997c50444e5ce68d583834ed3a8ad Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66063 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* mb/google/nissa/var/craask: Add DPTF passive and critical policiesTyler Wang2022-07-271-0/+61
| | | | | | | | | | | | | | Add critical, passive policy, and pl values from thermal team. BUG=b:239495499 TEST=Build and test on MB, system can boot to OS. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I8beb3b57ff56c6fe413bb0e3dd43d693aee08e36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66125 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* soc/intel/meteorlake: Use coreboot native event handler for FSP-SSrinidhi N Kaushik2022-07-271-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Beginning FSP 2.2 specifications Fsps Config Upd "FspEventHandler" was moved to Fsps Arch Upd. Hence we were not seeing Fsps Debug log was not using coreboot debug library. This change assigns Fspd Arch Upd FspEventHandler with coreboot ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER Kconfig is enabled. Before: Dumping FSPS_UPD - Size: 0x00001510 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 0x00 0x00 0x00000010: 0x00 With the fix: [SPEW ] Dumping FSPS_UPD - Size: 0x00001528 [SPEW ] 0x00000000: 0x41 0x44 0x4C 0x55 0x50 0x44 0x5F 0x53 0x02 [SPEW ] 0x00000010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 [SPEW ] 0x00000020: 0x01 0x00 0x00 0x00 0x20 0x00 0x00 0x00 0xAA [SPEW ] 0x00000030: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 [SPEW ] 0x00000040: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 BUG=b:237263080 TEST=Able to build and boot MTL RVP, verified the FSP-S debug log is using coreboot debug library. Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Ie63258f6427b3da7927a866bc3767f548b16e3e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
* mb/google/nissa/var/pujjo: Enable PCIe port 4 for WLANLeo Chou2022-07-271-0/+20
| | | | | | | | | | | | | Pujjo support WLAN device, enable PCIe port 4 for WLAN device BUG=b:239899932 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* soc/mediatek/mt8195: Skip PCIe ops for eMMC SKUsYu-Ping Wu2022-07-271-2/+7
| | | | | | | | | | | | | | | | | To avoid unnecessary PCIe early initialization for non-NVMe devices (which would take about 150ms on dojo), skip setting PCIe ops when initializing mt8195 SoC. BUG=b:238850212 TEST=emerge-cherry coreboot TEST=Dojo SKU1 (eMMC) boot time <= 1s BRANCH=cherry Change-Id: I8945890ba422c0c4eb42683935220b7afbb80dfd Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
* mb/google/cherry: Introduce mainboard_needs_pcie_initYu-Ping Wu2022-07-272-0/+31
| | | | | | | | | | | | | | | | | | Implement mainboard_needs_pcie_init() for cherry as a callback for mt8195 SoC to determine whether to initialize PCIe. When the SKU id is unknown or unprovisioned (for example at the beginning of the factory flow), we should still initialize PCIe. Otherwise the devices with NVMe will fail to boot. BUG=b:238850212 TEST=emerge-cherry coreboot BRANCH=cherry Change-Id: I2ed0ceeb37d2924ca16485fb2d130959a7eff102 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65992 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-09 17:09:07 +0000