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* util/elogtool: Mark redundant boot mode event type as `deprecated`Subrata Banik2022-08-061-108/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds `_DEPRECATED_` tag to ChromeOS boot mode related event logging types as below: * ELOG_TYPE_CROS_RECOVERY_MODE <---- to record recovery boot reason while booting into recovery mode * ELOG_TYPE_CROS_DEVELOPER_MODE <--- if the platform is booted into developer mode. * ELOG_TYPE_CROS_DIAGNOSTICS <---- if the platform is booted into diagnostic mode. Drop static structure `cros_deprecated_recovery_reasons` as it has been replaced by vb2_get_recovery_reason_string() function. ELOG_TYPE_FW_BOOT_INFO event type is now used to record all those related fw boot info along with ChromeOS boot mode/reason etc. BUG=b:215615970 TEST=Build and boot google/kano to ChromeOS. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I932952ce32337e2d54473667ce17582a90882da8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/cbfstool: Fix truncate command error handling and cbfs_image_from_buffer()Jakub Czapiga2022-08-034-7/+10
| | | | | | | | | | | | | | | | Check return value of cbfs_truncate_space() in cbfs_truncate(). Remove return from cbfs_image_from_buffer() to inform about invalid image region when incorrect offset header was provided. Also change header offset provided to mentioned function in cbfs_expand_to_region() and cbfs_truncate_space() from zero to HEADER_OFFSET_UNKNOWN, as they do not support images with cbfs master header. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ib009212692fb3594a826436df765860f54837154 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/cbfstool/elogtool: Support logging FW vboot info in elogSubrata Banik2022-08-021-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | List of changes: 1. Add support for new elog event type to log vboot info (type 0xB7). 2. Add support string for fw_slot name, boot status and boot mode. 3. Print fw slot information like FW try count, FW current slot, previous FW slot, previous FW boot result and boot mode. BUG=b:215615970 TEST=Able to build and boot google/kano to OS. localhost # elogtool list 0 | 2022-07-01 11:10:27 | Log area cleared | 4088 1 | 2022-07-01 11:10:27 | Memory Cache Update | Normal | Success 2 | 2022-07-01 11:10:42 | System boot | 360 3 | 2022-07-01 11:10:42 | Power Fail 4 | 2022-07-01 11:10:42 | SUS Power Fail 5 | 2022-07-01 11:10:42 | ACPI Wake | S5 6 | 2022-07-01 11:10:42 | Wake Source | Power Button | 0 7 | 2022-07-01 11:10:42 | Chrome OS Developer Mode 8 | 2022-07-01 11:10:42 | Firmware vboot info | boot_mode=Developer | fw_tried=B | fw_try_count=0 | fw_prev_tried=B | fw_prev_result=Unknown 9 | 2022-07-01 11:11:42 | System boot | 361 10 | 2022-07-01 11:11:42 | System Reset 11 | 2022-07-01 11:11:42 | Firmware vboot info | boot_mode=Developer | fw_tried=B | fw_try_count=0 | fw_prev_tried=B | fw_prev_result=Success localhost # crossystem recovery_request=1 localhost # elogtool list 41 | 2022-07-13 12:13:48 | Firmware vboot info | boot_mode=Manual recovery boot | recovery_reason: 0x1/0 (Recovery requested from legacy utility) | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I48b5d54723683cef51e416fc6f58da000507fbcc Reviewed-on: https://review.coreboot.org/c/coreboot/+/65562 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/spd_tools/spd_gen/lp5: Remove maxSpeed for SabrinaKarthikeyan Ramasubramanian2022-08-011-12/+0
| | | | | | | | | | | | | | | Firmware component that does memory training already limits the memory controller to train at 5500 Mbps for all memory parts in Sabrina. Hence removing this interim SPD change to limit the speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I2bc82c7407a97aac282708c3e0bd56ae99a8fc31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66290 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Support PSP whitelist file on recovery A/B layoutKarthikeyan Ramasubramanian2022-08-011-1/+1
| | | | | | | | | | | | | | | | This is required to enable PSP verstage on SoCs with recovery A/B layout. BUG=b:217414563 TEST=Ensure that the concerned type 0x3a PSP entry is present in PSP L2 directory. Build and boot to OS in Skyrim with both PSP and x86 verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I5fae2b5dbcc95a99af3df9f59bb8516280ec1281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* crossgcc: Upgrade LLVM from 13.0.1 to 14.0.6Elyes Haouas2022-07-309-6/+6
| | | | | | | | | | Test build for QEMU x86 i440fx/piix4. Change-Id: I97d059947f7049b2491a98985795a4655891c3b3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* util/liveiso/common: Install devmem2 and pcimemFelix Singer2022-07-281-0/+2
| | | | | | | | | | | | devmem2 and pcimem are useful tools which allow working (reading and writing) with memory mapped IO. Change-Id: Ifda547b44af3c8e11cd4171a1dfbce3713455303 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66171 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/amdfwtool: Update the location of PSP verstage and signing keyKarthikeyan Ramasubramanian2022-07-261-2/+2
| | | | | | | | | | | | | | | On SoCs which use A/B recovery layout, PSP verstage and signing keys are expected to be present only in PSP L2 directory. Update amdfwtool to include the PSP verstage and signing key only in PSP L2 directory. BUG=b:239519603, b:238938623 TEST=Build and boot to OS in Skyrim with PSP verstage. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ieeb415be800b7ccf10d6983eb0b567e0a5eaa955 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util/kconfig: Add README.md documenting the uprev procedurePatrick Georgi2022-07-221-0/+39
| | | | | | | | Change-Id: I2e74f1c5cb1657e11d4f7ea101549329274102db Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/spd_tools: Limit memory speed to 5500 Mbps for SabrinaKarthikeyan Ramasubramanian2022-07-191-5/+17
| | | | | | | | | | | | | | In Sabrina platform, memory speed is limited to 5500 Mbps. Update the SPD generation tool to limit to that speed. BUG=b:238074863 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ie3507898167012e0d812c9b1aacba72e9055fcd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
* lint/checkpatch: Add check for used comma where semicolon could beElyes Haouas2022-07-191-0/+11
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I6d3a49378008bad61b2a18bd8cb28be952a18006 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Add a check for use of self-assignmentsElyes Haouas2022-07-191-0/+11
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: If47a7826ee67a2be25a4caa2a447484e5f11411b Reviewed-on: https://review.coreboot.org/c/coreboot/+/65836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Add a check for existence of a commit logElyes Haouas2022-07-191-0/+13
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I4e3b98140d900c5717f4badde71c7be88fd1e23a Reviewed-on: https://review.coreboot.org/c/coreboot/+/65835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Update 'Check patch "separator" and "signoff"'Elyes Haouas2022-07-191-4/+69
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Id3d7375216af5bf75ed7ce61fa8ea2dfebe8ac77 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Update 'check for unwanted Gerrit info'Elyes Haouas2022-07-191-4/+14
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I856bfa0f0d39fda549671b1029cccdc39f831bab Reviewed-on: https://review.coreboot.org/c/coreboot/+/65833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Update 'uncoalesced string fragments'Elyes Haouas2022-07-191-3/+9
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I21b2a0d87cbf610fc48e273ed78ab779ad4a6932 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65832 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Update 'concatenated string without spaces between elements'Elyes Haouas2022-07-191-3/+11
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I04e58aca4a30e82f3da0cda08403d0daf3b5fb10 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Update 'check indentation of a line with a break'Elyes Haouas2022-07-191-3/+6
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I79170a45cd8184ebc816b4f16656a3cfdc257f60 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Update 'check for logical continuations'Elyes Haouas2022-07-191-2/+10
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I222e3378ded4cd73d0141cd1e38ac3282d311cc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Update 'check for adding lines without a newline'Elyes Haouas2022-07-191-2/+5
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bd68e9a6609a3dfa7dc856f24e4b616714d9990 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* lint/checkpatch: Update 'check for assignments on the start of a line'Elyes Haouas2022-07-191-2/+8
| | | | | | | | | | This reduce the difference with linux v5.19-rc7. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ia7d4b0176bad849e79f037f74c3d99ce9eb061c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65825 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* util/xcompile/xcompile: Define GCOV_${TARCH}Yu-Ping Wu2022-07-151-0/+1
| | | | | | | | | | | | | | | | When payloads analyze the coverage using gcov (or lcov), the gcov version must match the CC version. Otherwise gcov would fail to parse the .gcno files. Therefore, define GCOV_${TARCH} in xcompile, so that payloads don't need to do tedious string manipulations to find the right gcov path. Change-Id: If2fc329810c463a3d2c56deaf4e4a3fc3c0a3ed9 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org>
* commonlib: Substitude macro "__unused" in compiler.hBill XIE2022-07-142-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Since there are many identifiers whose name contain "__unused" in headers of musl libc, introducing a macro which expands "__unused" to the source of a util may have disastrous effect during its compiling under a musl-based platform. However, it is hard to detect musl at build time as musl is notorious for having explicitly been refusing to add a macro like "__MUSL__" to announce its own presence. Using __always_unused and __maybe_unused for everything may be a good idea. This is how it works in the Linux kernel, so that would at least make us match some other standard rather than doing our own thing (especially since the other compiler.h shorthand macros are also inspired by Linux). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I547ae3371d7568f5aed732ceefe0130a339716a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/spd_tools: Add support for 7500 MT/s lp5 modulesJack Rosenthal2022-07-141-0/+5
| | | | | | | | | | | | | | | | | | spd_tools does not support LP5x modules yet, and the easiest way to do this is to add support for 7500 MT/s in lp5.go (reference the comments on CB:65063). BUG=b:238674174 BRANCH=firmware-brya-14505.B TEST=With follow-on CL, run: util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I1558d69bc6f28c02c20aa9cd87d4543c1cf52afd Reviewed-on: https://review.coreboot.org/c/coreboot/+/65794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
* util/spd_tools: Add Intel Meteor Lake (MTL) platformSubrata Banik2022-07-143-1/+4
| | | | | | | | | | | | | | This patch add support for MTL platform to the `spd_tools`. This would be useful to create dynamic SPD for rex variants. BUG=b:224325352 TEST=Able to generate SPD for LP5 DRAM part. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I1db6e3a63d2842c12ef0f256ba1d32b9258670f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
* Remove executable flag from source codes and text filesPetr Cvek2022-07-142-0/+0
| | | | | | | | | | | Markdown, definition file and sconfig source codes don't need to be executables. This patch fixes that. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Change-Id: Ic97d684318c689259f7895e3dfbd552434c3882e Reviewed-on: https://review.coreboot.org/c/coreboot/+/65807 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util: Allow installing to a build rootTim Crawford2022-07-123-3/+6
| | | | | | | | | | | | | Modify util Makefiles to allow installing to a build root specified by DESTDIR. Allows using the `install` target for packaging. Change-Id: I3a31ea0fde9922731e1621dcc8f94b2c1326c93c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60540 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <patrick@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/release/build-release: Use `git log … -1` over `|head -1`Paul Menzel2022-07-061-1/+1
| | | | | | | | | | | | Avoid piping to `head` to print the top line, and do it in `git log` directly. Change-Id: Id9b99b06c5bdd9c381bd039fc1914a9a2f332aa6 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64941 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* treewide: Unify Google brandingJon Murphy2022-07-048-20/+20
| | | | | | | | | | | | | | | | | Branding changes to unify and update Chrome OS to ChromeOS (removing the space). This CL also includes changing Chromium OS to ChromiumOS as well. BUG=None TEST=N/A Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/amdfwtool: Initalize all variables before useFred Reitberger2022-06-301-12/+1
| | | | | | | | | | | | | | | | Not all of the fields of the amd_cb_config structure were properly initialized. Rather than initialize each field individually, initialize the entire structure to 0. TEST: Boot chausie Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia343f01bce3956d66d01ce485b43963193c9df31 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* crossgcc: Upgrade CMake from 3.23.0 to 3.23.2Elyes Haouas2022-06-273-2/+2
| | | | | | | | Change-Id: I3613522fa2a958d2a42674f17aa794bdda4ca74a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63123 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* nvramtool: Fix building on Linux systems with musl libcEvgeny Zinoviev2022-06-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | Current implementation only supports glibc (by looking for __GLIBC__) and fails to build on systems with alternative libc implementations, such as musl; sys/io.h is never included, there are no outb/inb functions which results in undefined references at linking stage. Using __linux__ instead of __GLIBC__ to test whether the system is Linux seems to be a more proper way to detect Linux and it also fixes nvramtool compilation on musl systems. Tested on Gentoo Linux with musl 1.2.2 (builds and works fine) and Void Linux with glibc (still builds and works fine). Change-Id: Idcdc3a033b40f16a6053209813f1e06209ee459a Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48757 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/ifdtool: Fix printing or setting PCH strapsArthur Heymans2022-06-231-7/+7
| | | | | | | | | | | When printing or setting the PCH straps use the PSL directly instead of multiplying it by 4. Change-Id: Ia91697fdf0c6d80502e8611b259c444f39c6cd57 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/lint: Add coreboot specific dictionary fileMartin Roth2022-06-221-0/+2173
| | | | | | | | | | | | This is a wordlist that I've compiled to use in spellcheckers to ignore all of the coreboot specific terms. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I718519000eaf31786380474eb71b99ca442e3bed Reviewed-on: https://review.coreboot.org/c/coreboot/+/64809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/inteltool: Add an additional Device ID for Intel HD 4400 GPUArashk Mahshidfar2022-06-222-0/+3
| | | | | | | | | | Add 0x0A16 as a Device ID for Intel HD 4400 Change-Id: I0129376c0ce005c1bfabaa9dbd8d8dfc6c92e5d3 Signed-off-by: Arashk Mahshidfar <arashkmahshidfar@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* util/cbfstool: Set `USE_FLASHROM=0` to build vbootAngel Pons2022-06-191-0/+1
| | | | | | | | | | | | | | | | cbfstool does not need to build vboot with flashrom support. TEST=./util/abuild/abuild -a --timeless -y -c $(nproc) -Z -t hp/280_g2 no longer fails due to missing libflashrom.h header. Change-Id: I57edcb1b67baa4c458874b11e9ca0238b4419c46 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* util/cbfstool/common.c: Deduplicate buffer_create() logicEdward O'Callaghan2022-06-161-5/+5
| | | | | | | | | | | BUG=b:207808292,b:231152447 TEST=builds with vboot_ref uprev. Change-Id: Id7d9b6f5254b08720eebb37151e12ee68ed7f8d7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65145 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* util/cbfstool: Decouple elogtool from vboot_ref flashrom codeEdward O'Callaghan2022-06-164-10/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently elogtool sub-proccesses flashrom as calling libflashrom requires a missing function from the previous flashrom release. Pending a new release of flashrom we must continue to use subprocess. However the current subprocess wrapper implementation lives in vboot_reference which is a git sub-module of coreboot. This causes all sorts of grief keeping a subprocess ABI stable from vboot_reference when the rest of vboot_reference builds of HEAD of the flashrom tree (i.e., using unreleased libflashrom functions). In order to not keep finding ourseleves in a bind between the two separately moving trees with different build environments, decouple elogtool with its own mini copy of flashrom subprocess wrapping logic. Squash in, util/cbfstool/elogtool.c: Convert args into struct in flashrom helper vboot signatures for flashrom r/w helpers changed in the upstream commit bd2971326ee94fc5. Reflect the change here to allow vboot ref and coreboot to realign. BUG=b:207808292,b:231152447 TEST=builds with vboot_ref uprev. Change-Id: I04925e4d9a44b52e4a6fb6f9cec332cab2c7c725 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
* util/mb/google: add support for nissaShou-Chieh Hsu2022-06-146-0/+39
| | | | | | | | | | | | | Add the file template for creating a new variant of Nissa. BUG=b:229550821 Signed-off-by: Shou-Chieh Hsu <shouchieh@google.com> Change-Id: I04f75ff91f9851b82641f703ba950b04c22e2e72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64045 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
* util/liveiso: Update to NixOS 22.05Felix Singer2022-06-133-3/+2
| | | | | | | | | | | | | Update configs for NixOS 22.05. pulseaudio-modules-bt has been abandoned, and is superseded by pulseaudio's native Bluetooth functionality. Thus, remove it. Change-Id: Ic3b1dbc3c2ab092b576ba2151c93c74d4f298efc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@tutanota.com>
* crossgcc/gnat.patch: Add additional gnatlib object filesNico Huber2022-06-101-0/+30
| | | | | | | | | | | | | | | | | | | | | | | Newer host versions of gnatbind miss these when building the cross gnat1 and gnatbind. Tested with the following host compilers with and without bootstrapping that the resulting coreboot images of three boards stay the same: * GCC 4.9.2 (Debian) * GCC 6.3 (Debian) * GCC 7.4 (Debian) * GCC 8.3 (Debian) * GCC 9.4 (Debian) * GCC 10.2 (Debian) * GCC 12.1 (ArchLinux) Change-Id: I09c6b3cc7b15f1c505acd3ec2c1959b101d6dfb7 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65000 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* crossgcc/gnat.patch: Never treat warnings as errorsNico Huber2022-06-101-1/+1
| | | | | | | | | | | | | | | | | We used to disable individual warnings that are expected when building our GCC version with a newer one. Not all warnings can be disabled indvidually, though, and it's much easier to simply allow warnings. As a plus, we get the warnings in the log (in case anybody would ever look into it). Partially fixes building with host GCC 12.1. Change-Id: I8fafec4fc49db73b6dba311c775eea2cc92a9b48 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* util/util_readme: update to give additional informationMartin Roth2022-06-072-3/+33
| | | | | | | | | | | | | | Add a note to the top of the util.md document saying not to edit it. The Documentation/util.md file had been updated to contain additional information at the bottom. This copies that information into the file after it's been created. Change-Id: I4b08439420ceb706df62e3949406585ea34c1514 Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* util, Documentation: Run util_readme.sh to regen util.mdMartin Roth2022-06-071-18/+26
| | | | | | | | | Change-Id: Ie14204d0637bb5081e2fae4a9a0e2590bf7abeeb Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64582 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
* cbfstool: Expand CBFS verification validity checkJulius Werner2022-06-071-8/+29
| | | | | | | | | | | | | | | | | | | | | This patch adds a new line to `cbfstool print -v` output that records the overall CBFS verification health of the image. While this info was already visible from individual fields before, it's nice to have a one-stop location to see "this is a good image" without having to carefully parse a lot of output manually. Also add a few lines to the Makefile that check whether this field is valid for the final image (it always should be, but hopefully this check will allow us to catch regressions like the one fixed by CB:64547 sooner in the future). BUG=b:233263447 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1b74b01a55b22294556007aaee835d0fdb9e1c63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* inteltool/gpio_names/tigerlake.h: Fix HVMOS pad countMichał Żygowski2022-06-031-1/+1
| | | | | | | | | Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I344fd2db9d53ad5e82240aaa2b766ac0d8a2045d Reviewed-on: https://review.coreboot.org/c/coreboot/+/64464 Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
* util/scripts/cross-repo-cherrypick: Modify output formatPatrick Georgi2022-06-031-2/+5
| | | | | | | | | | | | | | | | As far as I know the Chromium OS team is the only user of this script, so align its output with that of other tools used there: - Replace "Original-Commit-Id" with "GitOrigin-RevId" - Reuse Change-Id instead of moving it to the Original- prefix, which leads to the creation of a new Change ID. Change-Id: I8c39c512901c83a64f00aa48a539e6621f827242 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
* util/release/build-release: Use short git hash for .coreboot-version4.17Martin Roth2022-06-031-1/+2
| | | | | | | | | | | | | | | Builds were suddenly failing when the release was done, because the coreboot version was overflowing a 64 character limit. We don't need or use the full hash in other places, so limit the hash to just what's needed to identify the commit. Change-Id: I57c535ca251792cae2c9a9c951e6b44bb61e4e78 Signed-off-by: Martin Roth <martin@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
* cbfs: Add CBFS_TYPE_INTEL_FIT and exclude it from CBFS verificationJulius Werner2022-06-012-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel Firmware Interface Table (FIT) is a bit of an annoying outlier among CBFS files because it gets manipulated by a separate utility (ifittool) after cbfstool has already added it to the image. This will break file hashes created for CBFS verification. This is not actually a problem when booting, since coreboot never actually loads the FIT from CBFS -- instead, it's only in the image for use by platform-specific mechanisms that run before coreboot's bootblock. But having an invalid file hash in the CBFS image is confusing when you want to verify that the image is correctly built for verification. This patch adds a new CBFS file type "intel_fit" which is only used for the intel_fit (and intel_fit_ts, if applicable) file containing the FIT. cbfstool will avoid generating and verifying file hashes for this type, like it already does for the "bootblock" and "cbfs header" types. (Note that this means that any attempt to use the CBFS API to actually access this file from coreboot will result in a verification error when CBFS verification is enabled.) Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I1c1bb6dab0c9ccc6e78529758a42ad3194cd130c Reviewed-on: https://review.coreboot.org/c/coreboot/+/64736 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOADJulius Werner2022-06-013-11/+11
| | | | | | | | | | | | | | There are too many "FIT" in firmware land. In order to reduce possible confusion of CBFS_TYPE_FIT with the Intel Firmware Interface Table, this patch renames it to CBFS_TYPE_FIT_PAYLOAD (including the cbfstool argument, so calling scripts will now need to replace `-t fit` with `-t fit_payload`). Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I826cefce54ade06c6612c8a7bb53e02092e7b11a Reviewed-on: https://review.coreboot.org/c/coreboot/+/64735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-11 14:54:27 +0000