diff options
| author | Robert Guenzel <robert.guenzel@intel.com> | 2022-12-08 16:44:15 +0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2022-12-08 10:04:24 +0000 |
| commit | 1c75bf3c21da79b1bc1d50cfc593b57f73f2c560 (patch) | |
| tree | d520932d72d3aa74ad2faee1b6b60a7391a29038 | |
| parent | c14c4719f9372c62d3f43c1ca3d95989c65e9d88 (diff) | |
| download | edk2-1c75bf3c21da79b1bc1d50cfc593b57f73f2c560.tar.gz edk2-1c75bf3c21da79b1bc1d50cfc593b57f73f2c560.tar.bz2 edk2-1c75bf3c21da79b1bc1d50cfc593b57f73f2c560.zip | |
UefiCpuPkg: Bug fix in 5LPage handling
When build in DEBUG, the code asserts that 5LPage support is there
when the physical address width is larger than 48.
In a RELEASE build it will just force LA57 to 1 in CR4
even if CPUID(7).ECX[16] says it is not supported.
UefiCpuPkg: Bug fix in 5LPage handling
The hang (in the ASSERT) in DEBUG is not warranted as there are
legal configurations with CPUID(7).ECX[16](==LA57)=0
and with a physical address width of larger than 48 (like 52).
This is also supported by this code:
https://github.com/tianocore/edk2/blob/master/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c#L221
There (as long as physical address width is smaller or equal to 52)
any address width above 48 will be reduced to 48 and the
system can and will work without 5LPaging.
The forced setting of LA57 in CR4 (in the absence of LA57 in CPUID(7).ECX)
is a spec violation and should not happen.
Hence the proposed fix
a) removes the assert.
b) only returns TRUE from Is5LevelPagingNeeded if 5LPaging is actually
supported by HW.
Signed-off-by: Robert Guenzel <robert.guenzel@intel.com>
| -rw-r--r-- | UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c index 6587212f4e..bf90050503 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -1,7 +1,7 @@ /** @file
Page Fault (#PF) handler for X64 processors
-Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -104,8 +104,9 @@ Is5LevelPagingNeeded ( ExtFeatureEcx.Bits.FiveLevelPage
));
- if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) {
- ASSERT (ExtFeatureEcx.Bits.FiveLevelPage == 1);
+ if ((VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) &&
+ (ExtFeatureEcx.Bits.FiveLevelPage == 1))
+ {
return TRUE;
} else {
return FALSE;
|