diff options
| author | Michael Kubacki <michael.kubacki@microsoft.com> | 2021-12-05 14:53:50 -0800 |
|---|---|---|
| committer | mergify[bot] <37929162+mergify[bot]@users.noreply.github.com> | 2021-12-07 17:24:28 +0000 |
| commit | 429309e0c6b74792d679681a8edd0d5ae0ff850c (patch) | |
| tree | 9d26d88024790b459c60a44e14500b7c7076f0d1 | |
| parent | 7c2a6033c149625482a18cd51b65513c8fb8fe15 (diff) | |
| download | edk2-429309e0c6b74792d679681a8edd0d5ae0ff850c.tar.gz edk2-429309e0c6b74792d679681a8edd0d5ae0ff850c.tar.bz2 edk2-429309e0c6b74792d679681a8edd0d5ae0ff850c.zip | |
ArmPkg: Apply uncrustify changes
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737
Apply uncrustify changes to .c/.h files in the ArmPkg package
Cc: Andrew Fish <afish@apple.com>
Cc: Leif Lindholm <leif@nuviainc.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Andrew Fish <afish@apple.com>
142 files changed, 6195 insertions, 5391 deletions
diff --git a/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c b/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c index 137dd787ea..8bb8155590 100644 --- a/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c +++ b/ArmPkg/Drivers/ArmCrashDumpDxe/ArmCrashDumpDxe.c @@ -12,21 +12,23 @@ #include <Library/UefiBootServicesTableLib.h>
#include <Protocol/Cpu.h>
-STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;
+STATIC EFI_CPU_ARCH_PROTOCOL *mCpu;
EFI_STATUS
EFIAPI
ArmCrashDumpDxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&mCpu);
- ASSERT_EFI_ERROR(Status);
+ ASSERT_EFI_ERROR (Status);
- return mCpu->RegisterInterruptHandler (mCpu,
- EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,
- &DefaultExceptionHandler);
+ return mCpu->RegisterInterruptHandler (
+ mCpu,
+ EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS,
+ &DefaultExceptionHandler
+ );
}
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c index 5fb33c5465..cd12fcda27 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicCommonDxe.c @@ -11,8 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent VOID
EFIAPI
IrqInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
);
VOID
@@ -26,14 +26,13 @@ ExitBootServicesEvent ( EFI_HANDLE gHardwareInterruptHandle = NULL;
// Notifications
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// Maximum Number of Interrupts
-UINTN mGicNumInterrupts = 0;
+UINTN mGicNumInterrupts = 0;
HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL;
-
/**
Calculate GICD_ICFGRn base address and corresponding bit
field Int_config[1] of the GIC distributor register.
@@ -47,21 +46,21 @@ HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers = NULL; **/
EFI_STATUS
GicGetDistributorIcfgBaseAndBit (
- IN HARDWARE_INTERRUPT_SOURCE Source,
- OUT UINTN *RegAddress,
- OUT UINTN *Config1Bit
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ OUT UINTN *RegAddress,
+ OUT UINTN *Config1Bit
)
{
- UINTN RegIndex;
- UINTN Field;
+ UINTN RegIndex;
+ UINTN Field;
if (Source >= mGicNumInterrupts) {
- ASSERT(Source < mGicNumInterrupts);
+ ASSERT (Source < mGicNumInterrupts);
return EFI_UNSUPPORTED;
}
- RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant
- Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
+ RegIndex = Source / ARM_GIC_ICDICFR_F_STRIDE; // NOTE: truncation is significant
+ Field = Source % ARM_GIC_ICDICFR_F_STRIDE;
*RegAddress = PcdGet64 (PcdGicDistributorBase)
+ ARM_GIC_ICDICFR
+ (ARM_GIC_ICDICFR_BYTES * RegIndex);
@@ -71,8 +70,6 @@ GicGetDistributorIcfgBaseAndBit ( return EFI_SUCCESS;
}
-
-
/**
Register Handler for the specified interrupt source.
@@ -87,13 +84,13 @@ GicGetDistributorIcfgBaseAndBit ( EFI_STATUS
EFIAPI
RegisterInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN HARDWARE_INTERRUPT_HANDLER Handler
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN HARDWARE_INTERRUPT_HANDLER Handler
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -108,25 +105,25 @@ RegisterInterruptSource ( gRegisteredInterruptHandlers[Source] = Handler;
// If the interrupt handler is unregistered then disable the interrupt
- if (NULL == Handler){
+ if (NULL == Handler) {
return This->DisableInterruptSource (This, Source);
} else {
return This->EnableInterruptSource (This, Source);
}
}
-STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
+STATIC VOID *mCpuArchProtocolNotifyEventRegistration;
STATIC
VOID
EFIAPI
CpuArchEventProtocolNotify (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
- EFI_CPU_ARCH_PROTOCOL *Cpu;
- EFI_STATUS Status;
+ EFI_CPU_ARCH_PROTOCOL *Cpu;
+ EFI_STATUS Status;
// Get the CPU protocol that this driver requires.
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
@@ -137,17 +134,28 @@ CpuArchEventProtocolNotify ( // Unregister the default exception handler.
Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
- __FUNCTION__, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Cpu->RegisterInterruptHandler() - %r\n",
+ __FUNCTION__,
+ Status
+ ));
return;
}
// Register to receive interrupts
- Status = Cpu->RegisterInterruptHandler (Cpu, ARM_ARCH_EXCEPTION_IRQ,
- Context);
+ Status = Cpu->RegisterInterruptHandler (
+ Cpu,
+ ARM_ARCH_EXCEPTION_IRQ,
+ Context
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: Cpu->RegisterInterruptHandler() - %r\n",
- __FUNCTION__, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Cpu->RegisterInterruptHandler() - %r\n",
+ __FUNCTION__,
+ Status
+ ));
}
gBS->CloseEvent (Event);
@@ -157,13 +165,13 @@ EFI_STATUS InstallAndRegisterInterruptService (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
- IN EFI_EVENT_NOTIFY ExitBootServicesEvent
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
+ IN EFI_EVENT_NOTIFY ExitBootServicesEvent
)
{
- EFI_STATUS Status;
- CONST UINTN RihArraySize =
- (sizeof(HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
+ EFI_STATUS Status;
+ CONST UINTN RihArraySize =
+ (sizeof (HARDWARE_INTERRUPT_HANDLER) * mGicNumInterrupts);
// Initialize the array for the Interrupt Handlers
gRegisteredInterruptHandlers = AllocateZeroPool (RihArraySize);
@@ -191,7 +199,8 @@ InstallAndRegisterInterruptService ( TPL_CALLBACK,
CpuArchEventProtocolNotify,
InterruptHandler,
- &mCpuArchProtocolNotifyEventRegistration);
+ &mCpuArchProtocolNotifyEventRegistration
+ );
// Register for an ExitBootServicesEvent
Status = gBS->CreateEvent (
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.c b/ArmPkg/Drivers/ArmGic/ArmGicDxe.c index a210a6af10..1b40d8f942 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.c @@ -32,12 +32,12 @@ Abstract: **/
EFI_STATUS
InterruptDxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- ARM_GIC_ARCH_REVISION Revision;
+ EFI_STATUS Status;
+ ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h index c78b788ac0..0f621682a1 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicDxe.h +++ b/ArmPkg/Drivers/ArmGic/ArmGicDxe.h @@ -21,7 +21,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Protocol/HardwareInterrupt.h>
#include <Protocol/HardwareInterrupt2.h>
-extern UINTN mGicNumInterrupts;
+extern UINTN mGicNumInterrupts;
extern HARDWARE_INTERRUPT_HANDLER *gRegisteredInterruptHandlers;
// Common API
@@ -29,33 +29,32 @@ EFI_STATUS InstallAndRegisterInterruptService (
IN EFI_HARDWARE_INTERRUPT_PROTOCOL *InterruptProtocol,
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *Interrupt2Protocol,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
- IN EFI_EVENT_NOTIFY ExitBootServicesEvent
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler,
+ IN EFI_EVENT_NOTIFY ExitBootServicesEvent
);
EFI_STATUS
EFIAPI
RegisterInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN HARDWARE_INTERRUPT_HANDLER Handler
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN HARDWARE_INTERRUPT_HANDLER Handler
);
// GicV2 API
EFI_STATUS
GicV2DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
);
// GicV3 API
EFI_STATUS
GicV3DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
);
-
// Shared code
/**
@@ -71,9 +70,9 @@ GicV3DxeInitialize ( **/
EFI_STATUS
GicGetDistributorIcfgBaseAndBit (
- IN HARDWARE_INTERRUPT_SOURCE Source,
- OUT UINTN *RegAddress,
- OUT UINTN *Config1Bit
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ OUT UINTN *RegAddress,
+ OUT UINTN *Config1Bit
);
#endif // ARM_GIC_DXE_H_
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c index bd4b5edb90..58ab45f812 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c @@ -24,13 +24,13 @@ + ARM_GICR_SGI_VLPI_FRAME_SIZE \
+ ARM_GICR_SGI_RESERVED_FRAME_SIZE)
-#define ISENABLER_ADDRESS(base,offset) ((base) + \
+#define ISENABLER_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ISENABLER + 4 * (offset))
-#define ICENABLER_ADDRESS(base,offset) ((base) + \
+#define ICENABLER_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GICR_ICENABLER + 4 * (offset))
-#define IPRIORITY_ADDRESS(base,offset) ((base) + \
+#define IPRIORITY_ADDRESS(base, offset) ((base) +\
ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + 4 * (offset))
/**
@@ -57,15 +57,15 @@ SourceIsSpi ( STATIC
UINTN
GicGetCpuRedistributorBase (
- IN UINTN GicRedistributorBase,
- IN ARM_GIC_ARCH_REVISION Revision
+ IN UINTN GicRedistributorBase,
+ IN ARM_GIC_ARCH_REVISION Revision
)
{
- UINTN MpId;
- UINTN CpuAffinity;
- UINTN Affinity;
- UINTN GicCpuRedistributorBase;
- UINT64 TypeRegister;
+ UINTN MpId;
+ UINTN CpuAffinity;
+ UINTN Affinity;
+ UINTN GicCpuRedistributorBase;
+ UINT64 TypeRegister;
MpId = ArmReadMpidr ();
// Define CPU affinity as:
@@ -83,7 +83,7 @@ GicGetCpuRedistributorBase ( do {
TypeRegister = MmioRead64 (GicCpuRedistributorBase + ARM_GICR_TYPER);
- Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
+ Affinity = ARM_GICR_TYPER_GET_AFFINITY (TypeRegister);
if (Affinity == CpuAffinity) {
return GicCpuRedistributorBase;
}
@@ -107,7 +107,7 @@ GicGetCpuRedistributorBase ( UINTN
EFIAPI
ArmGicGetInterfaceIdentification (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
)
{
// Read the GIC Identification Register
@@ -117,10 +117,10 @@ ArmGicGetInterfaceIdentification ( UINTN
EFIAPI
ArmGicGetMaxNumInterrupts (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
)
{
- UINTN ItLines;
+ UINTN ItLines;
ItLines = MmioRead32 (GicDistributorBase + ARM_GIC_ICDICTR) & 0x1F;
@@ -133,10 +133,10 @@ ArmGicGetMaxNumInterrupts ( VOID
EFIAPI
ArmGicSendSgiTo (
- IN INTN GicDistributorBase,
- IN INTN TargetListFilter,
- IN INTN CPUTargetList,
- IN INTN SgiId
+ IN INTN GicDistributorBase,
+ IN INTN TargetListFilter,
+ IN INTN CPUTargetList,
+ IN INTN SgiId
)
{
MmioWrite32 (
@@ -162,12 +162,12 @@ ArmGicSendSgiTo ( UINTN
EFIAPI
ArmGicAcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- OUT UINTN *InterruptId
+ IN UINTN GicInterruptInterfaceBase,
+ OUT UINTN *InterruptId
)
{
- UINTN Value;
- ARM_GIC_ARCH_REVISION Revision;
+ UINTN Value;
+ ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@@ -193,11 +193,11 @@ ArmGicAcknowledgeInterrupt ( VOID
EFIAPI
ArmGicEndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
)
{
- ARM_GIC_ARCH_REVISION Revision;
+ ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@@ -212,25 +212,26 @@ ArmGicEndOfInterrupt ( VOID
EFIAPI
ArmGicSetInterruptPriority (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source,
- IN UINTN Priority
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source,
+ IN UINTN Priority
)
{
- UINT32 RegOffset;
- UINTN RegShift;
- ARM_GIC_ARCH_REVISION Revision;
- UINTN GicCpuRedistributorBase;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ ARM_GIC_ARCH_REVISION Revision;
+ UINTN GicCpuRedistributorBase;
// Calculate register offset and bit position
RegOffset = Source / 4;
- RegShift = (Source % 4) * 8;
+ RegShift = (Source % 4) * 8;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
- SourceIsSpi (Source)) {
+ SourceIsSpi (Source))
+ {
MmioAndThenOr32 (
GicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),
@@ -256,24 +257,25 @@ ArmGicSetInterruptPriority ( VOID
EFIAPI
ArmGicEnableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
)
{
- UINT32 RegOffset;
- UINTN RegShift;
- ARM_GIC_ARCH_REVISION Revision;
- UINTN GicCpuRedistributorBase;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ ARM_GIC_ARCH_REVISION Revision;
+ UINTN GicCpuRedistributorBase;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
- RegShift = Source % 32;
+ RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
- SourceIsSpi (Source)) {
+ SourceIsSpi (Source))
+ {
// Write set-enable register
MmioWrite32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset),
@@ -291,7 +293,7 @@ ArmGicEnableInterrupt ( // Write set-enable register
MmioWrite32 (
- ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
+ ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
1 << RegShift
);
}
@@ -300,24 +302,25 @@ ArmGicEnableInterrupt ( VOID
EFIAPI
ArmGicDisableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
)
{
- UINT32 RegOffset;
- UINTN RegShift;
- ARM_GIC_ARCH_REVISION Revision;
- UINTN GicCpuRedistributorBase;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ ARM_GIC_ARCH_REVISION Revision;
+ UINTN GicCpuRedistributorBase;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
- RegShift = Source % 32;
+ RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
- SourceIsSpi (Source)) {
+ SourceIsSpi (Source))
+ {
// Write clear-enable register
MmioWrite32 (
GicDistributorBase + ARM_GIC_ICDICER + (4 * RegOffset),
@@ -325,16 +328,16 @@ ArmGicDisableInterrupt ( );
} else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
- GicRedistributorBase,
- Revision
- );
+ GicRedistributorBase,
+ Revision
+ );
if (GicCpuRedistributorBase == 0) {
return;
}
// Write clear-enable register
MmioWrite32 (
- ICENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset),
+ ICENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset),
1 << RegShift
);
}
@@ -343,29 +346,30 @@ ArmGicDisableInterrupt ( BOOLEAN
EFIAPI
ArmGicIsInterruptEnabled (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
)
{
- UINT32 RegOffset;
- UINTN RegShift;
- ARM_GIC_ARCH_REVISION Revision;
- UINTN GicCpuRedistributorBase;
- UINT32 Interrupts;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ ARM_GIC_ARCH_REVISION Revision;
+ UINTN GicCpuRedistributorBase;
+ UINT32 Interrupts;
// Calculate enable register offset and bit position
RegOffset = Source / 32;
- RegShift = Source % 32;
+ RegShift = Source % 32;
Revision = ArmGicGetSupportedArchRevision ();
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
FeaturePcdGet (PcdArmGicV3WithV2Legacy) ||
- SourceIsSpi (Source)) {
+ SourceIsSpi (Source))
+ {
Interrupts = ((MmioRead32 (
GicDistributorBase + ARM_GIC_ICDISER + (4 * RegOffset)
)
- & (1 << RegShift)) != 0);
+ & (1 << RegShift)) != 0);
} else {
GicCpuRedistributorBase = GicGetCpuRedistributorBase (
GicRedistributorBase,
@@ -377,7 +381,7 @@ ArmGicIsInterruptEnabled ( // Read set-enable register
Interrupts = MmioRead32 (
- ISENABLER_ADDRESS(GicCpuRedistributorBase, RegOffset)
+ ISENABLER_ADDRESS (GicCpuRedistributorBase, RegOffset)
);
}
@@ -387,7 +391,7 @@ ArmGicIsInterruptEnabled ( VOID
EFIAPI
ArmGicDisableDistributor (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
)
{
// Disable Gic Distributor
@@ -397,10 +401,10 @@ ArmGicDisableDistributor ( VOID
EFIAPI
ArmGicEnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
)
{
- ARM_GIC_ARCH_REVISION Revision;
+ ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
@@ -415,10 +419,10 @@ ArmGicEnableInterruptInterface ( VOID
EFIAPI
ArmGicDisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
)
{
- ARM_GIC_ARCH_REVISION Revision;
+ ARM_GIC_ARCH_REVISION Revision;
Revision = ArmGicGetSupportedArchRevision ();
if (Revision == ARM_GIC_ARCH_REVISION_2) {
diff --git a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c index 7e8ae5ac26..aa4f0e2123 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c +++ b/ArmPkg/Drivers/ArmGic/ArmGicNonSecLib.c @@ -13,10 +13,10 @@ VOID
EFIAPI
ArmGicEnableDistributor (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
)
{
- ARM_GIC_ARCH_REVISION Revision;
+ ARM_GIC_ARCH_REVISION Revision;
/*
* Enable GIC distributor in Non-Secure world.
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c index 64b5054be8..25290342bd 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c @@ -22,11 +22,11 @@ Abstract: #define ARM_GIC_DEFAULT_PRIORITY 0x80
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
-extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol;
+extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol;
-STATIC UINT32 mGicInterruptInterfaceBase;
-STATIC UINT32 mGicDistributorBase;
+STATIC UINT32 mGicInterruptInterfaceBase;
+STATIC UINT32 mGicDistributorBase;
/**
Enable interrupt source Source.
@@ -42,12 +42,12 @@ STATIC EFI_STATUS
EFIAPI
GicV2EnableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -70,12 +70,12 @@ STATIC EFI_STATUS
EFIAPI
GicV2DisableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -99,13 +99,13 @@ STATIC EFI_STATUS
EFIAPI
GicV2GetInterruptSourceState (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN BOOLEAN *InterruptState
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN BOOLEAN *InterruptState
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -129,12 +129,12 @@ STATIC EFI_STATUS
EFIAPI
GicV2EndOfInterrupt (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -158,8 +158,8 @@ STATIC VOID
EFIAPI
GicV2IrqInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 GicInterrupt;
@@ -185,7 +185,7 @@ GicV2IrqInterruptHandler ( }
// The protocol instance produced by this driver
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV2Protocol = {
RegisterInterruptSource,
GicV2EnableInterruptSource,
GicV2DisableInterruptSource,
@@ -208,28 +208,28 @@ EFI_STATUS EFIAPI
GicV2GetTriggerType (
IN EFI_HARDWARE_INTERRUPT2_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
)
{
- UINTN RegAddress;
- UINTN Config1Bit;
- EFI_STATUS Status;
+ UINTN RegAddress;
+ UINTN Config1Bit;
+ EFI_STATUS Status;
Status = GicGetDistributorIcfgBaseAndBit (
- Source,
- &RegAddress,
- &Config1Bit
- );
+ Source,
+ &RegAddress,
+ &Config1Bit
+ );
if (EFI_ERROR (Status)) {
return Status;
}
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
- *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
} else {
- *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
}
return EFI_SUCCESS;
@@ -254,18 +254,22 @@ GicV2SetTriggerType ( IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
)
{
- UINTN RegAddress;
- UINTN Config1Bit;
- UINT32 Value;
- EFI_STATUS Status;
- BOOLEAN SourceEnabled;
-
- if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
- && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
- DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
- TriggerType));
- ASSERT (FALSE);
- return EFI_UNSUPPORTED;
+ UINTN RegAddress;
+ UINTN Config1Bit;
+ UINT32 Value;
+ EFI_STATUS Status;
+ BOOLEAN SourceEnabled;
+
+ if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
+ && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
+ {
+ DEBUG ((
+ DEBUG_ERROR,
+ "Invalid interrupt trigger type: %d\n", \
+ TriggerType
+ ));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
}
Status = GicGetDistributorIcfgBaseAndBit (
@@ -279,7 +283,7 @@ GicV2SetTriggerType ( }
Status = GicV2GetInterruptSourceState (
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source,
&SourceEnabled
);
@@ -296,7 +300,7 @@ GicV2SetTriggerType ( // otherwise GIC behavior is UNPREDICTABLE.
if (SourceEnabled) {
GicV2DisableInterruptSource (
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source
);
}
@@ -310,7 +314,7 @@ GicV2SetTriggerType ( // Restore interrupt state
if (SourceEnabled) {
GicV2EnableInterruptSource (
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source
);
}
@@ -318,7 +322,7 @@ GicV2SetTriggerType ( return EFI_SUCCESS;
}
-EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
+EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V2Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV2EnableInterruptSource,
(HARDWARE_INTERRUPT2_DISABLE)GicV2DisableInterruptSource,
@@ -345,8 +349,8 @@ GicV2ExitBootServicesEvent ( IN VOID *Context
)
{
- UINTN Index;
- UINT32 GicInterrupt;
+ UINTN Index;
+ UINT32 GicInterrupt;
// Disable all the interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
@@ -382,30 +386,30 @@ GicV2ExitBootServicesEvent ( **/
EFI_STATUS
GicV2DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINT32 RegOffset;
- UINTN RegShift;
- UINT32 CpuTarget;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT32 RegOffset;
+ UINTN RegShift;
+ UINT32 CpuTarget;
// Make sure the Interrupt Controller Protocol is not already installed in
// the system.
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gHardwareInterruptProtocolGuid);
mGicInterruptInterfaceBase = PcdGet64 (PcdGicInterruptInterfaceBase);
- mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
- mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
+ mGicDistributorBase = PcdGet64 (PcdGicDistributorBase);
+ mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
for (Index = 0; Index < mGicNumInterrupts; Index++) {
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
// Set Priority
RegOffset = Index / 4;
- RegShift = (Index % 4) * 8;
+ RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
~(0xff << RegShift),
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c index ff910c1755..f403bec367 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Lib.c @@ -12,7 +12,7 @@ UINTN
EFIAPI
ArmGicV2AcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase
+ IN UINTN GicInterruptInterfaceBase
)
{
// Read the Interrupt Acknowledge Register
@@ -22,8 +22,8 @@ ArmGicV2AcknowledgeInterrupt ( VOID
EFIAPI
ArmGicV2EndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
)
{
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, Source);
diff --git a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c index 08f219c104..85c2a920a5 100644 --- a/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c +++ b/ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2NonSecLib.c @@ -10,11 +10,10 @@ #include <Library/IoLib.h>
#include <Library/ArmGicLib.h>
-
VOID
EFIAPI
ArmGicV2EnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
)
{
/*
@@ -27,7 +26,7 @@ ArmGicV2EnableInterruptInterface ( VOID
EFIAPI
ArmGicV2DisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
)
{
// Disable Gic Interface
diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index fa515d1a01..b1f0cd48c7 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -12,11 +12,11 @@ #define ARM_GIC_DEFAULT_PRIORITY 0x80
-extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
-extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
+extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol;
+extern EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol;
-STATIC UINTN mGicDistributorBase;
-STATIC UINTN mGicRedistributorsBase;
+STATIC UINTN mGicDistributorBase;
+STATIC UINTN mGicRedistributorsBase;
/**
Enable interrupt source Source.
@@ -32,12 +32,12 @@ STATIC EFI_STATUS
EFIAPI
GicV3EnableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -60,12 +60,12 @@ STATIC EFI_STATUS
EFIAPI
GicV3DisableInterruptSource (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -89,13 +89,13 @@ STATIC EFI_STATUS
EFIAPI
GicV3GetInterruptSourceState (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN BOOLEAN *InterruptState
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN BOOLEAN *InterruptState
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -123,12 +123,12 @@ STATIC EFI_STATUS
EFIAPI
GicV3EndOfInterrupt (
- IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
- IN HARDWARE_INTERRUPT_SOURCE Source
+ IN EFI_HARDWARE_INTERRUPT_PROTOCOL *This,
+ IN HARDWARE_INTERRUPT_SOURCE Source
)
{
if (Source >= mGicNumInterrupts) {
- ASSERT(FALSE);
+ ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -152,8 +152,8 @@ STATIC VOID
EFIAPI
GicV3IrqInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
UINT32 GicInterrupt;
@@ -179,7 +179,7 @@ GicV3IrqInterruptHandler ( }
// The protocol instance produced by this driver
-EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
+EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptV3Protocol = {
RegisterInterruptSource,
GicV3EnableInterruptSource,
GicV3DisableInterruptSource,
@@ -206,9 +206,9 @@ GicV3GetTriggerType ( OUT EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE *TriggerType
)
{
- UINTN RegAddress;
- UINTN Config1Bit;
- EFI_STATUS Status;
+ UINTN RegAddress;
+ UINTN Config1Bit;
+ EFI_STATUS Status;
Status = GicGetDistributorIcfgBaseAndBit (
Source,
@@ -221,9 +221,9 @@ GicV3GetTriggerType ( }
if ((MmioRead32 (RegAddress) & (1 << Config1Bit)) == 0) {
- *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH;
} else {
- *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
+ *TriggerType = EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING;
}
return EFI_SUCCESS;
@@ -248,18 +248,22 @@ GicV3SetTriggerType ( IN EFI_HARDWARE_INTERRUPT2_TRIGGER_TYPE TriggerType
)
{
- UINTN RegAddress;
- UINTN Config1Bit;
- UINT32 Value;
- EFI_STATUS Status;
- BOOLEAN SourceEnabled;
-
- if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
- && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH)) {
- DEBUG ((DEBUG_ERROR, "Invalid interrupt trigger type: %d\n", \
- TriggerType));
- ASSERT (FALSE);
- return EFI_UNSUPPORTED;
+ UINTN RegAddress;
+ UINTN Config1Bit;
+ UINT32 Value;
+ EFI_STATUS Status;
+ BOOLEAN SourceEnabled;
+
+ if ( (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING)
+ && (TriggerType != EFI_HARDWARE_INTERRUPT2_TRIGGER_LEVEL_HIGH))
+ {
+ DEBUG ((
+ DEBUG_ERROR,
+ "Invalid interrupt trigger type: %d\n", \
+ TriggerType
+ ));
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
}
Status = GicGetDistributorIcfgBaseAndBit (
@@ -273,7 +277,7 @@ GicV3SetTriggerType ( }
Status = GicV3GetInterruptSourceState (
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source,
&SourceEnabled
);
@@ -290,7 +294,7 @@ GicV3SetTriggerType ( // otherwise GIC behavior is UNPREDICTABLE.
if (SourceEnabled) {
GicV3DisableInterruptSource (
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source
);
}
@@ -303,7 +307,7 @@ GicV3SetTriggerType ( // Restore interrupt state
if (SourceEnabled) {
GicV3EnableInterruptSource (
- (EFI_HARDWARE_INTERRUPT_PROTOCOL*)This,
+ (EFI_HARDWARE_INTERRUPT_PROTOCOL *)This,
Source
);
}
@@ -311,7 +315,7 @@ GicV3SetTriggerType ( return EFI_SUCCESS;
}
-EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
+EFI_HARDWARE_INTERRUPT2_PROTOCOL gHardwareInterrupt2V3Protocol = {
(HARDWARE_INTERRUPT2_REGISTER)RegisterInterruptSource,
(HARDWARE_INTERRUPT2_ENABLE)GicV3EnableInterruptSource,
(HARDWARE_INTERRUPT2_DISABLE)GicV3DisableInterruptSource,
@@ -337,7 +341,7 @@ GicV3ExitBootServicesEvent ( IN VOID *Context
)
{
- UINTN Index;
+ UINTN Index;
// Acknowledge all pending interrupts
for (Index = 0; Index < mGicNumInterrupts; Index++) {
@@ -364,14 +368,14 @@ GicV3ExitBootServicesEvent ( **/
EFI_STATUS
GicV3DxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- UINTN Index;
- UINT64 CpuTarget;
- UINT64 MpId;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINT64 CpuTarget;
+ UINT64 MpId;
// Make sure the Interrupt Controller Protocol is not already installed in
// the system.
@@ -424,14 +428,14 @@ GicV3DxeInitialize ( }
}
} else {
- MpId = ArmReadMpidr ();
+ MpId = ArmReadMpidr ();
CpuTarget = MpId &
- (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
+ (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2 | ARM_CORE_AFF3);
if ((MmioRead32 (
mGicDistributorBase + ARM_GIC_ICDDCR
- ) & ARM_GIC_ICDDCR_DS) != 0) {
-
+ ) & ARM_GIC_ICDDCR_DS) != 0)
+ {
// If the Disable Security (DS) control bit is set, we are dealing with a
// GIC that has only one security state. In this case, let's assume we are
// executing in non-secure state (which is appropriate for DXE modules)
diff --git a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c b/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c index d8625e1593..5a2866ccd8 100644 --- a/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c +++ b/ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.c @@ -18,7 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h>
-#define MAX_IO_PORT_ADDRESS 0xFFFF
+#define MAX_IO_PORT_ADDRESS 0xFFFF
//
// Handle for the CPU I/O 2 Protocol
@@ -28,7 +28,7 @@ STATIC EFI_HANDLE mHandle = NULL; //
// Lookup table for increment values based on transfer widths
//
-STATIC CONST UINT8 mInStride[] = {
+STATIC CONST UINT8 mInStride[] = {
1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32
@@ -46,7 +46,7 @@ STATIC CONST UINT8 mInStride[] = { //
// Lookup table for increment values based on transfer widths
//
-STATIC CONST UINT8 mOutStride[] = {
+STATIC CONST UINT8 mOutStride[] = {
1, // EfiCpuIoWidthUint8
2, // EfiCpuIoWidthUint16
4, // EfiCpuIoWidthUint32
@@ -117,14 +117,14 @@ CpuIoCheckParameter ( // For FIFO type, the target address won't increase during the access,
// so treat Count as 1
//
- if (Width >= EfiCpuIoWidthFifoUint8 && Width <= EfiCpuIoWidthFifoUint64) {
+ if ((Width >= EfiCpuIoWidthFifoUint8) && (Width <= EfiCpuIoWidthFifoUint64)) {
Count = 1;
}
//
// Check to see if Width is in the valid range for I/O Port operations
//
- Width = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ Width = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
if (!MmioOperation && (Width == EfiCpuIoWidthUint64)) {
return EFI_INVALID_PARAMETER;
}
@@ -161,6 +161,7 @@ CpuIoCheckParameter ( if (MaxCount < (Count - 1)) {
return EFI_UNSUPPORTED;
}
+
if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
return EFI_UNSUPPORTED;
}
@@ -240,9 +241,9 @@ CpuMemoryServiceRead ( //
// Select loop based on the width of the transfer
//
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
*Uint8Buffer = MmioRead8 ((UINTN)Address);
@@ -254,6 +255,7 @@ CpuMemoryServiceRead ( *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
}
}
+
return EFI_SUCCESS;
}
@@ -321,9 +323,9 @@ CpuMemoryServiceWrite ( //
// Select loop based on the width of the transfer
//
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
MmioWrite8 ((UINTN)Address, *Uint8Buffer);
@@ -335,6 +337,7 @@ CpuMemoryServiceWrite ( MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
}
}
+
return EFI_SUCCESS;
}
@@ -404,9 +407,9 @@ CpuIoServiceRead ( //
// Select loop based on the width of the transfer
//
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
@@ -490,9 +493,9 @@ CpuIoServiceWrite ( //
// Select loop based on the width of the transfer
//
- InStride = mInStride[Width];
- OutStride = mOutStride[Width];
- OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
+ InStride = mInStride[Width];
+ OutStride = mOutStride[Width];
+ OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH)(Width & 0x03);
for (Uint8Buffer = (UINT8 *)Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
if (OperationWidth == EfiCpuIoWidthUint8) {
@@ -510,7 +513,7 @@ CpuIoServiceWrite ( //
// CPU I/O 2 Protocol instance
//
-STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
+STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = {
{
CpuMemoryServiceRead,
CpuMemoryServiceWrite
@@ -521,7 +524,6 @@ STATIC EFI_CPU_IO2_PROTOCOL mCpuIo2 = { }
};
-
/**
The user Entry Point for module CpuIo2Dxe. The user code starts with this function.
@@ -539,12 +541,13 @@ ArmPciCpuIo2Initialize ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiCpuIo2ProtocolGuid);
Status = gBS->InstallMultipleProtocolInterfaces (
&mHandle,
- &gEfiCpuIo2ProtocolGuid, &mCpuIo2,
+ &gEfiCpuIo2ProtocolGuid,
+ &mCpuIo2,
NULL
);
ASSERT_EFI_ERROR (Status);
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h index b99ec465bd..de443015b5 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h +++ b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiBaseProtocolPrivate.h @@ -14,7 +14,7 @@ // Return values of BASE_DISCOVER_LIST_PROTOCOLS command.
typedef struct {
- UINT32 NumProtocols;
+ UINT32 NumProtocols;
// Array of four protocols in each element
// Total elements = 1 + (NumProtocols-1)/4
@@ -22,7 +22,7 @@ typedef struct { // NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
- UINT8 Protocols[1];
+ UINT8 Protocols[1];
} BASE_DISCOVER_LIST;
/** Initialize Base protocol and install protocol on a given handle.
@@ -34,7 +34,7 @@ typedef struct { **/
EFI_STATUS
ScmiBaseProtocolInit (
- IN OUT EFI_HANDLE* Handle
+ IN OUT EFI_HANDLE *Handle
);
#endif /* ARM_SCMI_BASE_PROTOCOL_PRIVATE_H_ */
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h index 43cc3bff8f..34dca852c7 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h +++ b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiClockProtocolPrivate.h @@ -16,57 +16,56 @@ // Clock rate in two 32bit words.
typedef struct {
- UINT32 Low;
- UINT32 High;
+ UINT32 Low;
+ UINT32 High;
} CLOCK_RATE_DWORD;
// Format of the returned rate array. Linear or Non-linear,.RatesFlag Bit[12]
-#define RATE_FORMAT_SHIFT 12
-#define RATE_FORMAT_MASK 0x0001
-#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \
+#define RATE_FORMAT_SHIFT 12
+#define RATE_FORMAT_MASK 0x0001
+#define RATE_FORMAT(RatesFlags) ((RatesFlags >> RATE_FORMAT_SHIFT) \
& RATE_FORMAT_MASK)
// Number of remaining rates after a call to the SCP, RatesFlag Bits[31:16]
-#define NUM_REMAIN_RATES_SHIFT 16
+#define NUM_REMAIN_RATES_SHIFT 16
#define NUM_REMAIN_RATES(RatesFlags) ((RatesFlags >> NUM_REMAIN_RATES_SHIFT))
// Number of rates that are returned by a call.to the SCP, RatesFlag Bits[11:0]
-#define NUM_RATES_MASK 0x0FFF
-#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK)
+#define NUM_RATES_MASK 0x0FFF
+#define NUM_RATES(RatesFlags) (RatesFlags & NUM_RATES_MASK)
// Return values for the CLOCK_DESCRIBER_RATE command.
typedef struct {
- UINT32 NumRatesFlags;
+ UINT32 NumRatesFlags;
// NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
- CLOCK_RATE_DWORD Rates[1];
+ CLOCK_RATE_DWORD Rates[1];
} CLOCK_DESCRIBE_RATES;
-#define CLOCK_SET_DEFAULT_FLAGS 0
+#define CLOCK_SET_DEFAULT_FLAGS 0
// Message parameters for CLOCK_RATE_SET command.
typedef struct {
- UINT32 Flags;
- UINT32 ClockId;
- CLOCK_RATE_DWORD Rate;
+ UINT32 Flags;
+ UINT32 ClockId;
+ CLOCK_RATE_DWORD Rate;
} CLOCK_RATE_SET_ATTRIBUTES;
-
// Message parameters for CLOCK_CONFIG_SET command.
typedef struct {
- UINT32 ClockId;
- UINT32 Attributes;
+ UINT32 ClockId;
+ UINT32 Attributes;
} CLOCK_CONFIG_SET_ATTRIBUTES;
// if ClockAttr Bit[0] is set then clock device is enabled.
-#define CLOCK_ENABLE_MASK 0x1
+#define CLOCK_ENABLE_MASK 0x1
#define CLOCK_ENABLED(ClockAttr) ((ClockAttr & CLOCK_ENABLE_MASK) == 1)
typedef struct {
- UINT32 Attributes;
- UINT8 ClockName[SCMI_MAX_STR_LEN];
+ UINT32 Attributes;
+ UINT8 ClockName[SCMI_MAX_STR_LEN];
} CLOCK_ATTRIBUTES;
#pragma pack()
@@ -79,7 +78,7 @@ typedef struct { **/
EFI_STATUS
ScmiClockProtocolInit (
- IN EFI_HANDLE *Handle
+ IN EFI_HANDLE *Handle
);
#endif /* ARM_SCMI_CLOCK_PROTOCOL_PRIVATE_H_ */
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h index b178aa3fdf..3c038f183d 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h +++ b/ArmPkg/Drivers/ArmScmiDxe/ArmScmiPerformanceProtocolPrivate.h @@ -15,23 +15,23 @@ #include <Protocol/ArmScmiPerformanceProtocol.h>
// Number of performance levels returned by a call to the SCP, Lvls Bits[11:0]
-#define NUM_PERF_LEVELS_MASK 0x0FFF
-#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK)
+#define NUM_PERF_LEVELS_MASK 0x0FFF
+#define NUM_PERF_LEVELS(Lvls) (Lvls & NUM_PERF_LEVELS_MASK)
// Number of performance levels remaining after a call to the SCP, Lvls Bits[31:16]
#define NUM_REMAIN_PERF_LEVELS_SHIFT 16
-#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
+#define NUM_REMAIN_PERF_LEVELS(Lvls) (Lvls >> NUM_REMAIN_PERF_LEVELS_SHIFT)
/** Return values for ScmiMessageIdPerformanceDescribeLevels command.
SCMI Spec section 4.5.2.5
**/
typedef struct {
- UINT32 NumLevels;
+ UINT32 NumLevels;
// NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
- SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels
+ SCMI_PERFORMANCE_LEVEL PerfLevel[1]; // Offset to array of performance levels
} PERF_DESCRIBE_LEVELS;
/** Initialize performance management protocol and install on a given Handle.
@@ -43,7 +43,7 @@ typedef struct { **/
EFI_STATUS
ScmiPerformanceProtocolInit (
- IN EFI_HANDLE* Handle
+ IN EFI_HANDLE *Handle
);
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_PRIVATE_H_ */
diff --git a/ArmPkg/Drivers/ArmScmiDxe/Scmi.c b/ArmPkg/Drivers/ArmScmiDxe/Scmi.c index 3793c06636..d5a1ff0be3 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/Scmi.c +++ b/ArmPkg/Drivers/ArmScmiDxe/Scmi.c @@ -29,7 +29,7 @@ **/
EFI_STATUS
ScmiCommandGetPayload (
- OUT UINT32** Payload
+ OUT UINT32 **Payload
)
{
EFI_STATUS Status;
@@ -76,7 +76,7 @@ EFI_STATUS ScmiCommandExecute (
IN SCMI_COMMAND *Command,
IN OUT UINT32 *PayloadLength,
- OUT UINT32 **ReturnValues OPTIONAL
+ OUT UINT32 **ReturnValues OPTIONAL
)
{
EFI_STATUS Status;
@@ -121,10 +121,12 @@ ScmiCommandExecute ( return EFI_DEVICE_ERROR;
}
- Response = (SCMI_MESSAGE_RESPONSE*)MtlGetChannelPayload (Channel);
+ Response = (SCMI_MESSAGE_RESPONSE *)MtlGetChannelPayload (Channel);
if (Response->Status != ScmiSuccess) {
- DEBUG ((DEBUG_ERROR, "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
+ DEBUG ((
+ DEBUG_ERROR,
+ "SCMI error: ProtocolId = 0x%x, MessageId = 0x%x, error = %d\n",
Command->ProtocolId,
Command->MessageId,
Response->Status
@@ -163,7 +165,7 @@ ScmiProtocolDiscoveryCommon ( SCMI_COMMAND Command;
UINT32 PayloadLength;
- PayloadLength = 0;
+ PayloadLength = 0;
Command.ProtocolId = ProtocolId;
Command.MessageId = MessageId;
@@ -190,13 +192,13 @@ ScmiGetProtocolVersion ( OUT UINT32 *Version
)
{
- EFI_STATUS Status;
- UINT32 *ProtocolVersion;
+ EFI_STATUS Status;
+ UINT32 *ProtocolVersion;
Status = ScmiProtocolDiscoveryCommon (
ProtocolId,
ScmiMessageIdProtocolVersion,
- (UINT32**)&ProtocolVersion
+ (UINT32 **)&ProtocolVersion
);
if (EFI_ERROR (Status)) {
return Status;
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c b/ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c index 2c6206be93..6ab2922065 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c +++ b/ArmPkg/Drivers/ArmScmiDxe/ScmiBaseProtocol.c @@ -106,9 +106,9 @@ BaseDiscoverVendorDetails ( }
AsciiStrCpyS (
- (CHAR8*)VendorIdentifier,
+ (CHAR8 *)VendorIdentifier,
SCMI_MAX_STR_LEN,
- (CONST CHAR8*)ReturnValues
+ (CONST CHAR8 *)ReturnValues
);
return EFI_SUCCESS;
@@ -256,7 +256,6 @@ BaseDiscoverListProtocols ( Skip = 0;
while (Skip < TotalProtocols) {
-
*MessageParams = Skip;
// Note PayloadLength is a IN/OUT parameter.
@@ -265,7 +264,7 @@ BaseDiscoverListProtocols ( Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
- (UINT32**)&DiscoverList
+ (UINT32 **)&DiscoverList
);
if (EFI_ERROR (Status)) {
return Status;
@@ -282,7 +281,7 @@ BaseDiscoverListProtocols ( }
// Instance of the SCMI Base protocol.
-STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {
+STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = {
BaseGetVersion,
BaseGetTotalProtocols,
BaseDiscoverVendor,
@@ -300,7 +299,7 @@ STATIC CONST SCMI_BASE_PROTOCOL BaseProtocol = { **/
EFI_STATUS
ScmiBaseProtocolInit (
- IN OUT EFI_HANDLE* Handle
+ IN OUT EFI_HANDLE *Handle
)
{
return gBS->InstallMultipleProtocolInterfaces (
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c b/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c index cc223d6720..12a7e6df5d 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c +++ b/ArmPkg/Drivers/ArmScmiDxe/ScmiClockProtocol.c @@ -28,11 +28,11 @@ STATIC
UINT64
ConvertTo64Bit (
- IN UINT32 Low,
- IN UINT32 High
+ IN UINT32 Low,
+ IN UINT32 High
)
{
- return (Low | ((UINT64)High << 32));
+ return (Low | ((UINT64)High << 32));
}
/** Return version of the clock management protocol supported by SCP firmware.
@@ -74,7 +74,7 @@ ClockGetTotalClocks ( )
{
EFI_STATUS Status;
- UINT32 *ReturnValues;
+ UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes (ScmiProtocolIdClock, &ReturnValues);
if (EFI_ERROR (Status)) {
@@ -108,12 +108,12 @@ ClockGetClockAttributes ( OUT CHAR8 *ClockAsciiName
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- UINT32 *MessageParams;
- CLOCK_ATTRIBUTES *ClockAttributes;
- SCMI_COMMAND Cmd;
- UINT32 PayloadLength;
+ UINT32 *MessageParams;
+ CLOCK_ATTRIBUTES *ClockAttributes;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {
@@ -130,18 +130,19 @@ ClockGetClockAttributes ( Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
- (UINT32**)&ClockAttributes
+ (UINT32 **)&ClockAttributes
);
if (EFI_ERROR (Status)) {
return Status;
}
- // TRUE if bit 0 of ClockAttributes->Attributes is set.
+
+ // TRUE if bit 0 of ClockAttributes->Attributes is set.
*Enabled = CLOCK_ENABLED (ClockAttributes->Attributes);
AsciiStrCpyS (
ClockAsciiName,
SCMI_MAX_STR_LEN,
- (CONST CHAR8*)ClockAttributes->ClockName
+ (CONST CHAR8 *)ClockAttributes->ClockName
);
return EFI_SUCCESS;
@@ -174,29 +175,29 @@ STATIC EFI_STATUS
ClockDescribeRates (
IN SCMI_CLOCK_PROTOCOL *This,
- IN UINT32 ClockId,
+ IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format,
OUT UINT32 *TotalRates,
IN OUT UINT32 *RateArraySize,
OUT SCMI_CLOCK_RATE *RateArray
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- UINT32 PayloadLength;
- SCMI_COMMAND Cmd;
- UINT32 *MessageParams;
- CLOCK_DESCRIBE_RATES *DescribeRates;
- CLOCK_RATE_DWORD *Rate;
+ UINT32 PayloadLength;
+ SCMI_COMMAND Cmd;
+ UINT32 *MessageParams;
+ CLOCK_DESCRIBE_RATES *DescribeRates;
+ CLOCK_RATE_DWORD *Rate;
- UINT32 RequiredArraySize;
- UINT32 RateIndex;
- UINT32 RateNo;
- UINT32 RateOffset;
+ UINT32 RequiredArraySize;
+ UINT32 RateIndex;
+ UINT32 RateNo;
+ UINT32 RateOffset;
- *TotalRates = 0;
+ *TotalRates = 0;
RequiredArraySize = 0;
- RateIndex = 0;
+ RateIndex = 0;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {
@@ -206,20 +207,19 @@ ClockDescribeRates ( Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockDescribeRates;
- *MessageParams++ = ClockId;
+ *MessageParams++ = ClockId;
do {
-
*MessageParams = RateIndex;
// Set Payload length, note PayloadLength is a IN/OUT parameter.
- PayloadLength = sizeof (ClockId) + sizeof (RateIndex);
+ PayloadLength = sizeof (ClockId) + sizeof (RateIndex);
// Execute and wait for response on a SCMI channel.
Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
- (UINT32**)&DescribeRates
+ (UINT32 **)&DescribeRates
);
if (EFI_ERROR (Status)) {
return Status;
@@ -237,10 +237,10 @@ ClockDescribeRates ( + NUM_REMAIN_RATES (DescribeRates->NumRatesFlags);
if (*Format == ScmiClockRateFormatDiscrete) {
- RequiredArraySize = (*TotalRates) * sizeof (UINT64);
+ RequiredArraySize = (*TotalRates) * sizeof (UINT64);
} else {
- // We need to return triplet of 64 bit value for each rate
- RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64);
+ // We need to return triplet of 64 bit value for each rate
+ RequiredArraySize = (*TotalRates) * 3 * sizeof (UINT64);
}
if (RequiredArraySize > (*RateArraySize)) {
@@ -262,7 +262,7 @@ ClockDescribeRates ( for (RateNo = 0; RateNo < NUM_RATES (DescribeRates->NumRatesFlags); RateNo++) {
// Linear clock rates from minimum to maximum in steps
// Minimum clock rate.
- Rate = &DescribeRates->Rates[RateOffset++];
+ Rate = &DescribeRates->Rates[RateOffset++];
RateArray[RateIndex].ContinuousRate.Min =
ConvertTo64Bit (Rate->Low, Rate->High);
@@ -304,13 +304,13 @@ ClockRateGet ( OUT UINT64 *Rate
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
UINT32 *MessageParams;
CLOCK_RATE_DWORD *ClockRate;
SCMI_COMMAND Cmd;
- UINT32 PayloadLength;
+ UINT32 PayloadLength;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {
@@ -318,10 +318,10 @@ ClockRateGet ( }
// Fill arguments for clock protocol command.
- *MessageParams = ClockId;
+ *MessageParams = ClockId;
- Cmd.ProtocolId = ScmiProtocolIdClock;
- Cmd.MessageId = ScmiMessageIdClockRateGet;
+ Cmd.ProtocolId = ScmiProtocolIdClock;
+ Cmd.MessageId = ScmiMessageIdClockRateGet;
PayloadLength = sizeof (ClockId);
@@ -329,7 +329,7 @@ ClockRateGet ( Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
- (UINT32**)&ClockRate
+ (UINT32 **)&ClockRate
);
if (EFI_ERROR (Status)) {
return Status;
@@ -358,21 +358,21 @@ ClockRateSet ( IN UINT64 Rate
)
{
- EFI_STATUS Status;
- CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes;
- SCMI_COMMAND Cmd;
- UINT32 PayloadLength;
+ EFI_STATUS Status;
+ CLOCK_RATE_SET_ATTRIBUTES *ClockRateSetAttributes;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
- Status = ScmiCommandGetPayload ((UINT32**)&ClockRateSetAttributes);
+ Status = ScmiCommandGetPayload ((UINT32 **)&ClockRateSetAttributes);
if (EFI_ERROR (Status)) {
return Status;
}
// Fill arguments for clock protocol command.
- ClockRateSetAttributes->ClockId = ClockId;
- ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS;
- ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
- ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
+ ClockRateSetAttributes->ClockId = ClockId;
+ ClockRateSetAttributes->Flags = CLOCK_SET_DEFAULT_FLAGS;
+ ClockRateSetAttributes->Rate.Low = (UINT32)Rate;
+ ClockRateSetAttributes->Rate.High = (UINT32)(Rate >> 32);
Cmd.ProtocolId = ScmiProtocolIdClock;
Cmd.MessageId = ScmiMessageIdClockRateSet;
@@ -402,17 +402,17 @@ ClockRateSet ( STATIC
EFI_STATUS
ClockEnable (
- IN SCMI_CLOCK2_PROTOCOL *This,
- IN UINT32 ClockId,
- IN BOOLEAN Enable
+ IN SCMI_CLOCK2_PROTOCOL *This,
+ IN UINT32 ClockId,
+ IN BOOLEAN Enable
)
{
- EFI_STATUS Status;
- CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes;
- SCMI_COMMAND Cmd;
- UINT32 PayloadLength;
+ EFI_STATUS Status;
+ CLOCK_CONFIG_SET_ATTRIBUTES *ClockConfigSetAttributes;
+ SCMI_COMMAND Cmd;
+ UINT32 PayloadLength;
- Status = ScmiCommandGetPayload ((UINT32**)&ClockConfigSetAttributes);
+ Status = ScmiCommandGetPayload ((UINT32 **)&ClockConfigSetAttributes);
if (EFI_ERROR (Status)) {
return Status;
}
@@ -437,17 +437,17 @@ ClockEnable ( }
// Instance of the SCMI clock management protocol.
-STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = {
+STATIC CONST SCMI_CLOCK_PROTOCOL ScmiClockProtocol = {
ClockGetVersion,
ClockGetTotalClocks,
ClockGetClockAttributes,
ClockDescribeRates,
ClockRateGet,
ClockRateSet
- };
+};
// Instance of the SCMI clock management protocol.
-STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
+STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = {
(SCMI_CLOCK2_GET_VERSION)ClockGetVersion,
(SCMI_CLOCK2_GET_TOTAL_CLOCKS)ClockGetTotalClocks,
(SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)ClockGetClockAttributes,
@@ -456,7 +456,7 @@ STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = { (SCMI_CLOCK2_RATE_SET)ClockRateSet,
SCMI_CLOCK2_PROTOCOL_VERSION,
ClockEnable
- };
+};
/** Initialize clock management protocol and install protocol on a given handle.
@@ -466,7 +466,7 @@ STATIC CONST SCMI_CLOCK2_PROTOCOL ScmiClock2Protocol = { **/
EFI_STATUS
ScmiClockProtocolInit (
- IN EFI_HANDLE* Handle
+ IN EFI_HANDLE *Handle
)
{
return gBS->InstallMultipleProtocolInterfaces (
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c b/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c index fb4e79aa36..1fc448b9bf 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c +++ b/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.c @@ -23,10 +23,10 @@ #include "ScmiDxe.h"
#include "ScmiPrivate.h"
-STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
- { ScmiProtocolIdBase, ScmiBaseProtocolInit },
+STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = {
+ { ScmiProtocolIdBase, ScmiBaseProtocolInit },
{ ScmiProtocolIdPerformance, ScmiPerformanceProtocolInit },
- { ScmiProtocolIdClock, ScmiClockProtocolInit }
+ { ScmiProtocolIdClock, ScmiClockProtocolInit }
};
/** ARM SCMI driver entry point function.
@@ -47,8 +47,8 @@ STATIC CONST SCMI_PROTOCOL_ENTRY Protocols[] = { EFI_STATUS
EFIAPI
ArmScmiDxeEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
@@ -72,7 +72,7 @@ ArmScmiDxeEntryPoint ( Status = gBS->LocateProtocol (
&gArmScmiBaseProtocolGuid,
NULL,
- (VOID**)&BaseProtocol
+ (VOID **)&BaseProtocol
);
if (EFI_ERROR (Status)) {
ASSERT (FALSE);
@@ -88,7 +88,8 @@ ArmScmiDxeEntryPoint ( // Accept any version between SCMI v1.0 and SCMI v2.0
if ((Version < BASE_PROTOCOL_VERSION_V1) ||
- (Version > BASE_PROTOCOL_VERSION_V2)) {
+ (Version > BASE_PROTOCOL_VERSION_V2))
+ {
ASSERT (FALSE);
return EFI_UNSUPPORTED;
}
@@ -96,7 +97,7 @@ ArmScmiDxeEntryPoint ( // Apart from Base protocol, SCMI may implement various other protocols,
// query total protocols implemented by the SCP firmware.
NumProtocols = 0;
- Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols);
+ Status = BaseProtocol->GetTotalProtocols (BaseProtocol, &NumProtocols);
if (EFI_ERROR (Status)) {
ASSERT (FALSE);
return Status;
@@ -109,7 +110,7 @@ ArmScmiDxeEntryPoint ( Status = gBS->AllocatePool (
EfiBootServicesData,
SupportedListSize,
- (VOID**)&SupportedList
+ (VOID **)&SupportedList
);
if (EFI_ERROR (Status)) {
ASSERT (FALSE);
@@ -130,7 +131,8 @@ ArmScmiDxeEntryPoint ( // Install supported protocol on ImageHandle.
for (ProtocolIndex = 1; ProtocolIndex < ARRAY_SIZE (Protocols);
- ProtocolIndex++) {
+ ProtocolIndex++)
+ {
for (Index = 0; Index < NumProtocols; Index++) {
if (Protocols[ProtocolIndex].Id == SupportedList[Index]) {
Status = Protocols[ProtocolIndex].InitFn (&ImageHandle);
@@ -138,6 +140,7 @@ ArmScmiDxeEntryPoint ( ASSERT_EFI_ERROR (Status);
return Status;
}
+
break;
}
}
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h b/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h index 28242aab1c..a6f87a34d0 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h +++ b/ArmPkg/Drivers/ArmScmiDxe/ScmiDxe.h @@ -8,12 +8,13 @@ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
DEN0056A_System_Control_and_Management_Interface.pdf
**/
+
#ifndef SCMI_DXE_H_
#define SCMI_DXE_H_
#include "ScmiPrivate.h"
-#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN
+#define MAX_VENDOR_LEN SCMI_MAX_STR_LEN
/** Pointer to protocol initialization function.
@@ -29,8 +30,8 @@ EFI_STATUS );
typedef struct {
- SCMI_PROTOCOL_ID Id; // Protocol Id.
- SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function.
+ SCMI_PROTOCOL_ID Id; // Protocol Id.
+ SCMI_PROTOCOL_INIT_FXN InitFn; // Protocol init function.
} SCMI_PROTOCOL_ENTRY;
#endif /* SCMI_DXE_H_ */
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c b/ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c index 684ed713d5..0f89808fbd 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c +++ b/ArmPkg/Drivers/ArmScmiDxe/ScmiPerformanceProtocol.c @@ -51,12 +51,12 @@ PerformanceGetVersion ( STATIC
EFI_STATUS
PerformanceGetAttributes (
- IN SCMI_PERFORMANCE_PROTOCOL *This,
- OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
)
{
EFI_STATUS Status;
- UINT32* ReturnValues;
+ UINT32 *ReturnValues;
Status = ScmiGetProtocolAttributes (
ScmiProtocolIdPerformance,
@@ -90,7 +90,7 @@ STATIC EFI_STATUS
PerformanceDomainAttributes (
IN SCMI_PERFORMANCE_PROTOCOL *This,
- IN UINT32 DomainId,
+ IN UINT32 DomainId,
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
)
{
@@ -160,21 +160,21 @@ PerformanceDescribeLevels ( EFI_STATUS Status;
UINT32 PayloadLength;
SCMI_COMMAND Cmd;
- UINT32* MessageParams;
+ UINT32 *MessageParams;
UINT32 LevelIndex;
UINT32 RequiredSize;
UINT32 LevelNo;
UINT32 ReturnNumLevels;
UINT32 ReturnRemainNumLevels;
- PERF_DESCRIBE_LEVELS *Levels;
+ PERF_DESCRIBE_LEVELS *Levels;
Status = ScmiCommandGetPayload (&MessageParams);
if (EFI_ERROR (Status)) {
return Status;
}
- LevelIndex = 0;
+ LevelIndex = 0;
RequiredSize = 0;
*MessageParams++ = DomainId;
@@ -183,7 +183,6 @@ PerformanceDescribeLevels ( Cmd.MessageId = ScmiMessageIdPerformanceDescribeLevels;
do {
-
*MessageParams = LevelIndex;
// Note, PayloadLength is an IN/OUT parameter.
@@ -192,13 +191,13 @@ PerformanceDescribeLevels ( Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
- (UINT32**)&Levels
+ (UINT32 **)&Levels
);
if (EFI_ERROR (Status)) {
return Status;
}
- ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels);
+ ReturnNumLevels = NUM_PERF_LEVELS (Levels->NumLevels);
ReturnRemainNumLevels = NUM_REMAIN_PERF_LEVELS (Levels->NumLevels);
if (RequiredSize == 0) {
@@ -213,13 +212,12 @@ PerformanceDescribeLevels ( }
for (LevelNo = 0; LevelNo < ReturnNumLevels; LevelNo++) {
- CopyMem (
- &LevelArray[LevelIndex++],
- &Levels->PerfLevel[LevelNo],
- sizeof (SCMI_PERFORMANCE_LEVEL)
- );
+ CopyMem (
+ &LevelArray[LevelIndex++],
+ &Levels->PerfLevel[LevelNo],
+ sizeof (SCMI_PERFORMANCE_LEVEL)
+ );
}
-
} while (ReturnRemainNumLevels != 0);
*LevelArraySize = RequiredSize;
@@ -239,9 +237,9 @@ PerformanceDescribeLevels ( **/
EFI_STATUS
PerformanceLimitsSet (
- IN SCMI_PERFORMANCE_PROTOCOL *This,
- IN UINT32 DomainId,
- IN SCMI_PERFORMANCE_LIMITS *Limits
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ IN SCMI_PERFORMANCE_LIMITS *Limits
)
{
EFI_STATUS Status;
@@ -285,9 +283,9 @@ PerformanceLimitsSet ( **/
EFI_STATUS
PerformanceLimitsGet (
- SCMI_PERFORMANCE_PROTOCOL *This,
- UINT32 DomainId,
- SCMI_PERFORMANCE_LIMITS *Limits
+ SCMI_PERFORMANCE_PROTOCOL *This,
+ UINT32 DomainId,
+ SCMI_PERFORMANCE_LIMITS *Limits
)
{
EFI_STATUS Status;
@@ -312,7 +310,7 @@ PerformanceLimitsGet ( Status = ScmiCommandExecute (
&Cmd,
&PayloadLength,
- (UINT32**)&ReturnValues
+ (UINT32 **)&ReturnValues
);
if (EFI_ERROR (Status)) {
return Status;
@@ -336,9 +334,9 @@ PerformanceLimitsGet ( **/
EFI_STATUS
PerformanceLevelSet (
- IN SCMI_PERFORMANCE_PROTOCOL *This,
- IN UINT32 DomainId,
- IN UINT32 Level
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ IN UINT32 Level
)
{
EFI_STATUS Status;
@@ -381,9 +379,9 @@ PerformanceLevelSet ( **/
EFI_STATUS
PerformanceLevelGet (
- IN SCMI_PERFORMANCE_PROTOCOL *This,
- IN UINT32 DomainId,
- OUT UINT32 *Level
+ IN SCMI_PERFORMANCE_PROTOCOL *This,
+ IN UINT32 DomainId,
+ OUT UINT32 *Level
)
{
EFI_STATUS Status;
@@ -419,7 +417,7 @@ PerformanceLevelGet ( }
// Instance of the SCMI performance management protocol.
-STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {
+STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = {
PerformanceGetVersion,
PerformanceGetAttributes,
PerformanceDomainAttributes,
@@ -439,7 +437,7 @@ STATIC CONST SCMI_PERFORMANCE_PROTOCOL PerformanceProtocol = { **/
EFI_STATUS
ScmiPerformanceProtocolInit (
- IN EFI_HANDLE* Handle
+ IN EFI_HANDLE *Handle
)
{
return gBS->InstallMultipleProtocolInterfaces (
diff --git a/ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h b/ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h index e56c9e0dc3..c041d1ed0b 100644 --- a/ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h +++ b/ArmPkg/Drivers/ArmScmiDxe/ScmiPrivate.h @@ -8,6 +8,7 @@ http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/
DEN0056A_System_Control_and_Management_Interface.pdf
**/
+
#ifndef SCMI_PRIVATE_H_
#define SCMI_PRIVATE_H_
@@ -52,21 +53,21 @@ typedef enum { // Not defined in SCMI specification but will help to identify a message.
typedef struct {
- SCMI_PROTOCOL_ID ProtocolId;
- UINT32 MessageId;
+ SCMI_PROTOCOL_ID ProtocolId;
+ UINT32 MessageId;
} SCMI_COMMAND;
#pragma pack(1)
// Response to a SCMI command.
typedef struct {
- INT32 Status;
- UINT32 ReturnValues[];
+ INT32 Status;
+ UINT32 ReturnValues[];
} SCMI_MESSAGE_RESPONSE;
// Message header. MsgId[7:0], MsgType[9:8], ProtocolId[17:10]
-#define MESSAGE_TYPE_SHIFT 8
-#define PROTOCOL_ID_SHIFT 10
+#define MESSAGE_TYPE_SHIFT 8
+#define PROTOCOL_ID_SHIFT 10
#define SCMI_MESSAGE_HEADER(MsgId, MsgType, ProtocolId) ( \
MsgType << MESSAGE_TYPE_SHIFT | \
ProtocolId << PROTOCOL_ID_SHIFT | \
@@ -74,7 +75,7 @@ typedef struct { )
// SCMI message header.
typedef struct {
- UINT32 MessageHeader;
+ UINT32 MessageHeader;
} SCMI_MESSAGE_HEADER;
#pragma pack()
@@ -89,7 +90,7 @@ typedef struct { **/
EFI_STATUS
ScmiCommandGetPayload (
- OUT UINT32** Payload
+ OUT UINT32 **Payload
);
/** Execute a SCMI command and receive a response.
@@ -115,7 +116,7 @@ EFI_STATUS ScmiCommandExecute (
IN SCMI_COMMAND *Command,
IN OUT UINT32 *PayloadLength,
- OUT UINT32 **ReturnValues OPTIONAL
+ OUT UINT32 **ReturnValues OPTIONAL
);
/** Return protocol version from SCP for a given protocol ID.
diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c index 838803aa9b..8997b7f61f 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c @@ -13,7 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/MemoryAllocationLib.h>
#include "CpuDxe.h"
-#define INVALID_ENTRY ((UINT32)~0)
+#define INVALID_ENTRY ((UINT32)~0)
#define MIN_T0SZ 16
#define BITS_PER_LEVEL 9
@@ -21,49 +21,52 @@ SPDX-License-Identifier: BSD-2-Clause-Patent STATIC
VOID
GetRootTranslationTableInfo (
- IN UINTN T0SZ,
- OUT UINTN *RootTableLevel,
- OUT UINTN *RootTableEntryCount
+ IN UINTN T0SZ,
+ OUT UINTN *RootTableLevel,
+ OUT UINTN *RootTableEntryCount
)
{
- *RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
- *RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
+ *RootTableLevel = (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
+ *RootTableEntryCount = TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
}
STATIC
UINT64
PageAttributeToGcdAttribute (
- IN UINT64 PageAttributes
+ IN UINT64 PageAttributes
)
{
UINT64 GcdAttributes;
switch (PageAttributes & TT_ATTR_INDX_MASK) {
- case TT_ATTR_INDX_DEVICE_MEMORY:
- GcdAttributes = EFI_MEMORY_UC;
- break;
- case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
- GcdAttributes = EFI_MEMORY_WC;
- break;
- case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
- GcdAttributes = EFI_MEMORY_WT;
- break;
- case TT_ATTR_INDX_MEMORY_WRITE_BACK:
- GcdAttributes = EFI_MEMORY_WB;
- break;
- default:
- DEBUG ((DEBUG_ERROR,
- "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",
- PageAttributes));
- ASSERT (0);
- // The Global Coherency Domain (GCD) value is defined as a bit set.
- // Returning 0 means no attribute has been set.
- GcdAttributes = 0;
+ case TT_ATTR_INDX_DEVICE_MEMORY:
+ GcdAttributes = EFI_MEMORY_UC;
+ break;
+ case TT_ATTR_INDX_MEMORY_NON_CACHEABLE:
+ GcdAttributes = EFI_MEMORY_WC;
+ break;
+ case TT_ATTR_INDX_MEMORY_WRITE_THROUGH:
+ GcdAttributes = EFI_MEMORY_WT;
+ break;
+ case TT_ATTR_INDX_MEMORY_WRITE_BACK:
+ GcdAttributes = EFI_MEMORY_WB;
+ break;
+ default:
+ DEBUG ((
+ DEBUG_ERROR,
+ "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n",
+ PageAttributes
+ ));
+ ASSERT (0);
+ // The Global Coherency Domain (GCD) value is defined as a bit set.
+ // Returning 0 means no attribute has been set.
+ GcdAttributes = 0;
}
// Determine protection attributes
if (((PageAttributes & TT_AP_MASK) == TT_AP_NO_RO) ||
- ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO)) {
+ ((PageAttributes & TT_AP_MASK) == TT_AP_RO_RO))
+ {
// Read only cases map to write-protect
GcdAttributes |= EFI_MEMORY_RO;
}
@@ -80,19 +83,19 @@ STATIC UINT64
GetFirstPageAttribute (
IN UINT64 *FirstLevelTableAddress,
- IN UINTN TableLevel
+ IN UINTN TableLevel
)
{
- UINT64 FirstEntry;
+ UINT64 FirstEntry;
// Get the first entry of the table
FirstEntry = *FirstLevelTableAddress;
- if ((TableLevel != 3) && (FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
+ if ((TableLevel != 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY)) {
// Only valid for Levels 0, 1 and 2
// Get the attribute of the subsequent table
- return GetFirstPageAttribute ((UINT64*)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);
+ return GetFirstPageAttribute ((UINT64 *)(FirstEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE), TableLevel + 1);
} else if (((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) ||
((TableLevel == 3) && ((FirstEntry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3)))
{
@@ -105,25 +108,25 @@ GetFirstPageAttribute ( STATIC
UINT64
GetNextEntryAttribute (
- IN UINT64 *TableAddress,
+ IN UINT64 *TableAddress,
IN UINTN EntryCount,
IN UINTN TableLevel,
IN UINT64 BaseAddress,
- IN OUT UINT32 *PrevEntryAttribute,
- IN OUT UINT64 *StartGcdRegion
+ IN OUT UINT32 *PrevEntryAttribute,
+ IN OUT UINT64 *StartGcdRegion
)
{
- UINTN Index;
- UINT64 Entry;
- UINT32 EntryAttribute;
- UINT32 EntryType;
- EFI_STATUS Status;
- UINTN NumberOfDescriptors;
+ UINTN Index;
+ UINT64 Entry;
+ UINT32 EntryAttribute;
+ UINT32 EntryType;
+ EFI_STATUS Status;
+ UINTN NumberOfDescriptors;
EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
// Get the memory space map from GCD
MemorySpaceMap = NULL;
- Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status);
// We cannot get more than 3-level page table
@@ -132,24 +135,28 @@ GetNextEntryAttribute ( // While the top level table might not contain TT_ENTRY_COUNT entries;
// the subsequent ones should be filled up
for (Index = 0; Index < EntryCount; Index++) {
- Entry = TableAddress[Index];
- EntryType = Entry & TT_TYPE_MASK;
+ Entry = TableAddress[Index];
+ EntryType = Entry & TT_TYPE_MASK;
EntryAttribute = Entry & TT_ATTR_INDX_MASK;
// If Entry is a Table Descriptor type entry then go through the sub-level table
if ((EntryType == TT_TYPE_BLOCK_ENTRY) ||
- ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3))) {
+ ((TableLevel == 3) && (EntryType == TT_TYPE_BLOCK_ENTRY_LEVEL3)))
+ {
if ((*PrevEntryAttribute == INVALID_ENTRY) || (EntryAttribute != *PrevEntryAttribute)) {
if (*PrevEntryAttribute != INVALID_ENTRY) {
// Update GCD with the last region
- SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
- *StartGcdRegion,
- (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,
- PageAttributeToGcdAttribute (*PrevEntryAttribute));
+ SetGcdMemorySpaceAttributes (
+ MemorySpaceMap,
+ NumberOfDescriptors,
+ *StartGcdRegion,
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))) - *StartGcdRegion,
+ PageAttributeToGcdAttribute (*PrevEntryAttribute)
+ );
}
// Start of the new region
- *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));
+ *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel));
*PrevEntryAttribute = EntryAttribute;
} else {
continue;
@@ -159,20 +166,27 @@ GetNextEntryAttribute ( ASSERT (TableLevel < 3);
// Increase the level number and scan the sub-level table
- GetNextEntryAttribute ((UINT64*)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE),
- TT_ENTRY_COUNT, TableLevel + 1,
- (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))),
- PrevEntryAttribute, StartGcdRegion);
+ GetNextEntryAttribute (
+ (UINT64 *)(Entry & TT_ADDRESS_MASK_DESCRIPTION_TABLE),
+ TT_ENTRY_COUNT,
+ TableLevel + 1,
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))),
+ PrevEntryAttribute,
+ StartGcdRegion
+ );
} else {
if (*PrevEntryAttribute != INVALID_ENTRY) {
// Update GCD with the last region
- SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
- *StartGcdRegion,
- (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel))) - *StartGcdRegion,
- PageAttributeToGcdAttribute (*PrevEntryAttribute));
+ SetGcdMemorySpaceAttributes (
+ MemorySpaceMap,
+ NumberOfDescriptors,
+ *StartGcdRegion,
+ (BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel))) - *StartGcdRegion,
+ PageAttributeToGcdAttribute (*PrevEntryAttribute)
+ );
// Start of the new region
- *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL(TableLevel));
+ *StartGcdRegion = BaseAddress + (Index * TT_ADDRESS_AT_LEVEL (TableLevel));
*PrevEntryAttribute = INVALID_ENTRY;
}
}
@@ -180,25 +194,25 @@ GetNextEntryAttribute ( FreePool (MemorySpaceMap);
- return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL(TableLevel));
+ return BaseAddress + (EntryCount * TT_ADDRESS_AT_LEVEL (TableLevel));
}
EFI_STATUS
SyncCacheConfig (
- IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
)
{
- EFI_STATUS Status;
- UINT32 PageAttribute;
- UINT64 *FirstLevelTableAddress;
- UINTN TableLevel;
- UINTN TableCount;
- UINTN NumberOfDescriptors;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
- UINTN Tcr;
- UINTN T0SZ;
- UINT64 BaseAddressGcdRegion;
- UINT64 EndAddressGcdRegion;
+ EFI_STATUS Status;
+ UINT32 PageAttribute;
+ UINT64 *FirstLevelTableAddress;
+ UINTN TableLevel;
+ UINTN TableCount;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
+ UINTN Tcr;
+ UINTN T0SZ;
+ UINT64 BaseAddressGcdRegion;
+ UINT64 EndAddressGcdRegion;
// This code assumes MMU is enabled and filed with section translations
ASSERT (ArmMmuEnabled ());
@@ -207,7 +221,7 @@ SyncCacheConfig ( // Get the memory space map from GCD
//
MemorySpaceMap = NULL;
- Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status);
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
@@ -217,7 +231,7 @@ SyncCacheConfig ( // with a way for GCD to query the CPU Arch. driver of the existing memory space attributes instead.
// Obtain page table base
- FirstLevelTableAddress = (UINT64*)(ArmGetTTBR0BaseAddress ());
+ FirstLevelTableAddress = (UINT64 *)(ArmGetTTBR0BaseAddress ());
// Get Translation Control Register value
Tcr = ArmGetTCR ();
@@ -232,17 +246,24 @@ SyncCacheConfig ( // We scan from the start of the memory map (ie: at the address 0x0)
BaseAddressGcdRegion = 0x0;
- EndAddressGcdRegion = GetNextEntryAttribute (FirstLevelTableAddress,
- TableCount, TableLevel,
- BaseAddressGcdRegion,
- &PageAttribute, &BaseAddressGcdRegion);
+ EndAddressGcdRegion = GetNextEntryAttribute (
+ FirstLevelTableAddress,
+ TableCount,
+ TableLevel,
+ BaseAddressGcdRegion,
+ &PageAttribute,
+ &BaseAddressGcdRegion
+ );
// Update GCD with the last region if valid
if (PageAttribute != INVALID_ENTRY) {
- SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors,
- BaseAddressGcdRegion,
- EndAddressGcdRegion - BaseAddressGcdRegion,
- PageAttributeToGcdAttribute (PageAttribute));
+ SetGcdMemorySpaceAttributes (
+ MemorySpaceMap,
+ NumberOfDescriptors,
+ BaseAddressGcdRegion,
+ EndAddressGcdRegion - BaseAddressGcdRegion,
+ PageAttributeToGcdAttribute (PageAttribute)
+ );
}
FreePool (MemorySpaceMap);
@@ -252,30 +273,31 @@ SyncCacheConfig ( UINT64
EfiAttributeToArmAttribute (
- IN UINT64 EfiAttributes
+ IN UINT64 EfiAttributes
)
{
- UINT64 ArmAttributes;
+ UINT64 ArmAttributes;
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {
- case EFI_MEMORY_UC:
- if (ArmReadCurrentEL () == AARCH64_EL2) {
- ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
- } else {
- ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
- }
- break;
- case EFI_MEMORY_WC:
- ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
- break;
- case EFI_MEMORY_WT:
- ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
- break;
- case EFI_MEMORY_WB:
- ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
- break;
- default:
- ArmAttributes = TT_ATTR_INDX_MASK;
+ case EFI_MEMORY_UC:
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
+ } else {
+ ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
+ }
+
+ break;
+ case EFI_MEMORY_WC:
+ ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+ break;
+ case EFI_MEMORY_WT:
+ ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+ break;
+ case EFI_MEMORY_WB:
+ ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+ break;
+ default:
+ ArmAttributes = TT_ATTR_INDX_MASK;
}
// Set the access flag to match the block attributes
@@ -298,19 +320,19 @@ EfiAttributeToArmAttribute ( // And then the function will identify the size of the region that has the same page table attribute.
EFI_STATUS
GetMemoryRegionRec (
- IN UINT64 *TranslationTable,
- IN UINTN TableLevel,
- IN UINT64 *LastBlockEntry,
- IN OUT UINTN *BaseAddress,
- OUT UINTN *RegionLength,
- OUT UINTN *RegionAttributes
+ IN UINT64 *TranslationTable,
+ IN UINTN TableLevel,
+ IN UINT64 *LastBlockEntry,
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
)
{
- EFI_STATUS Status;
- UINT64 *NextTranslationTable;
- UINT64 *BlockEntry;
- UINT64 BlockEntryType;
- UINT64 EntryType;
+ EFI_STATUS Status;
+ UINT64 *NextTranslationTable;
+ UINT64 *BlockEntry;
+ UINT64 BlockEntryType;
+ UINT64 EntryType;
if (TableLevel != 3) {
BlockEntryType = TT_TYPE_BLOCK_ENTRY;
@@ -319,22 +341,25 @@ GetMemoryRegionRec ( }
// Find the block entry linked to the Base Address
- BlockEntry = (UINT64*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);
- EntryType = *BlockEntry & TT_TYPE_MASK;
+ BlockEntry = (UINT64 *)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable, TableLevel, *BaseAddress);
+ EntryType = *BlockEntry & TT_TYPE_MASK;
if ((TableLevel < 3) && (EntryType == TT_TYPE_TABLE_ENTRY)) {
- NextTranslationTable = (UINT64*)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
+ NextTranslationTable = (UINT64 *)(*BlockEntry & TT_ADDRESS_MASK_DESCRIPTION_TABLE);
// The entry is a page table, so we go to the next level
Status = GetMemoryRegionRec (
- NextTranslationTable, // Address of the next level page table
- TableLevel + 1, // Next Page Table level
- (UINTN*)TT_LAST_BLOCK_ADDRESS(NextTranslationTable, TT_ENTRY_COUNT),
- BaseAddress, RegionLength, RegionAttributes);
+ NextTranslationTable, // Address of the next level page table
+ TableLevel + 1, // Next Page Table level
+ (UINTN *)TT_LAST_BLOCK_ADDRESS (NextTranslationTable, TT_ENTRY_COUNT),
+ BaseAddress,
+ RegionLength,
+ RegionAttributes
+ );
// In case of 'Success', it means the end of the block region has been found into the upper
// level translation table
- if (!EFI_ERROR(Status)) {
+ if (!EFI_ERROR (Status)) {
return EFI_SUCCESS;
}
@@ -343,7 +368,7 @@ GetMemoryRegionRec ( } else if (EntryType == BlockEntryType) {
// We have found the BlockEntry attached to the address. We save its start address (the start
// address might be before the 'BaseAddress') and attributes
- *BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL(TableLevel) - 1);
+ *BaseAddress = *BaseAddress & ~(TT_ADDRESS_AT_LEVEL (TableLevel) - 1);
*RegionLength = 0;
*RegionAttributes = *BlockEntry & TT_ATTRIBUTES_MASK;
} else {
@@ -353,11 +378,12 @@ GetMemoryRegionRec ( while (BlockEntry <= LastBlockEntry) {
if ((*BlockEntry & TT_ATTRIBUTES_MASK) == *RegionAttributes) {
- *RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL(TableLevel);
+ *RegionLength = *RegionLength + TT_BLOCK_ENTRY_SIZE_AT_LEVEL (TableLevel);
} else {
// In case we have found the end of the region we return success
return EFI_SUCCESS;
}
+
BlockEntry++;
}
@@ -369,13 +395,13 @@ GetMemoryRegionRec ( EFI_STATUS
GetMemoryRegion (
- IN OUT UINTN *BaseAddress,
- OUT UINTN *RegionLength,
- OUT UINTN *RegionAttributes
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
)
{
EFI_STATUS Status;
- UINT64 *TranslationTable;
+ UINT64 *TranslationTable;
UINTN TableLevel;
UINTN EntryCount;
UINTN T0SZ;
@@ -388,9 +414,14 @@ GetMemoryRegion ( // Get the Table info from T0SZ
GetRootTranslationTableInfo (T0SZ, &TableLevel, &EntryCount);
- Status = GetMemoryRegionRec (TranslationTable, TableLevel,
- (UINTN*)TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount),
- BaseAddress, RegionLength, RegionAttributes);
+ Status = GetMemoryRegionRec (
+ TranslationTable,
+ TableLevel,
+ (UINTN *)TT_LAST_BLOCK_ADDRESS (TranslationTable, EntryCount),
+ BaseAddress,
+ RegionLength,
+ RegionAttributes
+ );
// If the region continues up to the end of the root table then GetMemoryRegionRec()
// will return EFI_NOT_FOUND
diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c index 54fad23cb4..2daf47ba6f 100644 --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c @@ -22,7 +22,7 @@ SectionToGcdAttributes ( *GcdAttributes = 0;
// determine cacheability attributes
- switch(SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
+ switch (SectionAttributes & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) {
case TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED:
*GcdAttributes |= EFI_MEMORY_UC;
break;
@@ -49,9 +49,9 @@ SectionToGcdAttributes ( }
// determine protection attributes
- switch(SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
+ switch (SectionAttributes & TT_DESCRIPTOR_SECTION_AP_MASK) {
case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write
- //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
+ // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
break;
case TT_DESCRIPTOR_SECTION_AP_RW_NO:
@@ -86,7 +86,7 @@ PageToGcdAttributes ( *GcdAttributes = 0;
// determine cacheability attributes
- switch(PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {
+ switch (PageAttributes & TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK) {
case TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED:
*GcdAttributes |= EFI_MEMORY_UC;
break;
@@ -113,9 +113,9 @@ PageToGcdAttributes ( }
// determine protection attributes
- switch(PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
+ switch (PageAttributes & TT_DESCRIPTOR_PAGE_AP_MASK) {
case TT_DESCRIPTOR_PAGE_AP_NO_NO: // no read, no write
- //*GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
+ // *GcdAttributes |= EFI_MEMORY_RO | EFI_MEMORY_RP;
break;
case TT_DESCRIPTOR_PAGE_AP_RW_NO:
@@ -143,43 +143,43 @@ PageToGcdAttributes ( EFI_STATUS
SyncCacheConfigPage (
- IN UINT32 SectionIndex,
- IN UINT32 FirstLevelDescriptor,
- IN UINTN NumberOfDescriptors,
- IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
- IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,
- IN OUT UINT64 *NextRegionLength,
- IN OUT UINT32 *NextSectionAttributes
+ IN UINT32 SectionIndex,
+ IN UINT32 FirstLevelDescriptor,
+ IN UINTN NumberOfDescriptors,
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
+ IN OUT EFI_PHYSICAL_ADDRESS *NextRegionBase,
+ IN OUT UINT64 *NextRegionLength,
+ IN OUT UINT32 *NextSectionAttributes
)
{
- EFI_STATUS Status;
- UINT32 i;
- volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
- UINT32 NextPageAttributes;
- UINT32 PageAttributes;
- UINT32 BaseAddress;
- UINT64 GcdAttributes;
+ EFI_STATUS Status;
+ UINT32 i;
+ volatile ARM_PAGE_TABLE_ENTRY *SecondLevelTable;
+ UINT32 NextPageAttributes;
+ UINT32 PageAttributes;
+ UINT32 BaseAddress;
+ UINT64 GcdAttributes;
// Get the Base Address from FirstLevelDescriptor;
- BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
+ BaseAddress = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (SectionIndex << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
// Convert SectionAttributes into PageAttributes
NextPageAttributes =
- TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(*NextSectionAttributes,0) |
- TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(*NextSectionAttributes);
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (*NextSectionAttributes, 0) |
+ TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (*NextSectionAttributes);
// obtain page table base
SecondLevelTable = (ARM_PAGE_TABLE_ENTRY *)(FirstLevelDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
- for (i=0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
+ for (i = 0; i < TRANSLATION_TABLE_PAGE_COUNT; i++) {
if ((SecondLevelTable[i] & TT_DESCRIPTOR_PAGE_TYPE_MASK) == TT_DESCRIPTOR_PAGE_TYPE_PAGE) {
// extract attributes (cacheability and permissions)
PageAttributes = SecondLevelTable[i] & (TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK | TT_DESCRIPTOR_PAGE_AP_MASK);
if (NextPageAttributes == 0) {
// start on a new region
- *NextRegionLength = 0;
- *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
+ *NextRegionLength = 0;
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = PageAttributes;
} else if (PageAttributes != NextPageAttributes) {
// Convert Section Attributes into GCD Attributes
@@ -190,8 +190,8 @@ SyncCacheConfigPage ( SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
// start on a new region
- *NextRegionLength = 0;
- *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
+ *NextRegionLength = 0;
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = PageAttributes;
}
} else if (NextPageAttributes != 0) {
@@ -202,37 +202,37 @@ SyncCacheConfigPage ( // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, *NextRegionBase, *NextRegionLength, GcdAttributes);
- *NextRegionLength = 0;
- *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
+ *NextRegionLength = 0;
+ *NextRegionBase = BaseAddress | (i << TT_DESCRIPTOR_PAGE_BASE_SHIFT);
NextPageAttributes = 0;
}
+
*NextRegionLength += TT_DESCRIPTOR_PAGE_SIZE;
}
// Convert back PageAttributes into SectionAttributes
*NextSectionAttributes =
- TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(NextPageAttributes,0) |
- TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(NextPageAttributes);
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (NextPageAttributes, 0) |
+ TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (NextPageAttributes);
return EFI_SUCCESS;
}
EFI_STATUS
SyncCacheConfig (
- IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
)
{
- EFI_STATUS Status;
- UINT32 i;
- EFI_PHYSICAL_ADDRESS NextRegionBase;
- UINT64 NextRegionLength;
- UINT32 NextSectionAttributes;
- UINT32 SectionAttributes;
- UINT64 GcdAttributes;
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
- UINTN NumberOfDescriptors;
- EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
-
+ EFI_STATUS Status;
+ UINT32 i;
+ EFI_PHYSICAL_ADDRESS NextRegionBase;
+ UINT64 NextRegionLength;
+ UINT32 NextSectionAttributes;
+ UINT32 SectionAttributes;
+ UINT64 GcdAttributes;
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ UINTN NumberOfDescriptors;
+ EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap;
DEBUG ((DEBUG_PAGE, "SyncCacheConfig()\n"));
@@ -243,10 +243,9 @@ SyncCacheConfig ( // Get the memory space map from GCD
//
MemorySpaceMap = NULL;
- Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
+ Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
ASSERT_EFI_ERROR (Status);
-
// The GCD implementation maintains its own copy of the state of memory space attributes. GCD needs
// to know what the initial memory space attributes are. The CPU Arch. Protocol does not provide a
// GetMemoryAttributes function for GCD to get this so we must resort to calling GCD (as if we were
@@ -261,15 +260,15 @@ SyncCacheConfig ( // iterate through each 1MB descriptor
NextRegionBase = NextRegionLength = 0;
- for (i=0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
+ for (i = 0; i < TRANSLATION_TABLE_SECTION_COUNT; i++) {
if ((FirstLevelTable[i] & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
// extract attributes (cacheability and permissions)
SectionAttributes = FirstLevelTable[i] & (TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK | TT_DESCRIPTOR_SECTION_AP_MASK);
if (NextSectionAttributes == 0) {
// start on a new region
- NextRegionLength = 0;
- NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
+ NextRegionLength = 0;
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = SectionAttributes;
} else if (SectionAttributes != NextSectionAttributes) {
// Convert Section Attributes into GCD Attributes
@@ -280,21 +279,27 @@ SyncCacheConfig ( SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
// start on a new region
- NextRegionLength = 0;
- NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
+ NextRegionLength = 0;
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = SectionAttributes;
}
+
NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
- } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(FirstLevelTable[i])) {
+ } else if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (FirstLevelTable[i])) {
// In this case any bits set in the 'NextSectionAttributes' are garbage and were set from
// bits that are actually part of the pagetable address. We clear it out to zero so that
// the SyncCacheConfigPage will use the page attributes instead of trying to convert the
// section attributes into page attributes
NextSectionAttributes = 0;
- Status = SyncCacheConfigPage (
- i,FirstLevelTable[i],
- NumberOfDescriptors, MemorySpaceMap,
- &NextRegionBase,&NextRegionLength,&NextSectionAttributes);
+ Status = SyncCacheConfigPage (
+ i,
+ FirstLevelTable[i],
+ NumberOfDescriptors,
+ MemorySpaceMap,
+ &NextRegionBase,
+ &NextRegionLength,
+ &NextSectionAttributes
+ );
ASSERT_EFI_ERROR (Status);
} else {
// We do not support yet 16MB sections
@@ -309,10 +314,11 @@ SyncCacheConfig ( // update GCD with these changes (this will recurse into our own CpuSetMemoryAttributes below which is OK)
SetGcdMemorySpaceAttributes (MemorySpaceMap, NumberOfDescriptors, NextRegionBase, NextRegionLength, GcdAttributes);
- NextRegionLength = 0;
- NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
+ NextRegionLength = 0;
+ NextRegionBase = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (i << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
NextSectionAttributes = 0;
}
+
NextRegionLength += TT_DESCRIPTOR_SECTION_SIZE;
}
} // section entry loop
@@ -333,10 +339,10 @@ SyncCacheConfig ( UINT64
EfiAttributeToArmAttribute (
- IN UINT64 EfiAttributes
+ IN UINT64 EfiAttributes
)
{
- UINT64 ArmAttributes;
+ UINT64 ArmAttributes;
switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) {
case EFI_MEMORY_UC:
@@ -382,15 +388,15 @@ EfiAttributeToArmAttribute ( EFI_STATUS
GetMemoryRegionPage (
- IN UINT32 *PageTable,
- IN OUT UINTN *BaseAddress,
- OUT UINTN *RegionLength,
- OUT UINTN *RegionAttributes
+ IN UINT32 *PageTable,
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
)
{
- UINT32 PageAttributes;
- UINT32 TableIndex;
- UINT32 PageDescriptor;
+ UINT32 PageAttributes;
+ UINT32 TableIndex;
+ UINT32 PageDescriptor;
// Convert the section attributes into page attributes
PageAttributes = ConvertSectionAttributesToPageAttributes (*RegionAttributes, 0);
@@ -400,7 +406,7 @@ GetMemoryRegionPage ( ASSERT (TableIndex < TRANSLATION_TABLE_PAGE_COUNT);
// Go through the page table to find the end of the section
- for (; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) {
+ for ( ; TableIndex < TRANSLATION_TABLE_PAGE_COUNT; TableIndex++) {
// Get the section at the given index
PageDescriptor = PageTable[TableIndex];
@@ -416,7 +422,7 @@ GetMemoryRegionPage ( }
} else {
// We do not support Large Page yet. We return EFI_SUCCESS that means end of the region.
- ASSERT(0);
+ ASSERT (0);
return EFI_SUCCESS;
}
}
@@ -426,9 +432,9 @@ GetMemoryRegionPage ( EFI_STATUS
GetMemoryRegion (
- IN OUT UINTN *BaseAddress,
- OUT UINTN *RegionLength,
- OUT UINTN *RegionAttributes
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
)
{
EFI_STATUS Status;
@@ -436,8 +442,8 @@ GetMemoryRegion ( UINT32 PageAttributes;
UINT32 PageTableIndex;
UINT32 SectionDescriptor;
- ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
- UINT32 *PageTable;
+ ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ UINT32 *PageTable;
// Initialize the arguments
*RegionLength = 0;
@@ -459,32 +465,32 @@ GetMemoryRegion ( if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||
((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))
{
- *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
+ *BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK;
*RegionAttributes = SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK;
} else {
// Otherwise, we round it to the page boundary
*BaseAddress = (*BaseAddress) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK;
// Get the attribute at the page table level (Level 2)
- PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
+ PageTable = (UINT32 *)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
// Calculate index into first level translation table for start of modification
PageTableIndex = ((*BaseAddress) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
- PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK;
+ PageAttributes = PageTable[PageTableIndex] & TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK;
*RegionAttributes = TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY (PageAttributes, 0) |
TT_DESCRIPTOR_CONVERT_TO_SECTION_AP (PageAttributes);
}
- for (;TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) {
+ for ( ; TableIndex < TRANSLATION_TABLE_SECTION_COUNT; TableIndex++) {
// Get the section at the given index
SectionDescriptor = FirstLevelTable[TableIndex];
// If the entry is a level-2 page table then we scan it to find the end of the region
if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (SectionDescriptor)) {
// Extract the page table location from the descriptor
- PageTable = (UINT32*)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
+ PageTable = (UINT32 *)(SectionDescriptor & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK);
// Scan the page table to find the end of the region.
Status = GetMemoryRegionPage (PageTable, BaseAddress, RegionLength, RegionAttributes);
@@ -494,7 +500,8 @@ GetMemoryRegion ( break;
}
} else if (((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) ||
- ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION)) {
+ ((SectionDescriptor & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION))
+ {
if ((SectionDescriptor & TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK) != *RegionAttributes) {
// If the attributes of the section differ from the one targeted then we exit the loop
break;
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c index 082ef30fb6..62a6e2d620 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c @@ -11,7 +11,7 @@ #include <Guid/IdleLoopEvent.h>
-BOOLEAN mIsFlushingGCD;
+BOOLEAN mIsFlushingGCD;
/**
This function flushes the range of addresses from Start to Start+Length
@@ -43,13 +43,12 @@ BOOLEAN mIsFlushingGCD; EFI_STATUS
EFIAPI
CpuFlushCpuDataCache (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS Start,
- IN UINT64 Length,
- IN EFI_CPU_FLUSH_TYPE FlushType
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS Start,
+ IN UINT64 Length,
+ IN EFI_CPU_FLUSH_TYPE FlushType
)
{
-
switch (FlushType) {
case EfiCpuFlushTypeWriteBack:
WriteBackDataCacheRange ((VOID *)(UINTN)Start, (UINTN)Length);
@@ -67,7 +66,6 @@ CpuFlushCpuDataCache ( return EFI_SUCCESS;
}
-
/**
This function enables interrupt processing by the processor.
@@ -80,7 +78,7 @@ CpuFlushCpuDataCache ( EFI_STATUS
EFIAPI
CpuEnableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
+ IN EFI_CPU_ARCH_PROTOCOL *This
)
{
ArmEnableInterrupts ();
@@ -88,7 +86,6 @@ CpuEnableInterrupt ( return EFI_SUCCESS;
}
-
/**
This function disables interrupt processing by the processor.
@@ -101,7 +98,7 @@ CpuEnableInterrupt ( EFI_STATUS
EFIAPI
CpuDisableInterrupt (
- IN EFI_CPU_ARCH_PROTOCOL *This
+ IN EFI_CPU_ARCH_PROTOCOL *This
)
{
ArmDisableInterrupts ();
@@ -109,7 +106,6 @@ CpuDisableInterrupt ( return EFI_SUCCESS;
}
-
/**
This function retrieves the processor's current interrupt state a returns it in
State. If interrupts are currently enabled, then TRUE is returned. If interrupts
@@ -126,19 +122,18 @@ CpuDisableInterrupt ( EFI_STATUS
EFIAPI
CpuGetInterruptState (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- OUT BOOLEAN *State
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ OUT BOOLEAN *State
)
{
if (State == NULL) {
return EFI_INVALID_PARAMETER;
}
- *State = ArmGetInterruptState();
+ *State = ArmGetInterruptState ();
return EFI_SUCCESS;
}
-
/**
This function generates an INIT on the processor. If this function succeeds, then the
processor will be reset, and control will not be returned to the caller. If InitType is
@@ -158,8 +153,8 @@ CpuGetInterruptState ( EFI_STATUS
EFIAPI
CpuInit (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_CPU_INIT_TYPE InitType
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_CPU_INIT_TYPE InitType
)
{
return EFI_UNSUPPORTED;
@@ -168,9 +163,9 @@ CpuInit ( EFI_STATUS
EFIAPI
CpuRegisterInterruptHandler (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
return RegisterInterruptHandler (InterruptType, InterruptHandler);
@@ -179,10 +174,10 @@ CpuRegisterInterruptHandler ( EFI_STATUS
EFIAPI
CpuGetTimerValue (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN UINT32 TimerIndex,
- OUT UINT64 *TimerValue,
- OUT UINT64 *TimerPeriod OPTIONAL
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN UINT32 TimerIndex,
+ OUT UINT64 *TimerValue,
+ OUT UINT64 *TimerPeriod OPTIONAL
)
{
return EFI_UNSUPPORTED;
@@ -199,8 +194,8 @@ CpuGetTimerValue ( VOID
EFIAPI
IdleLoopEventCallback (
- IN EFI_EVENT Event,
- IN VOID *Context
+ IN EFI_EVENT Event,
+ IN VOID *Context
)
{
CpuSleep ();
@@ -209,8 +204,8 @@ IdleLoopEventCallback ( //
// Globals used to initialize the protocol
//
-EFI_HANDLE mCpuHandle = NULL;
-EFI_CPU_ARCH_PROTOCOL mCpu = {
+EFI_HANDLE mCpuHandle = NULL;
+EFI_CPU_ARCH_PROTOCOL mCpu = {
CpuFlushCpuDataCache,
CpuEnableInterrupt,
CpuDisableInterrupt,
@@ -226,7 +221,7 @@ EFI_CPU_ARCH_PROTOCOL mCpu = { STATIC
VOID
InitializeDma (
- IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
+ IN OUT EFI_CPU_ARCH_PROTOCOL *CpuArchProtocol
)
{
CpuArchProtocol->DmaBufferAlignment = ArmCacheWritebackGranule ();
@@ -234,22 +229,23 @@ InitializeDma ( EFI_STATUS
CpuDxeInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
- EFI_EVENT IdleLoopEvent;
+ EFI_EVENT IdleLoopEvent;
InitializeExceptions (&mCpu);
InitializeDma (&mCpu);
Status = gBS->InstallMultipleProtocolInterfaces (
- &mCpuHandle,
- &gEfiCpuArchProtocolGuid, &mCpu,
- NULL
- );
+ &mCpuHandle,
+ &gEfiCpuArchProtocolGuid,
+ &mCpu,
+ NULL
+ );
//
// Make sure GCD and MMU settings match. This API calls gDS->SetMemorySpaceAttributes ()
@@ -262,8 +258,8 @@ CpuDxeInitialize ( // If the platform is a MPCore system then install the Configuration Table describing the
// secondary core states
- if (ArmIsMpCore()) {
- PublishArmProcessorTable();
+ if (ArmIsMpCore ()) {
+ PublishArmProcessorTable ();
}
//
diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h index 4cf3ab258c..58ee1444c1 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h @@ -31,7 +31,7 @@ #include <Protocol/DebugSupport.h>
#include <Protocol/LoadedImage.h>
-extern BOOLEAN mIsFlushingGCD;
+extern BOOLEAN mIsFlushingGCD;
/**
This function registers and enables the handler specified by InterruptHandler for a processor
@@ -55,11 +55,10 @@ extern BOOLEAN mIsFlushingGCD; **/
EFI_STATUS
RegisterInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
-
/**
This function registers and enables the handler specified by InterruptHandler for a processor
interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the
@@ -82,28 +81,27 @@ RegisterInterruptHandler ( **/
EFI_STATUS
RegisterDebuggerInterruptHandler (
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
-
EFI_STATUS
EFIAPI
CpuSetMemoryAttributes (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
EFI_STATUS
InitializeExceptions (
- IN EFI_CPU_ARCH_PROTOCOL *Cpu
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu
);
EFI_STATUS
SyncCacheConfig (
- IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
+ IN EFI_CPU_ARCH_PROTOCOL *CpuProtocol
);
/**
@@ -117,30 +115,30 @@ SyncCacheConfig ( **/
VOID
EFIAPI
-PublishArmProcessorTable(
+PublishArmProcessorTable (
VOID
);
// The ARM Attributes might be defined on 64-bit (case of the long format description table)
UINT64
EfiAttributeToArmAttribute (
- IN UINT64 EfiAttributes
+ IN UINT64 EfiAttributes
);
EFI_STATUS
GetMemoryRegion (
- IN OUT UINTN *BaseAddress,
- OUT UINTN *RegionLength,
- OUT UINTN *RegionAttributes
+ IN OUT UINTN *BaseAddress,
+ OUT UINTN *RegionLength,
+ OUT UINTN *RegionAttributes
);
EFI_STATUS
SetGcdMemorySpaceAttributes (
- IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
- IN UINTN NumberOfDescriptors,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
+ IN UINTN NumberOfDescriptors,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
#endif // CPU_DXE_H_
diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c index cdb1d6786a..2e73719dce 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c @@ -29,33 +29,36 @@ **/
EFI_STATUS
SearchGcdMemorySpaces (
- IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
- IN UINTN NumberOfDescriptors,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- OUT UINTN *StartIndex,
- OUT UINTN *EndIndex
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
+ IN UINTN NumberOfDescriptors,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ OUT UINTN *StartIndex,
+ OUT UINTN *EndIndex
)
{
- UINTN Index;
+ UINTN Index;
*StartIndex = 0;
*EndIndex = 0;
for (Index = 0; Index < NumberOfDescriptors; Index++) {
if ((BaseAddress >= MemorySpaceMap[Index].BaseAddress) &&
- (BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) {
+ (BaseAddress < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)))
+ {
*StartIndex = Index;
}
+
if (((BaseAddress + Length - 1) >= MemorySpaceMap[Index].BaseAddress) &&
- ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length))) {
+ ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)))
+ {
*EndIndex = Index;
return EFI_SUCCESS;
}
}
+
return EFI_NOT_FOUND;
}
-
/**
Sets the attributes for a specified range in Gcd Memory Space Map.
@@ -74,11 +77,11 @@ SearchGcdMemorySpaces ( **/
EFI_STATUS
SetGcdMemorySpaceAttributes (
- IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
- IN UINTN NumberOfDescriptors,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap,
+ IN UINTN NumberOfDescriptors,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
EFI_STATUS Status;
@@ -88,14 +91,21 @@ SetGcdMemorySpaceAttributes ( EFI_PHYSICAL_ADDRESS RegionStart;
UINT64 RegionLength;
- DEBUG ((DEBUG_GCD, "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",
- BaseAddress, BaseAddress + Length, Attributes));
+ DEBUG ((
+ DEBUG_GCD,
+ "SetGcdMemorySpaceAttributes[0x%lX; 0x%lX] = 0x%lX\n",
+ BaseAddress,
+ BaseAddress + Length,
+ Attributes
+ ));
// We do not support a smaller granularity than 4KB on ARM Architecture
if ((Length & EFI_PAGE_MASK) != 0) {
- DEBUG ((DEBUG_WARN,
- "Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",
- Length));
+ DEBUG ((
+ DEBUG_WARN,
+ "Warning: We do not support smaller granularity than 4KB on ARM Architecture (passed length: 0x%lX).\n",
+ Length
+ ));
}
//
@@ -120,6 +130,7 @@ SetGcdMemorySpaceAttributes ( if (MemorySpaceMap[Index].GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
continue;
}
+
//
// Calculate the start and end address of the overlapping range
//
@@ -128,11 +139,13 @@ SetGcdMemorySpaceAttributes ( } else {
RegionStart = MemorySpaceMap[Index].BaseAddress;
}
+
if ((BaseAddress + Length - 1) < (MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length)) {
RegionLength = BaseAddress + Length - RegionStart;
} else {
RegionLength = MemorySpaceMap[Index].BaseAddress + MemorySpaceMap[Index].Length - RegionStart;
}
+
//
// Set memory attributes according to MTRR attribute and the original attribute of descriptor
//
@@ -170,10 +183,10 @@ SetGcdMemorySpaceAttributes ( EFI_STATUS
EFIAPI
CpuSetMemoryAttributes (
- IN EFI_CPU_ARCH_PROTOCOL *This,
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 EfiAttributes
+ IN EFI_CPU_ARCH_PROTOCOL *This,
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 EfiAttributes
)
{
EFI_STATUS Status;
@@ -197,7 +210,7 @@ CpuSetMemoryAttributes ( // Get the region starting from 'BaseAddress' and its 'Attribute'
RegionBaseAddress = BaseAddress;
- Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes);
+ Status = GetMemoryRegion (&RegionBaseAddress, &RegionLength, &RegionArmAttributes);
// Data & Instruction Caches are flushed when we set new memory attributes.
// So, we only set the attributes if the new region is different.
diff --git a/ArmPkg/Drivers/CpuDxe/CpuMpCore.c b/ArmPkg/Drivers/CpuDxe/CpuMpCore.c index 8a9e8c2fa3..08de464645 100644 --- a/ArmPkg/Drivers/CpuDxe/CpuMpCore.c +++ b/ArmPkg/Drivers/CpuDxe/CpuMpCore.c @@ -14,7 +14,7 @@ #include <Guid/ArmMpCoreInfo.h>
-ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
+ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {
{
EFI_ARM_PROCESSOR_TABLE_SIGNATURE,
0,
@@ -26,7 +26,7 @@ ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = { EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION,
{ 0 },
0
- }, //ARM Processor table header
+ }, // ARM Processor table header
0, // Number of entries in ARM processor Table
NULL // ARM Processor Table
};
@@ -45,47 +45,48 @@ PublishArmProcessorTable ( VOID
)
{
- EFI_PEI_HOB_POINTERS Hob;
+ EFI_PEI_HOB_POINTERS Hob;
Hob.Raw = GetHobList ();
// Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB
- for (; !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) {
+ for ( ; !END_OF_HOB_LIST (Hob); Hob.Raw = GET_NEXT_HOB (Hob)) {
// Check for Correct HOB type
if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {
// Check for correct GUID type
- if (CompareGuid(&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {
- ARM_PROCESSOR_TABLE *ArmProcessorTable;
- EFI_STATUS Status;
+ if (CompareGuid (&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {
+ ARM_PROCESSOR_TABLE *ArmProcessorTable;
+ EFI_STATUS Status;
// Allocate Runtime memory for ARM processor table
- ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE));
+ ArmProcessorTable = (ARM_PROCESSOR_TABLE *)AllocateRuntimePool (sizeof (ARM_PROCESSOR_TABLE));
// Check if the memory allocation is successful or not
- ASSERT(NULL != ArmProcessorTable);
+ ASSERT (NULL != ArmProcessorTable);
// Set ARM processor table to default values
- CopyMem(ArmProcessorTable,&mArmProcessorTableTemplate,sizeof(ARM_PROCESSOR_TABLE));
+ CopyMem (ArmProcessorTable, &mArmProcessorTableTemplate, sizeof (ARM_PROCESSOR_TABLE));
// Fill in Length fields of ARM processor table
- ArmProcessorTable->Header.Length = sizeof(ARM_PROCESSOR_TABLE);
- ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE(Hob);
+ ArmProcessorTable->Header.Length = sizeof (ARM_PROCESSOR_TABLE);
+ ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE (Hob);
// Fill in Identifier(ARM processor table GUID)
ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid;
// Set Number of ARM core entries in the Table
- ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO);
+ ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE (Hob)/sizeof (ARM_CORE_INFO);
// Allocate runtime memory for ARM processor Table entries
- ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool (
- ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO));
+ ArmProcessorTable->ArmCpus = (ARM_CORE_INFO *)AllocateRuntimePool (
+ ArmProcessorTable->NumberOfEntries * sizeof (ARM_CORE_INFO)
+ );
// Check if the memory allocation is successful or not
- ASSERT(NULL != ArmProcessorTable->ArmCpus);
+ ASSERT (NULL != ArmProcessorTable->ArmCpus);
// Copy ARM Processor Table data from HOB list to newly allocated memory
- CopyMem(ArmProcessorTable->ArmCpus,GET_GUID_HOB_DATA(Hob), ArmProcessorTable->Header.DataLen);
+ CopyMem (ArmProcessorTable->ArmCpus, GET_GUID_HOB_DATA (Hob), ArmProcessorTable->Header.DataLen);
// Install the ARM Processor table into EFI system configuration table
Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable);
diff --git a/ArmPkg/Drivers/CpuDxe/Exception.c b/ArmPkg/Drivers/CpuDxe/Exception.c index 503c882a3f..441f92d502 100644 --- a/ArmPkg/Drivers/CpuDxe/Exception.c +++ b/ArmPkg/Drivers/CpuDxe/Exception.c @@ -13,23 +13,23 @@ EFI_STATUS
InitializeExceptions (
- IN EFI_CPU_ARCH_PROTOCOL *Cpu
+ IN EFI_CPU_ARCH_PROTOCOL *Cpu
)
{
- EFI_STATUS Status;
- EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
- EFI_VECTOR_HANDOFF_INFO *VectorInfo;
- BOOLEAN IrqEnabled;
- BOOLEAN FiqEnabled;
+ EFI_STATUS Status;
+ EFI_VECTOR_HANDOFF_INFO *VectorInfoList;
+ EFI_VECTOR_HANDOFF_INFO *VectorInfo;
+ BOOLEAN IrqEnabled;
+ BOOLEAN FiqEnabled;
VectorInfo = (EFI_VECTOR_HANDOFF_INFO *)NULL;
- Status = EfiGetSystemConfigurationTable(&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
- if (Status == EFI_SUCCESS && VectorInfoList != NULL) {
+ Status = EfiGetSystemConfigurationTable (&gEfiVectorHandoffTableGuid, (VOID **)&VectorInfoList);
+ if ((Status == EFI_SUCCESS) && (VectorInfoList != NULL)) {
VectorInfo = VectorInfoList;
}
// initialize the CpuExceptionHandlerLib so we take over the exception vector table from the DXE Core
- InitializeCpuExceptionHandlers(VectorInfo);
+ InitializeCpuExceptionHandlers (VectorInfo);
Status = EFI_SUCCESS;
@@ -64,7 +64,7 @@ InitializeExceptions ( //
DEBUG_CODE (
ArmEnableAsynchronousAbort ();
- );
+ );
return Status;
}
@@ -90,11 +90,11 @@ previously installed. **/
EFI_STATUS
-RegisterInterruptHandler(
- IN EFI_EXCEPTION_TYPE InterruptType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+RegisterInterruptHandler (
+ IN EFI_EXCEPTION_TYPE InterruptType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
// pass down to CpuExceptionHandlerLib
- return (EFI_STATUS)RegisterCpuInterruptHandler(InterruptType, InterruptHandler);
+ return (EFI_STATUS)RegisterCpuInterruptHandler (InterruptType, InterruptHandler);
}
diff --git a/ArmPkg/Drivers/CpuPei/CpuPei.c b/ArmPkg/Drivers/CpuPei/CpuPei.c index c44311d6b7..85ef5ec07b 100644 --- a/ArmPkg/Drivers/CpuPei/CpuPei.c +++ b/ArmPkg/Drivers/CpuPei/CpuPei.c @@ -16,8 +16,6 @@ Abstract: **/
-
-
//
// The package level header files this module uses
//
@@ -58,10 +56,10 @@ InitializeCpuPeim ( IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
- ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
- UINTN ArmCoreCount;
- ARM_CORE_INFO *ArmCoreInfoTable;
+ EFI_STATUS Status;
+ ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;
+ UINTN ArmCoreCount;
+ ARM_CORE_INFO *ArmCoreInfoTable;
// Enable program flow prediction, if supported.
ArmEnableBranchPrediction ();
@@ -70,12 +68,12 @@ InitializeCpuPeim ( BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize));
// Only MP Core platform need to produce gArmMpCoreInfoPpiGuid
- Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi);
- if (!EFI_ERROR(Status)) {
+ Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID **)&ArmMpCoreInfoPpi);
+ if (!EFI_ERROR (Status)) {
// Build the MP Core Info Table
ArmCoreCount = 0;
- Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
- if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {
+ Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);
+ if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) {
// Build MPCore Info HOB
BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);
}
diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h index 28db57e07b..9bc3bf4704 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdog.h @@ -5,20 +5,21 @@ * SPDX-License-Identifier: BSD-2-Clause-Patent
*
**/
+
#ifndef GENERIC_WATCHDOG_H_
#define GENERIC_WATCHDOG_H_
// Refresh Frame:
-#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
+#define GENERIC_WDOG_REFRESH_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogRefreshBase) + 0x000)
// Control Frame:
-#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)
-#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)
-#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
-#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)
+#define GENERIC_WDOG_CONTROL_STATUS_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x000)
+#define GENERIC_WDOG_OFFSET_REG ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x008)
+#define GENERIC_WDOG_COMPARE_VALUE_REG_LOW ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x010)
+#define GENERIC_WDOG_COMPARE_VALUE_REG_HIGH ((UINTN)FixedPcdGet64 (PcdGenericWatchdogControlBase) + 0x014)
// Values of bit 0 of the Control/Status Register
-#define GENERIC_WDOG_ENABLED 1
-#define GENERIC_WDOG_DISABLED 0
+#define GENERIC_WDOG_ENABLED 1
+#define GENERIC_WDOG_DISABLED 0
-#endif // GENERIC_WATCHDOG_H_
+#endif // GENERIC_WATCHDOG_H_
diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c index f79cc9170f..66c6c37c08 100644 --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c @@ -25,18 +25,18 @@ /* The number of 100ns periods (the unit of time passed to these functions)
in a second */
-#define TIME_UNITS_PER_SECOND 10000000
+#define TIME_UNITS_PER_SECOND 10000000
// Tick frequency of the generic timer basis of the generic watchdog.
-STATIC UINTN mTimerFrequencyHz = 0;
+STATIC UINTN mTimerFrequencyHz = 0;
/* In cases where the compare register was set manually, information about
how long the watchdog was asked to wait cannot be retrieved from hardware.
It is therefore stored here. 0 means the timer is not running. */
-STATIC UINT64 mNumTimerTicks = 0;
+STATIC UINT64 mNumTimerTicks = 0;
-STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
-STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
+STATIC EFI_HARDWARE_INTERRUPT2_PROTOCOL *mInterruptProtocol;
+STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
STATIC
VOID
@@ -97,12 +97,12 @@ STATIC VOID
EFIAPI
WatchdogInterruptHandler (
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
- STATIC CONST CHAR16 ResetString[]= L"The generic watchdog timer ran out.";
- UINT64 TimerPeriod;
+ STATIC CONST CHAR16 ResetString[] = L"The generic watchdog timer ran out.";
+ UINT64 TimerPeriod;
WatchdogDisable ();
@@ -119,8 +119,12 @@ WatchdogInterruptHandler ( mWatchdogNotify (TimerPeriod + 1);
}
- gRT->ResetSystem (EfiResetCold, EFI_TIMEOUT, StrSize (ResetString),
- (CHAR16 *)ResetString);
+ gRT->ResetSystem (
+ EfiResetCold,
+ EFI_TIMEOUT,
+ StrSize (ResetString),
+ (CHAR16 *)ResetString
+ );
// If we got here then the reset didn't work
ASSERT (FALSE);
@@ -154,15 +158,15 @@ STATIC EFI_STATUS
EFIAPI
WatchdogRegisterHandler (
- IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
- IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN EFI_WATCHDOG_TIMER_NOTIFY NotifyFunction
)
{
- if (mWatchdogNotify == NULL && NotifyFunction == NULL) {
+ if ((mWatchdogNotify == NULL) && (NotifyFunction == NULL)) {
return EFI_INVALID_PARAMETER;
}
- if (mWatchdogNotify != NULL && NotifyFunction != NULL) {
+ if ((mWatchdogNotify != NULL) && (NotifyFunction != NULL)) {
return EFI_ALREADY_STARTED;
}
@@ -188,11 +192,11 @@ STATIC EFI_STATUS
EFIAPI
WatchdogSetTimerPeriod (
- IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
- IN UINT64 TimerPeriod // In 100ns units
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ IN UINT64 TimerPeriod // In 100ns units
)
{
- UINTN SystemCount;
+ UINTN SystemCount;
// if TimerPeriod is 0, this is a request to stop the watchdog.
if (TimerPeriod == 0) {
@@ -244,8 +248,8 @@ STATIC EFI_STATUS
EFIAPI
WatchdogGetTimerPeriod (
- IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
- OUT UINT64 *TimerPeriod
+ IN EFI_WATCHDOG_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
@@ -289,26 +293,29 @@ WatchdogGetTimerPeriod ( Retrieves the period of the timer interrupt in 100ns units.
**/
-STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
+STATIC EFI_WATCHDOG_TIMER_ARCH_PROTOCOL mWatchdogTimer = {
WatchdogRegisterHandler,
WatchdogSetTimerPeriod,
WatchdogGetTimerPeriod
};
-STATIC EFI_EVENT mEfiExitBootServicesEvent;
+STATIC EFI_EVENT mEfiExitBootServicesEvent;
EFI_STATUS
EFIAPI
GenericWatchdogEntry (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- EFI_HANDLE Handle;
-
- Status = gBS->LocateProtocol (&gHardwareInterrupt2ProtocolGuid, NULL,
- (VOID **)&mInterruptProtocol);
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ Status = gBS->LocateProtocol (
+ &gHardwareInterrupt2ProtocolGuid,
+ NULL,
+ (VOID **)&mInterruptProtocol
+ );
ASSERT_EFI_ERROR (Status);
/* Make sure the Watchdog Timer Architectural Protocol has not been installed
@@ -320,33 +327,44 @@ GenericWatchdogEntry ( ASSERT (mTimerFrequencyHz != 0);
// Install interrupt handler
- Status = mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol,
+ Status = mInterruptProtocol->RegisterInterruptSource (
+ mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
- WatchdogInterruptHandler);
+ WatchdogInterruptHandler
+ );
if (EFI_ERROR (Status)) {
return Status;
}
- Status = mInterruptProtocol->SetTriggerType (mInterruptProtocol,
+ Status = mInterruptProtocol->SetTriggerType (
+ mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
- EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING);
+ EFI_HARDWARE_INTERRUPT2_TRIGGER_EDGE_RISING
+ );
if (EFI_ERROR (Status)) {
goto UnregisterHandler;
}
// Install the Timer Architectural Protocol onto a new handle
Handle = NULL;
- Status = gBS->InstallMultipleProtocolInterfaces (&Handle,
- &gEfiWatchdogTimerArchProtocolGuid, &mWatchdogTimer,
- NULL);
+ Status = gBS->InstallMultipleProtocolInterfaces (
+ &Handle,
+ &gEfiWatchdogTimerArchProtocolGuid,
+ &mWatchdogTimer,
+ NULL
+ );
if (EFI_ERROR (Status)) {
goto UnregisterHandler;
}
// Register for an ExitBootServicesEvent
- Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, TPL_NOTIFY,
- WatchdogExitBootServicesEvent, NULL,
- &mEfiExitBootServicesEvent);
+ Status = gBS->CreateEvent (
+ EVT_SIGNAL_EXIT_BOOT_SERVICES,
+ TPL_NOTIFY,
+ WatchdogExitBootServicesEvent,
+ NULL,
+ &mEfiExitBootServicesEvent
+ );
ASSERT_EFI_ERROR (Status);
mNumTimerTicks = 0;
@@ -356,8 +374,10 @@ GenericWatchdogEntry ( UnregisterHandler:
// Unregister the handler
- mInterruptProtocol->RegisterInterruptSource (mInterruptProtocol,
+ mInterruptProtocol->RegisterInterruptSource (
+ mInterruptProtocol,
FixedPcdGet32 (PcdGenericWatchdogEl2IntrNum),
- NULL);
+ NULL
+ );
return Status;
}
diff --git a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h index 32753947e1..5c5fcb5768 100644 --- a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h +++ b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunicate.h @@ -9,14 +9,14 @@ #ifndef MM_COMMUNICATE_H_
#define MM_COMMUNICATE_H_
-#define MM_MAJOR_VER_MASK 0xEFFF0000
-#define MM_MINOR_VER_MASK 0x0000FFFF
-#define MM_MAJOR_VER_SHIFT 16
+#define MM_MAJOR_VER_MASK 0xEFFF0000
+#define MM_MINOR_VER_MASK 0x0000FFFF
+#define MM_MAJOR_VER_SHIFT 16
-#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT)
-#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK)
+#define MM_MAJOR_VER(x) (((x) & MM_MAJOR_VER_MASK) >> MM_MAJOR_VER_SHIFT)
+#define MM_MINOR_VER(x) ((x) & MM_MINOR_VER_MASK)
-#define MM_CALLER_MAJOR_VER 0x1UL
-#define MM_CALLER_MINOR_VER 0x0
+#define MM_CALLER_MAJOR_VER 0x1UL
+#define MM_CALLER_MINOR_VER 0x0
#endif /* MM_COMMUNICATE_H_ */
diff --git a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c index b1e3095809..7c8284104d 100644 --- a/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c +++ b/ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.c @@ -63,18 +63,18 @@ STATIC EFI_HANDLE mMmCommunicateHandle; EFI_STATUS
EFIAPI
MmCommunication2Communicate (
- IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,
- IN OUT VOID *CommBufferPhysical,
- IN OUT VOID *CommBufferVirtual,
- IN OUT UINTN *CommSize OPTIONAL
+ IN CONST EFI_MM_COMMUNICATION2_PROTOCOL *This,
+ IN OUT VOID *CommBufferPhysical,
+ IN OUT VOID *CommBufferVirtual,
+ IN OUT UINTN *CommSize OPTIONAL
)
{
- EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;
- ARM_SMC_ARGS CommunicateSmcArgs;
- EFI_STATUS Status;
- UINTN BufferSize;
+ EFI_MM_COMMUNICATE_HEADER *CommunicateHeader;
+ ARM_SMC_ARGS CommunicateSmcArgs;
+ EFI_STATUS Status;
+ UINTN BufferSize;
- Status = EFI_ACCESS_DENIED;
+ Status = EFI_ACCESS_DENIED;
BufferSize = 0;
ZeroMem (&CommunicateSmcArgs, sizeof (ARM_SMC_ARGS));
@@ -100,15 +100,17 @@ MmCommunication2Communicate ( // This case can be used by the consumer of this driver to find out the
// max size that can be used for allocating CommBuffer.
if ((*CommSize == 0) ||
- (*CommSize > mNsCommBuffMemRegion.Length)) {
+ (*CommSize > mNsCommBuffMemRegion.Length))
+ {
*CommSize = mNsCommBuffMemRegion.Length;
return EFI_BAD_BUFFER_SIZE;
}
+
//
// CommSize must match MessageLength + sizeof (EFI_MM_COMMUNICATE_HEADER);
//
if (*CommSize != BufferSize) {
- return EFI_INVALID_PARAMETER;
+ return EFI_INVALID_PARAMETER;
}
}
@@ -117,7 +119,8 @@ MmCommunication2Communicate ( // environment then return the expected size.
//
if ((BufferSize == 0) ||
- (BufferSize > mNsCommBuffMemRegion.Length)) {
+ (BufferSize > mNsCommBuffMemRegion.Length))
+ {
CommunicateHeader->MessageLength = mNsCommBuffMemRegion.Length -
sizeof (CommunicateHeader->HeaderGuid) -
sizeof (CommunicateHeader->MessageLength);
@@ -143,41 +146,41 @@ MmCommunication2Communicate ( ArmCallSmc (&CommunicateSmcArgs);
switch (CommunicateSmcArgs.Arg0) {
- case ARM_SMC_MM_RET_SUCCESS:
- ZeroMem (CommBufferVirtual, BufferSize);
- // On successful return, the size of data being returned is inferred from
- // MessageLength + Header.
- CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
- BufferSize = CommunicateHeader->MessageLength +
- sizeof (CommunicateHeader->HeaderGuid) +
- sizeof (CommunicateHeader->MessageLength);
-
- CopyMem (
- CommBufferVirtual,
- (VOID *)mNsCommBuffMemRegion.VirtualBase,
- BufferSize
- );
- Status = EFI_SUCCESS;
- break;
-
- case ARM_SMC_MM_RET_INVALID_PARAMS:
- Status = EFI_INVALID_PARAMETER;
- break;
-
- case ARM_SMC_MM_RET_DENIED:
- Status = EFI_ACCESS_DENIED;
- break;
-
- case ARM_SMC_MM_RET_NO_MEMORY:
- // Unexpected error since the CommSize was checked for zero length
- // prior to issuing the SMC
- Status = EFI_OUT_OF_RESOURCES;
- ASSERT (0);
- break;
-
- default:
- Status = EFI_ACCESS_DENIED;
- ASSERT (0);
+ case ARM_SMC_MM_RET_SUCCESS:
+ ZeroMem (CommBufferVirtual, BufferSize);
+ // On successful return, the size of data being returned is inferred from
+ // MessageLength + Header.
+ CommunicateHeader = (EFI_MM_COMMUNICATE_HEADER *)mNsCommBuffMemRegion.VirtualBase;
+ BufferSize = CommunicateHeader->MessageLength +
+ sizeof (CommunicateHeader->HeaderGuid) +
+ sizeof (CommunicateHeader->MessageLength);
+
+ CopyMem (
+ CommBufferVirtual,
+ (VOID *)mNsCommBuffMemRegion.VirtualBase,
+ BufferSize
+ );
+ Status = EFI_SUCCESS;
+ break;
+
+ case ARM_SMC_MM_RET_INVALID_PARAMS:
+ Status = EFI_INVALID_PARAMETER;
+ break;
+
+ case ARM_SMC_MM_RET_DENIED:
+ Status = EFI_ACCESS_DENIED;
+ break;
+
+ case ARM_SMC_MM_RET_NO_MEMORY:
+ // Unexpected error since the CommSize was checked for zero length
+ // prior to issuing the SMC
+ Status = EFI_OUT_OF_RESOURCES;
+ ASSERT (0);
+ break;
+
+ default:
+ Status = EFI_ACCESS_DENIED;
+ ASSERT (0);
}
return Status;
@@ -209,7 +212,7 @@ VOID EFIAPI
NotifySetVirtualAddressMap (
IN EFI_EVENT Event,
- IN VOID *Context
+ IN VOID *Context
)
{
EFI_STATUS Status;
@@ -219,19 +222,23 @@ NotifySetVirtualAddressMap ( (VOID **)&mNsCommBuffMemRegion.VirtualBase
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "NotifySetVirtualAddressMap():"
- " Unable to convert MM runtime pointer. Status:0x%r\n", Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "NotifySetVirtualAddressMap():"
+ " Unable to convert MM runtime pointer. Status:0x%r\n",
+ Status
+ ));
}
-
}
STATIC
EFI_STATUS
-GetMmCompatibility ()
+GetMmCompatibility (
+ )
{
- EFI_STATUS Status;
- UINT32 MmVersion;
- ARM_SMC_ARGS MmVersionArgs;
+ EFI_STATUS Status;
+ UINT32 MmVersion;
+ ARM_SMC_ARGS MmVersionArgs;
// MM_VERSION uses SMC32 calling conventions
MmVersionArgs.Arg0 = ARM_SMC_ID_MM_VERSION_AARCH32;
@@ -240,27 +247,38 @@ GetMmCompatibility () MmVersion = MmVersionArgs.Arg0;
- if ((MM_MAJOR_VER(MmVersion) == MM_CALLER_MAJOR_VER) &&
- (MM_MINOR_VER(MmVersion) >= MM_CALLER_MINOR_VER)) {
- DEBUG ((DEBUG_INFO, "MM Version: Major=0x%x, Minor=0x%x\n",
- MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion)));
+ if ((MM_MAJOR_VER (MmVersion) == MM_CALLER_MAJOR_VER) &&
+ (MM_MINOR_VER (MmVersion) >= MM_CALLER_MINOR_VER))
+ {
+ DEBUG ((
+ DEBUG_INFO,
+ "MM Version: Major=0x%x, Minor=0x%x\n",
+ MM_MAJOR_VER (MmVersion),
+ MM_MINOR_VER (MmVersion)
+ ));
Status = EFI_SUCCESS;
} else {
- DEBUG ((DEBUG_ERROR, "Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",
- MM_MAJOR_VER(MmVersion), MM_MINOR_VER(MmVersion), MM_CALLER_MAJOR_VER, MM_CALLER_MINOR_VER));
+ DEBUG ((
+ DEBUG_ERROR,
+ "Incompatible MM Versions.\n Current Version: Major=0x%x, Minor=0x%x.\n Expected: Major=0x%x, Minor>=0x%x.\n",
+ MM_MAJOR_VER (MmVersion),
+ MM_MINOR_VER (MmVersion),
+ MM_CALLER_MAJOR_VER,
+ MM_CALLER_MINOR_VER
+ ));
Status = EFI_UNSUPPORTED;
}
return Status;
}
-STATIC EFI_GUID* CONST mGuidedEventGuid[] = {
+STATIC EFI_GUID *CONST mGuidedEventGuid[] = {
&gEfiEndOfDxeEventGroupGuid,
&gEfiEventExitBootServicesGuid,
&gEfiEventReadyToBootGuid,
};
-STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)];
+STATIC EFI_EVENT mGuidedEvent[ARRAY_SIZE (mGuidedEventGuid)];
/**
Event notification that is fired when GUIDed Event Group is signaled.
@@ -277,15 +295,15 @@ MmGuidedEventNotify ( IN VOID *Context
)
{
- EFI_MM_COMMUNICATE_HEADER Header;
- UINTN Size;
+ EFI_MM_COMMUNICATE_HEADER Header;
+ UINTN Size;
//
// Use Guid to initialize EFI_SMM_COMMUNICATE_HEADER structure
//
CopyGuid (&Header.HeaderGuid, Context);
Header.MessageLength = 1;
- Header.Data[0] = 0;
+ Header.Data[0] = 0;
Size = sizeof (Header);
MmCommunication2Communicate (&mMmCommunication2, &Header, &Header, &Size);
@@ -308,23 +326,23 @@ MmGuidedEventNotify ( EFI_STATUS
EFIAPI
MmCommunication2Initialize (
- IN EFI_HANDLE ImageHandle,
+ IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- UINTN Index;
+ EFI_STATUS Status;
+ UINTN Index;
// Check if we can make the MM call
Status = GetMmCompatibility ();
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
goto ReturnErrorStatus;
}
mNsCommBuffMemRegion.PhysicalBase = PcdGet64 (PcdMmBufferBase);
// During boot , Virtual and Physical are same
mNsCommBuffMemRegion.VirtualBase = mNsCommBuffMemRegion.PhysicalBase;
- mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);
+ mNsCommBuffMemRegion.Length = PcdGet64 (PcdMmBufferSize);
ASSERT (mNsCommBuffMemRegion.PhysicalBase != 0);
@@ -339,8 +357,11 @@ MmCommunication2Initialize ( EFI_MEMORY_RUNTIME
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: "
- "Failed to add MM-NS Buffer Memory Space\n"));
+ DEBUG ((
+ DEBUG_ERROR,
+ "MmCommunicateInitialize: "
+ "Failed to add MM-NS Buffer Memory Space\n"
+ ));
goto ReturnErrorStatus;
}
@@ -350,8 +371,11 @@ MmCommunication2Initialize ( EFI_MEMORY_WB | EFI_MEMORY_XP | EFI_MEMORY_RUNTIME
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "MmCommunicateInitialize: "
- "Failed to set MM-NS Buffer Memory attributes\n"));
+ DEBUG ((
+ DEBUG_ERROR,
+ "MmCommunicateInitialize: "
+ "Failed to set MM-NS Buffer Memory attributes\n"
+ ));
goto CleanAddedMemorySpace;
}
@@ -362,9 +386,12 @@ MmCommunication2Initialize ( EFI_NATIVE_INTERFACE,
&mMmCommunication2
);
- if (EFI_ERROR(Status)) {
- DEBUG ((DEBUG_ERROR, "MmCommunicationInitialize: "
- "Failed to install MM communication protocol\n"));
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "MmCommunicationInitialize: "
+ "Failed to install MM communication protocol\n"
+ ));
goto CleanAddedMemorySpace;
}
@@ -381,17 +408,24 @@ MmCommunication2Initialize ( ASSERT_EFI_ERROR (Status);
for (Index = 0; Index < ARRAY_SIZE (mGuidedEventGuid); Index++) {
- Status = gBS->CreateEventEx (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,
- MmGuidedEventNotify, mGuidedEventGuid[Index],
- mGuidedEventGuid[Index], &mGuidedEvent[Index]);
+ Status = gBS->CreateEventEx (
+ EVT_NOTIFY_SIGNAL,
+ TPL_CALLBACK,
+ MmGuidedEventNotify,
+ mGuidedEventGuid[Index],
+ mGuidedEventGuid[Index],
+ &mGuidedEvent[Index]
+ );
ASSERT_EFI_ERROR (Status);
if (EFI_ERROR (Status)) {
while (Index-- > 0) {
gBS->CloseEvent (mGuidedEvent[Index]);
}
+
goto UninstallProtocol;
}
}
+
return EFI_SUCCESS;
UninstallProtocol:
diff --git a/ArmPkg/Drivers/TimerDxe/TimerDxe.c b/ArmPkg/Drivers/TimerDxe/TimerDxe.c index 0370620fae..1559b323eb 100644 --- a/ArmPkg/Drivers/TimerDxe/TimerDxe.c +++ b/ArmPkg/Drivers/TimerDxe/TimerDxe.c @@ -7,7 +7,6 @@ **/
-
#include <PiDxe.h>
#include <Library/ArmLib.h>
@@ -24,18 +23,18 @@ #include <Protocol/HardwareInterrupt.h>
// The notification function to call on every timer interrupt.
-EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
-EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
+EFI_TIMER_NOTIFY mTimerNotifyFunction = (EFI_TIMER_NOTIFY)NULL;
+EFI_EVENT EfiExitBootServicesEvent = (EFI_EVENT)NULL;
// The current period of the timer interrupt
-UINT64 mTimerPeriod = 0;
+UINT64 mTimerPeriod = 0;
// The latest Timer Tick calculated for mTimerPeriod
-UINT64 mTimerTicks = 0;
+UINT64 mTimerTicks = 0;
// Number of elapsed period since the last Timer interrupt
-UINT64 mElapsedPeriod = 1;
+UINT64 mElapsedPeriod = 1;
// Cached copy of the Hardware Interrupt protocol instance
-EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
+EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL;
/**
This function registers the handler NotifyFunction so it is called every time
@@ -133,9 +132,9 @@ TimerDriverSetTimerPeriod ( IN UINT64 TimerPeriod
)
{
- UINT64 CounterValue;
- UINT64 TimerTicks;
- EFI_TPL OriginalTPL;
+ UINT64 CounterValue;
+ UINT64 TimerTicks;
+ EFI_TPL OriginalTPL;
// Always disable the timer
ArmGenericTimerDisableTimer ();
@@ -166,7 +165,7 @@ TimerDriverSetTimerPeriod ( ArmGenericTimerEnableTimer ();
} else {
// Save the new timer period
- mTimerPeriod = TimerPeriod;
+ mTimerPeriod = TimerPeriod;
// Reset the elapsed period
mElapsedPeriod = 1;
}
@@ -192,8 +191,8 @@ TimerDriverSetTimerPeriod ( EFI_STATUS
EFIAPI
TimerDriverGetTimerPeriod (
- IN EFI_TIMER_ARCH_PROTOCOL *This,
- OUT UINT64 *TimerPeriod
+ IN EFI_TIMER_ARCH_PROTOCOL *This,
+ OUT UINT64 *TimerPeriod
)
{
if (TimerPeriod == NULL) {
@@ -262,7 +261,7 @@ TimerDriverGenerateSoftInterrupt ( a period of time.
**/
-EFI_TIMER_ARCH_PROTOCOL gTimer = {
+EFI_TIMER_ARCH_PROTOCOL gTimer = {
TimerDriverRegisterHandler,
TimerDriverSetTimerPeriod,
TimerDriverGetTimerPeriod,
@@ -285,13 +284,13 @@ EFI_TIMER_ARCH_PROTOCOL gTimer = { VOID
EFIAPI
TimerInterruptHandler (
- IN HARDWARE_INTERRUPT_SOURCE Source,
- IN EFI_SYSTEM_CONTEXT SystemContext
+ IN HARDWARE_INTERRUPT_SOURCE Source,
+ IN EFI_SYSTEM_CONTEXT SystemContext
)
{
- EFI_TPL OriginalTPL;
- UINT64 CurrentValue;
- UINT64 CompareValue;
+ EFI_TPL OriginalTPL;
+ UINT64 CurrentValue;
+ UINT64 CompareValue;
//
// DXE core uses this callback for the EFI timer tick. The DXE core uses locks
@@ -305,8 +304,7 @@ TimerInterruptHandler ( gInterrupt->EndOfInterrupt (gInterrupt, Source);
// Check if the timer interrupt is active
- if ((ArmGenericTimerGetTimerCtrlReg () ) & ARM_ARCH_TIMER_ISTATUS) {
-
+ if ((ArmGenericTimerGetTimerCtrlReg ()) & ARM_ARCH_TIMER_ISTATUS) {
if (mTimerNotifyFunction != 0) {
mTimerNotifyFunction (mTimerPeriod * mElapsedPeriod);
}
@@ -338,7 +336,6 @@ TimerInterruptHandler ( gBS->RestoreTPL (OriginalTPL);
}
-
/**
Initialize the state information for the Timer Architectural Protocol and
the Timer Debug support protocol that allows the debugger to break into a
@@ -355,8 +352,8 @@ TimerInterruptHandler ( EFI_STATUS
EFIAPI
TimerInitialize (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_HANDLE Handle;
@@ -374,7 +371,7 @@ TimerInitialize ( ASSERT_EFI_ERROR (Status);
// Disable the timer
- TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg ();
+ TimerCtrlReg = ArmGenericTimerGetTimerCtrlReg ();
TimerCtrlReg |= ARM_ARCH_TIMER_IMASK;
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmGenericTimerSetTimerCtrlReg (TimerCtrlReg);
@@ -405,17 +402,18 @@ TimerInitialize ( ASSERT_EFI_ERROR (Status);
// Set up default timer
- Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32(PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
+ Status = TimerDriverSetTimerPeriod (&gTimer, FixedPcdGet32 (PcdTimerPeriod)); // TIMER_DEFAULT_PERIOD
ASSERT_EFI_ERROR (Status);
Handle = NULL;
// Install the Timer Architectural Protocol onto a new handle
- Status = gBS->InstallMultipleProtocolInterfaces(
+ Status = gBS->InstallMultipleProtocolInterfaces (
&Handle,
- &gEfiTimerArchProtocolGuid, &gTimer,
+ &gEfiTimerArchProtocolGuid,
+ &gTimer,
NULL
);
- ASSERT_EFI_ERROR(Status);
+ ASSERT_EFI_ERROR (Status);
// Everything is ready, unmask and enable timer interrupts
TimerCtrlReg = ARM_ARCH_TIMER_ENABLE;
diff --git a/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c b/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c index c5036b7b5c..39a30533ee 100644 --- a/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c +++ b/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c @@ -27,16 +27,16 @@ #include "SemihostFs.h"
-#define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs"
+#define DEFAULT_SEMIHOST_FS_LABEL L"SemihostFs"
-STATIC CHAR16 *mSemihostFsLabel;
+STATIC CHAR16 *mSemihostFsLabel;
-EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {
+EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {
EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,
VolumeOpen
};
-EFI_FILE gSemihostFsFile = {
+EFI_FILE gSemihostFsFile = {
EFI_FILE_PROTOCOL_REVISION,
FileOpen,
FileClose,
@@ -54,43 +54,45 @@ EFI_FILE gSemihostFsFile = { // Device path for semi-hosting. It contains our auto-generated Caller ID GUID.
//
typedef struct {
- VENDOR_DEVICE_PATH Guid;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH Guid;
+ EFI_DEVICE_PATH_PROTOCOL End;
} SEMIHOST_DEVICE_PATH;
-SEMIHOST_DEVICE_PATH gDevicePath = {
+SEMIHOST_DEVICE_PATH gDevicePath = {
{
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 } },
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0 }
+ },
EFI_CALLER_ID_GUID
},
- { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 } }
+ { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0 }
+ }
};
typedef struct {
- LIST_ENTRY Link;
- UINT64 Signature;
- EFI_FILE File;
- CHAR8 *FileName;
- UINT64 OpenMode;
- UINT32 Position;
- UINTN SemihostHandle;
- BOOLEAN IsRoot;
- EFI_FILE_INFO Info;
+ LIST_ENTRY Link;
+ UINT64 Signature;
+ EFI_FILE File;
+ CHAR8 *FileName;
+ UINT64 OpenMode;
+ UINT32 Position;
+ UINTN SemihostHandle;
+ BOOLEAN IsRoot;
+ EFI_FILE_INFO Info;
} SEMIHOST_FCB;
-#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' )
-#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)
-#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);
+#define SEMIHOST_FCB_SIGNATURE SIGNATURE_32( 'S', 'H', 'F', 'C' )
+#define SEMIHOST_FCB_FROM_THIS(a) CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)
+#define SEMIHOST_FCB_FROM_LINK(a) CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);
EFI_HANDLE gInstallHandle = NULL;
-LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);
+LIST_ENTRY gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);
SEMIHOST_FCB *
AllocateFCB (
VOID
)
{
- SEMIHOST_FCB *Fcb;
+ SEMIHOST_FCB *Fcb;
Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));
if (Fcb != NULL) {
@@ -103,7 +105,7 @@ AllocateFCB ( VOID
FreeFCB (
- IN SEMIHOST_FCB *Fcb
+ IN SEMIHOST_FCB *Fcb
)
{
// Remove Fcb from gFileList.
@@ -115,15 +117,13 @@ FreeFCB ( FreePool (Fcb);
}
-
-
EFI_STATUS
VolumeOpen (
- IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
- OUT EFI_FILE **Root
+ IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
+ OUT EFI_FILE **Root
)
{
- SEMIHOST_FCB *RootFcb;
+ SEMIHOST_FCB *RootFcb;
if (Root == NULL) {
return EFI_INVALID_PARAMETER;
@@ -134,7 +134,7 @@ VolumeOpen ( return EFI_OUT_OF_RESOURCES;
}
- RootFcb->IsRoot = TRUE;
+ RootFcb->IsRoot = TRUE;
RootFcb->Info.Attribute = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;
InsertTailList (&gFileList, &RootFcb->Link);
@@ -191,29 +191,33 @@ FileOpen ( return EFI_INVALID_PARAMETER;
}
- if ( (OpenMode != EFI_FILE_MODE_READ) &&
- (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) &&
- (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)) ) {
+ if ((OpenMode != EFI_FILE_MODE_READ) &&
+ (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE)) &&
+ (OpenMode != (EFI_FILE_MODE_READ | EFI_FILE_MODE_WRITE | EFI_FILE_MODE_CREATE)))
+ {
return EFI_INVALID_PARAMETER;
}
if (((OpenMode & EFI_FILE_MODE_CREATE) != 0) &&
- ((Attributes & EFI_FILE_DIRECTORY) != 0)) {
+ ((Attributes & EFI_FILE_DIRECTORY) != 0))
+ {
return EFI_WRITE_PROTECTED;
}
- Length = StrLen (FileName) + 1;
+ Length = StrLen (FileName) + 1;
AsciiFileName = AllocatePool (Length);
if (AsciiFileName == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
UnicodeStrToAsciiStrS (FileName, AsciiFileName, Length);
// Opening '/', '\', '.', or the NULL pathname is trying to open the root directory
if ((AsciiStrCmp (AsciiFileName, "\\") == 0) ||
(AsciiStrCmp (AsciiFileName, "/") == 0) ||
(AsciiStrCmp (AsciiFileName, "") == 0) ||
- (AsciiStrCmp (AsciiFileName, ".") == 0) ) {
+ (AsciiStrCmp (AsciiFileName, ".") == 0))
+ {
FreePool (AsciiFileName);
return (VolumeOpen (&gSemihostFs, NewHandle));
}
@@ -232,6 +236,7 @@ FileOpen ( } else {
SemihostMode = SEMIHOST_FILE_MODE_READ | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;
}
+
Return = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);
if (RETURN_ERROR (Return)) {
@@ -279,7 +284,7 @@ FileOpen ( FileFcb->Info.FileSize = Length;
FileFcb->Info.PhysicalSize = Length;
FileFcb->Info.Attribute = ((OpenMode & EFI_FILE_MODE_CREATE) != 0) ?
- Attributes : 0;
+ Attributes : 0;
InsertTailList (&gFileList, &FileFcb->Link);
@@ -308,7 +313,7 @@ STATIC EFI_STATUS
TruncateFile (
IN CHAR8 *FileName,
- IN UINTN Size
+ IN UINTN Size
)
{
EFI_STATUS Status;
@@ -338,7 +343,7 @@ TruncateFile ( goto Error;
}
- Read = 0;
+ Read = 0;
Remaining = Size;
while (Remaining > 0) {
ToRead = Remaining;
@@ -346,11 +351,12 @@ TruncateFile ( if (RETURN_ERROR (Return)) {
goto Error;
}
+
Remaining -= ToRead;
Read += ToRead;
}
- Return = SemihostFileClose (FileHandle);
+ Return = SemihostFileClose (FileHandle);
FileHandle = 0;
if (RETURN_ERROR (Return)) {
goto Error;
@@ -379,12 +385,12 @@ Error: if (FileHandle != 0) {
SemihostFileClose (FileHandle);
}
+
if (Buffer != NULL) {
FreePool (Buffer);
}
return (Status);
-
}
/**
@@ -402,13 +408,13 @@ FileClose ( IN EFI_FILE *This
)
{
- SEMIHOST_FCB *Fcb;
+ SEMIHOST_FCB *Fcb;
if (This == NULL) {
return EFI_INVALID_PARAMETER;
}
- Fcb = SEMIHOST_FCB_FROM_THIS(This);
+ Fcb = SEMIHOST_FCB_FROM_THIS (This);
if (!Fcb->IsRoot) {
SemihostFileClose (Fcb->SemihostHandle);
@@ -420,6 +426,7 @@ FileClose ( if (Fcb->Info.FileSize < Fcb->Info.PhysicalSize) {
TruncateFile (Fcb->FileName, Fcb->Info.FileSize);
}
+
FreePool (Fcb->FileName);
}
@@ -441,7 +448,7 @@ FileClose ( **/
EFI_STATUS
FileDelete (
- IN EFI_FILE *This
+ IN EFI_FILE *This
)
{
SEMIHOST_FCB *Fcb;
@@ -471,6 +478,7 @@ FileDelete ( if (RETURN_ERROR (Return)) {
return EFI_WARN_DELETE_FAILURE;
}
+
return EFI_SUCCESS;
} else {
return EFI_WARN_DELETE_FAILURE;
@@ -566,14 +574,15 @@ ExtendFile ( }
Remaining = Size;
- SetMem (WriteBuffer, 0, sizeof(WriteBuffer));
+ SetMem (WriteBuffer, 0, sizeof (WriteBuffer));
while (Remaining > 0) {
- WriteNb = MIN (Remaining, sizeof(WriteBuffer));
+ WriteNb = MIN (Remaining, sizeof (WriteBuffer));
WriteSize = WriteNb;
- Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer);
+ Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, WriteBuffer);
if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR;
}
+
Remaining -= WriteNb;
}
@@ -599,9 +608,9 @@ ExtendFile ( **/
EFI_STATUS
FileWrite (
- IN EFI_FILE *This,
- IN OUT UINTN *BufferSize,
- IN VOID *Buffer
+ IN EFI_FILE *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
)
{
SEMIHOST_FCB *Fcb;
@@ -617,8 +626,9 @@ FileWrite ( Fcb = SEMIHOST_FCB_FROM_THIS (This);
// We cannot write a read-only file
- if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
- || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) {
+ if ( (Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
+ || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE))
+ {
return EFI_ACCESS_DENIED;
}
@@ -632,11 +642,12 @@ FileWrite ( if (EFI_ERROR (Status)) {
return Status;
}
+
Fcb->Info.FileSize = Fcb->Position;
}
WriteSize = *BufferSize;
- Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);
+ Return = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);
if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR;
}
@@ -650,6 +661,7 @@ FileWrite ( if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR;
}
+
Fcb->Info.PhysicalSize = Length;
return EFI_SUCCESS;
@@ -668,17 +680,17 @@ FileWrite ( **/
EFI_STATUS
FileGetPosition (
- IN EFI_FILE *This,
- OUT UINT64 *Position
+ IN EFI_FILE *This,
+ OUT UINT64 *Position
)
{
- SEMIHOST_FCB *Fcb;
+ SEMIHOST_FCB *Fcb;
if ((This == NULL) || (Position == NULL)) {
return EFI_INVALID_PARAMETER;
}
- Fcb = SEMIHOST_FCB_FROM_THIS(This);
+ Fcb = SEMIHOST_FCB_FROM_THIS (This);
*Position = Fcb->Position;
@@ -701,8 +713,8 @@ FileGetPosition ( **/
EFI_STATUS
FileSetPosition (
- IN EFI_FILE *This,
- IN UINT64 Position
+ IN EFI_FILE *This,
+ IN UINT64 Position
)
{
SEMIHOST_FCB *Fcb;
@@ -718,8 +730,7 @@ FileSetPosition ( if (Position != 0) {
return EFI_UNSUPPORTED;
}
- }
- else {
+ } else {
//
// UEFI Spec section 12.5:
// "Seeking to position 0xFFFFFFFFFFFFFFFF causes the current position to
@@ -728,6 +739,7 @@ FileSetPosition ( if (Position == 0xFFFFFFFFFFFFFFFF) {
Position = Fcb->Info.FileSize;
}
+
Return = SemihostFileSeek (Fcb->SemihostHandle, MIN (Position, Fcb->Info.FileSize));
if (RETURN_ERROR (Return)) {
return EFI_DEVICE_ERROR;
@@ -760,14 +772,14 @@ GetFileInfo ( OUT VOID *Buffer
)
{
- EFI_FILE_INFO *Info;
- UINTN NameSize;
- UINTN ResultSize;
- UINTN Index;
+ EFI_FILE_INFO *Info;
+ UINTN NameSize;
+ UINTN ResultSize;
+ UINTN Index;
if (Fcb->IsRoot) {
- NameSize = 0;
- ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);
+ NameSize = 0;
+ ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof (CHAR16);
} else {
NameSize = AsciiStrLen (Fcb->FileName) + 1;
ResultSize = SIZE_OF_EFI_FILE_INFO + NameSize * sizeof (CHAR16);
@@ -787,7 +799,7 @@ GetFileInfo ( Info->Size = ResultSize;
if (Fcb->IsRoot) {
- Info->FileName[0] = L'\0';
+ Info->FileName[0] = L'\0';
} else {
for (Index = 0; Index < NameSize; Index++) {
Info->FileName[Index] = Fcb->FileName[Index];
@@ -818,9 +830,9 @@ GetFileInfo ( STATIC
EFI_STATUS
GetFilesystemInfo (
- IN SEMIHOST_FCB *Fcb,
- IN OUT UINTN *BufferSize,
- OUT VOID *Buffer
+ IN SEMIHOST_FCB *Fcb,
+ IN OUT UINTN *BufferSize,
+ OUT VOID *Buffer
)
{
EFI_FILE_SYSTEM_INFO *Info;
@@ -882,18 +894,19 @@ FileGetInfo ( OUT VOID *Buffer
)
{
- SEMIHOST_FCB *Fcb;
- EFI_STATUS Status;
- UINTN ResultSize;
+ SEMIHOST_FCB *Fcb;
+ EFI_STATUS Status;
+ UINTN ResultSize;
if ((This == NULL) ||
(InformationType == NULL) ||
(BufferSize == NULL) ||
- ((Buffer == NULL) && (*BufferSize > 0)) ) {
+ ((Buffer == NULL) && (*BufferSize > 0)))
+ {
return EFI_INVALID_PARAMETER;
}
- Fcb = SEMIHOST_FCB_FROM_THIS(This);
+ Fcb = SEMIHOST_FCB_FROM_THIS (This);
if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {
Status = GetFilesystemInfo (Fcb, BufferSize, Buffer);
@@ -963,11 +976,12 @@ SetFileInfo ( return EFI_ACCESS_DENIED;
}
- Length = StrLen (Info->FileName) + 1;
+ Length = StrLen (Info->FileName) + 1;
AsciiFileName = AllocatePool (Length);
if (AsciiFileName == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
UnicodeStrToAsciiStrS (Info->FileName, AsciiFileName, Length);
FileSizeIsDifferent = (Info->FileSize != Fcb->Info.FileSize);
@@ -985,7 +999,8 @@ SetFileInfo ( // description.
//
if ((Fcb->OpenMode == EFI_FILE_MODE_READ) ||
- (Fcb->Info.Attribute & EFI_FILE_READ_ONLY) ) {
+ (Fcb->Info.Attribute & EFI_FILE_READ_ONLY))
+ {
if (FileSizeIsDifferent || FileNameIsDifferent || ReadOnlyIsDifferent) {
Status = EFI_ACCESS_DENIED;
goto Error;
@@ -1006,6 +1021,7 @@ SetFileInfo ( if (EFI_ERROR (Status)) {
goto Error;
}
+
//
// The read/write position from the host file system point of view
// is at the end of the file. If the position from this module
@@ -1016,12 +1032,14 @@ SetFileInfo ( FileSetPosition (&Fcb->File, Fcb->Position);
}
}
+
Fcb->Info.FileSize = FileSize;
Return = SemihostFileLength (Fcb->SemihostHandle, &Length);
if (RETURN_ERROR (Return)) {
goto Error;
}
+
Fcb->Info.PhysicalSize = Length;
}
@@ -1048,6 +1066,7 @@ SetFileInfo ( if (RETURN_ERROR (Return)) {
goto Error;
}
+
FreePool (Fcb->FileName);
Fcb->FileName = AsciiFileName;
AsciiFileName = NULL;
@@ -1119,19 +1138,24 @@ FileSetInfo ( if (Info->Size < (SIZE_OF_EFI_FILE_INFO + StrSize (Info->FileName))) {
return EFI_INVALID_PARAMETER;
}
+
if (BufferSize < Info->Size) {
return EFI_BAD_BUFFER_SIZE;
}
+
return SetFileInfo (Fcb, Info);
} else if (CompareGuid (InformationType, &gEfiFileSystemInfoGuid)) {
SystemInfo = Buffer;
if (SystemInfo->Size <
- (SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel))) {
+ (SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize (SystemInfo->VolumeLabel)))
+ {
return EFI_INVALID_PARAMETER;
}
+
if (BufferSize < SystemInfo->Size) {
return EFI_BAD_BUFFER_SIZE;
}
+
Buffer = SystemInfo->VolumeLabel;
if (StrSize (Buffer) > 0) {
@@ -1155,18 +1179,19 @@ FileSetInfo ( EFI_STATUS
FileFlush (
- IN EFI_FILE *File
+ IN EFI_FILE *File
)
{
- SEMIHOST_FCB *Fcb;
+ SEMIHOST_FCB *Fcb;
- Fcb = SEMIHOST_FCB_FROM_THIS(File);
+ Fcb = SEMIHOST_FCB_FROM_THIS (File);
if (Fcb->IsRoot) {
return EFI_SUCCESS;
} else {
- if ((Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
- || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE)) {
+ if ( (Fcb->Info.Attribute & EFI_FILE_READ_ONLY)
+ || !(Fcb->OpenMode & EFI_FILE_MODE_WRITE))
+ {
return EFI_ACCESS_DENIED;
} else {
return EFI_SUCCESS;
@@ -1176,11 +1201,11 @@ FileFlush ( EFI_STATUS
SemihostFsEntryPoint (
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = EFI_NOT_FOUND;
@@ -1192,12 +1217,14 @@ SemihostFsEntryPoint ( Status = gBS->InstallMultipleProtocolInterfaces (
&gInstallHandle,
- &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs,
- &gEfiDevicePathProtocolGuid, &gDevicePath,
+ &gEfiSimpleFileSystemProtocolGuid,
+ &gSemihostFs,
+ &gEfiDevicePathProtocolGuid,
+ &gDevicePath,
NULL
);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
FreePool (mSemihostFsLabel);
}
}
diff --git a/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h b/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h index 5fe7c5f4d4..a065e5b330 100644 --- a/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h +++ b/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h @@ -12,8 +12,8 @@ EFI_STATUS
VolumeOpen (
- IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
- OUT EFI_FILE **Root
+ IN EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,
+ OUT EFI_FILE **Root
);
/**
@@ -79,7 +79,7 @@ FileClose ( **/
EFI_STATUS
FileDelete (
- IN EFI_FILE *This
+ IN EFI_FILE *This
);
/**
@@ -127,9 +127,9 @@ FileRead ( **/
EFI_STATUS
FileWrite (
- IN EFI_FILE *This,
- IN OUT UINTN *BufferSize,
- IN VOID *Buffer
+ IN EFI_FILE *This,
+ IN OUT UINTN *BufferSize,
+ IN VOID *Buffer
);
/**
@@ -145,8 +145,8 @@ FileWrite ( **/
EFI_STATUS
FileGetPosition (
- IN EFI_FILE *File,
- OUT UINT64 *Position
+ IN EFI_FILE *File,
+ OUT UINT64 *Position
);
/**
@@ -164,8 +164,8 @@ FileGetPosition ( **/
EFI_STATUS
FileSetPosition (
- IN EFI_FILE *File,
- IN UINT64 Position
+ IN EFI_FILE *File,
+ IN UINT64 Position
);
/**
@@ -239,8 +239,7 @@ FileSetInfo ( EFI_STATUS
FileFlush (
- IN EFI_FILE *File
+ IN EFI_FILE *File
);
#endif // SEMIHOST_FS_H_
-
diff --git a/ArmPkg/Include/AsmMacroIoLib.h b/ArmPkg/Include/AsmMacroIoLib.h index 6c901ac387..2493a15b7b 100644 --- a/ArmPkg/Include/AsmMacroIoLib.h +++ b/ArmPkg/Include/AsmMacroIoLib.h @@ -9,7 +9,6 @@ **/
-
#ifndef ASM_MACRO_IO_LIB_H_
#define ASM_MACRO_IO_LIB_H_
@@ -20,7 +19,7 @@ .p2align 2 ; \
Name:
-#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define MOV32(Reg, Val) \
movw Reg, #(Val) & 0xffff ; \
diff --git a/ArmPkg/Include/AsmMacroIoLibV8.h b/ArmPkg/Include/AsmMacroIoLibV8.h index 337d9ae016..2c2b1cabd0 100644 --- a/ArmPkg/Include/AsmMacroIoLibV8.h +++ b/ArmPkg/Include/AsmMacroIoLibV8.h @@ -9,7 +9,6 @@ **/
-
#ifndef ASM_MACRO_IO_LIBV8_H_
#define ASM_MACRO_IO_LIBV8_H_
@@ -24,7 +23,6 @@ cbnz SAFE_XREG, 1f ;\
b . ;// We should never get here
-
// CurrentEL : 0xC = EL3; 8 = EL2; 4 = EL1
// This only selects between EL1 and EL2 and EL3, else we die.
// Provide the Macro with a safe temp xreg to use.
@@ -42,7 +40,7 @@ .type Name, %function ; \
Name:
-#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
#define MOV32(Reg, Val) \
movz Reg, (Val) >> 16, lsl #16 ; \
diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 10aeb9a15a..bfd2859f51 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -13,108 +13,108 @@ #include <Chipset/AArch64Mmu.h>
// ARM Interrupt ID in Exception Table
-#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_AARCH64_IRQ
// CPACR - Coprocessor Access Control Register definitions
-#define CPACR_TTA_EN (1UL << 28)
-#define CPACR_FPEN_EL1 (1UL << 20)
-#define CPACR_FPEN_FULL (3UL << 20)
-#define CPACR_CP_FULL_ACCESS 0x300000
+#define CPACR_TTA_EN (1UL << 28)
+#define CPACR_FPEN_EL1 (1UL << 20)
+#define CPACR_FPEN_FULL (3UL << 20)
+#define CPACR_CP_FULL_ACCESS 0x300000
// Coprocessor Trap Register (CPTR)
-#define AARCH64_CPTR_TFP (1 << 10)
+#define AARCH64_CPTR_TFP (1 << 10)
// ID_AA64PFR0 - AArch64 Processor Feature Register 0 definitions
-#define AARCH64_PFR0_FP (0xF << 16)
-#define AARCH64_PFR0_GIC (0xF << 24)
+#define AARCH64_PFR0_FP (0xF << 16)
+#define AARCH64_PFR0_GIC (0xF << 24)
// SCR - Secure Configuration Register definitions
-#define SCR_NS (1 << 0)
-#define SCR_IRQ (1 << 1)
-#define SCR_FIQ (1 << 2)
-#define SCR_EA (1 << 3)
-#define SCR_FW (1 << 4)
-#define SCR_AW (1 << 5)
+#define SCR_NS (1 << 0)
+#define SCR_IRQ (1 << 1)
+#define SCR_FIQ (1 << 2)
+#define SCR_EA (1 << 3)
+#define SCR_FW (1 << 4)
+#define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
-#define ARM_CPU_TYPE_SHIFT 4
-#define ARM_CPU_TYPE_MASK 0xFFF
-#define ARM_CPU_TYPE_AEMV8 0xD0F
-#define ARM_CPU_TYPE_A53 0xD03
-#define ARM_CPU_TYPE_A57 0xD07
-#define ARM_CPU_TYPE_A72 0xD08
-#define ARM_CPU_TYPE_A15 0xC0F
-#define ARM_CPU_TYPE_A9 0xC09
-#define ARM_CPU_TYPE_A7 0xC07
-#define ARM_CPU_TYPE_A5 0xC05
-
-#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
-#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+#define ARM_CPU_TYPE_SHIFT 4
+#define ARM_CPU_TYPE_MASK 0xFFF
+#define ARM_CPU_TYPE_AEMV8 0xD0F
+#define ARM_CPU_TYPE_A53 0xD03
+#define ARM_CPU_TYPE_A57 0xD07
+#define ARM_CPU_TYPE_A72 0xD08
+#define ARM_CPU_TYPE_A15 0xC0F
+#define ARM_CPU_TYPE_A9 0xC09
+#define ARM_CPU_TYPE_A7 0xC07
+#define ARM_CPU_TYPE_A5 0xC05
+
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
// Hypervisor Configuration Register
-#define ARM_HCR_FMO BIT3
-#define ARM_HCR_IMO BIT4
-#define ARM_HCR_AMO BIT5
-#define ARM_HCR_TSC BIT19
-#define ARM_HCR_TGE BIT27
+#define ARM_HCR_FMO BIT3
+#define ARM_HCR_IMO BIT4
+#define ARM_HCR_AMO BIT5
+#define ARM_HCR_TSC BIT19
+#define ARM_HCR_TGE BIT27
// Exception Syndrome Register
-#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
-#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
+#define AARCH64_ESR_EC(Ecr) ((0x3F << 26) & (Ecr))
+#define AARCH64_ESR_ISS(Ecr) ((0x1FFFFFF) & (Ecr))
-#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
-#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
+#define AARCH64_ESR_EC_SMC32 (0x13 << 26)
+#define AARCH64_ESR_EC_SMC64 (0x17 << 26)
// AArch64 Exception Level
-#define AARCH64_EL3 0xC
-#define AARCH64_EL2 0x8
-#define AARCH64_EL1 0x4
+#define AARCH64_EL3 0xC
+#define AARCH64_EL2 0x8
+#define AARCH64_EL1 0x4
// Saved Program Status Register definitions
-#define SPSR_A BIT8
-#define SPSR_I BIT7
-#define SPSR_F BIT6
+#define SPSR_A BIT8
+#define SPSR_I BIT7
+#define SPSR_F BIT6
-#define SPSR_AARCH32 BIT4
+#define SPSR_AARCH32 BIT4
-#define SPSR_AARCH32_MODE_USER 0x0
-#define SPSR_AARCH32_MODE_FIQ 0x1
-#define SPSR_AARCH32_MODE_IRQ 0x2
-#define SPSR_AARCH32_MODE_SVC 0x3
-#define SPSR_AARCH32_MODE_ABORT 0x7
-#define SPSR_AARCH32_MODE_UNDEF 0xB
-#define SPSR_AARCH32_MODE_SYS 0xF
+#define SPSR_AARCH32_MODE_USER 0x0
+#define SPSR_AARCH32_MODE_FIQ 0x1
+#define SPSR_AARCH32_MODE_IRQ 0x2
+#define SPSR_AARCH32_MODE_SVC 0x3
+#define SPSR_AARCH32_MODE_ABORT 0x7
+#define SPSR_AARCH32_MODE_UNDEF 0xB
+#define SPSR_AARCH32_MODE_SYS 0xF
// Counter-timer Hypervisor Control register definitions
-#define CNTHCTL_EL2_EL1PCTEN BIT0
-#define CNTHCTL_EL2_EL1PCEN BIT1
+#define CNTHCTL_EL2_EL1PCTEN BIT0
+#define CNTHCTL_EL2_EL1PCEN BIT1
-#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1)
// Vector table offset definitions
-#define ARM_VECTOR_CUR_SP0_SYNC 0x000
-#define ARM_VECTOR_CUR_SP0_IRQ 0x080
-#define ARM_VECTOR_CUR_SP0_FIQ 0x100
-#define ARM_VECTOR_CUR_SP0_SERR 0x180
-
-#define ARM_VECTOR_CUR_SPX_SYNC 0x200
-#define ARM_VECTOR_CUR_SPX_IRQ 0x280
-#define ARM_VECTOR_CUR_SPX_FIQ 0x300
-#define ARM_VECTOR_CUR_SPX_SERR 0x380
-
-#define ARM_VECTOR_LOW_A64_SYNC 0x400
-#define ARM_VECTOR_LOW_A64_IRQ 0x480
-#define ARM_VECTOR_LOW_A64_FIQ 0x500
-#define ARM_VECTOR_LOW_A64_SERR 0x580
-
-#define ARM_VECTOR_LOW_A32_SYNC 0x600
-#define ARM_VECTOR_LOW_A32_IRQ 0x680
-#define ARM_VECTOR_LOW_A32_FIQ 0x700
-#define ARM_VECTOR_LOW_A32_SERR 0x780
+#define ARM_VECTOR_CUR_SP0_SYNC 0x000
+#define ARM_VECTOR_CUR_SP0_IRQ 0x080
+#define ARM_VECTOR_CUR_SP0_FIQ 0x100
+#define ARM_VECTOR_CUR_SP0_SERR 0x180
+
+#define ARM_VECTOR_CUR_SPX_SYNC 0x200
+#define ARM_VECTOR_CUR_SPX_IRQ 0x280
+#define ARM_VECTOR_CUR_SPX_FIQ 0x300
+#define ARM_VECTOR_CUR_SPX_SERR 0x380
+
+#define ARM_VECTOR_LOW_A64_SYNC 0x400
+#define ARM_VECTOR_LOW_A64_IRQ 0x480
+#define ARM_VECTOR_LOW_A64_FIQ 0x500
+#define ARM_VECTOR_LOW_A64_SERR 0x580
+
+#define ARM_VECTOR_LOW_A32_SYNC 0x600
+#define ARM_VECTOR_LOW_A32_IRQ 0x680
+#define ARM_VECTOR_LOW_A32_FIQ 0x700
+#define ARM_VECTOR_LOW_A32_SERR 0x780
// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we
// build for ARMv8.0, we need to define the register here.
-#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
+#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
#define VECTOR_BASE(tbl) \
.section .text.##tbl##,"ax"; \
@@ -151,7 +151,7 @@ ArmReadTpidrurw ( VOID
EFIAPI
ArmWriteTpidrurw (
- UINTN Value
+ UINTN Value
);
UINTN
@@ -163,7 +163,7 @@ ArmGetTCR ( VOID
EFIAPI
ArmSetTCR (
- UINTN Value
+ UINTN Value
);
UINTN
@@ -175,7 +175,7 @@ ArmGetMAIR ( VOID
EFIAPI
ArmSetMAIR (
- UINTN Value
+ UINTN Value
);
VOID
@@ -210,7 +210,7 @@ ArmDisableAllExceptions ( VOID
ArmWriteHcr (
- IN UINTN Hcr
+ IN UINTN Hcr
);
UINTN
@@ -225,7 +225,7 @@ ArmReadCurrentEL ( UINTN
ArmWriteCptr (
- IN UINT64 Cptr
+ IN UINT64 Cptr
);
UINT32
@@ -235,7 +235,7 @@ ArmReadCntHctl ( VOID
ArmWriteCntHctl (
- IN UINT32 CntHctl
+ IN UINT32 CntHctl
);
#endif // AARCH64_H_
diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h index fe38ba1c50..2ea2cc0a87 100644 --- a/ArmPkg/Include/Chipset/AArch64Mmu.h +++ b/ArmPkg/Include/Chipset/AArch64Mmu.h @@ -12,12 +12,12 @@ //
// Memory Attribute Indirection register Definitions
//
-#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
-#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
-#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
-#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
+#define MAIR_ATTR_DEVICE_MEMORY 0x0ULL
+#define MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE 0x44ULL
+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH 0xBBULL
+#define MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK 0xFFULL
-#define MAIR_ATTR(n,value) ((value) << (((n) >> 2)*8))
+#define MAIR_ATTR(n, value) ((value) << (((n) >> 2)*8))
//
// Long-descriptor Translation Table format
@@ -27,7 +27,7 @@ // The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
#define TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel) (12 + ((3 - (TableLevel)) * 9))
-#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
+#define TT_BLOCK_ENTRY_SIZE_AT_LEVEL(Level) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(Level))
// Get the associated entry in the given Translation Table
#define TT_GET_ENTRY_FOR_ADDRESS(TranslationTable, Level, Address) \
@@ -35,164 +35,161 @@ // Return the smallest address granularity from the table level.
// The first offset starts at 12bit. There are 4 levels of 9-bit address range from level 3 to level 0
-#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
+#define TT_ADDRESS_AT_LEVEL(TableLevel) (1ULL << TT_ADDRESS_OFFSET_AT_LEVEL(TableLevel))
#define TT_LAST_BLOCK_ADDRESS(TranslationTable, EntryCount) \
((UINT64*)((EFI_PHYSICAL_ADDRESS)(TranslationTable) + (((EntryCount) - 1) * sizeof(UINT64))))
// There are 512 entries per table when 4K Granularity
-#define TT_ENTRY_COUNT 512
-#define TT_ALIGNMENT_BLOCK_ENTRY BIT12
-#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
-
-#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
-#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
-
-#define TT_TYPE_MASK 0x3
-#define TT_TYPE_TABLE_ENTRY 0x3
-#define TT_TYPE_BLOCK_ENTRY 0x1
-#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
-
-#define TT_ATTR_INDX_MASK (0x7 << 2)
-#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
-#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
-#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
-#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
-
-#define TT_AP_MASK (0x3UL << 6)
-#define TT_AP_NO_RW (0x0UL << 6)
-#define TT_AP_RW_RW (0x1UL << 6)
-#define TT_AP_NO_RO (0x2UL << 6)
-#define TT_AP_RO_RO (0x3UL << 6)
-
-#define TT_NS BIT5
-#define TT_AF BIT10
-
-#define TT_SH_NON_SHAREABLE (0x0 << 8)
-#define TT_SH_OUTER_SHAREABLE (0x2 << 8)
-#define TT_SH_INNER_SHAREABLE (0x3 << 8)
-#define TT_SH_MASK (0x3 << 8)
-
-#define TT_PXN_MASK BIT53
-#define TT_UXN_MASK BIT54 // EL1&0
-#define TT_XN_MASK BIT54 // EL2 / EL3
-
-#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
-
-#define TT_TABLE_PXN BIT59
-#define TT_TABLE_UXN BIT60 // EL1&0
-#define TT_TABLE_XN BIT60 // EL2 / EL3
-#define TT_TABLE_NS BIT63
-
-#define TT_TABLE_AP_MASK (BIT62 | BIT61)
-#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
-#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
-#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
+#define TT_ENTRY_COUNT 512
+#define TT_ALIGNMENT_BLOCK_ENTRY BIT12
+#define TT_ALIGNMENT_DESCRIPTION_TABLE BIT12
+
+#define TT_ADDRESS_MASK_BLOCK_ENTRY (0xFFFFFFFFFULL << 12)
+#define TT_ADDRESS_MASK_DESCRIPTION_TABLE (0xFFFFFFFFFULL << 12)
+
+#define TT_TYPE_MASK 0x3
+#define TT_TYPE_TABLE_ENTRY 0x3
+#define TT_TYPE_BLOCK_ENTRY 0x1
+#define TT_TYPE_BLOCK_ENTRY_LEVEL3 0x3
+
+#define TT_ATTR_INDX_MASK (0x7 << 2)
+#define TT_ATTR_INDX_DEVICE_MEMORY (0x0 << 2)
+#define TT_ATTR_INDX_MEMORY_NON_CACHEABLE (0x1 << 2)
+#define TT_ATTR_INDX_MEMORY_WRITE_THROUGH (0x2 << 2)
+#define TT_ATTR_INDX_MEMORY_WRITE_BACK (0x3 << 2)
+
+#define TT_AP_MASK (0x3UL << 6)
+#define TT_AP_NO_RW (0x0UL << 6)
+#define TT_AP_RW_RW (0x1UL << 6)
+#define TT_AP_NO_RO (0x2UL << 6)
+#define TT_AP_RO_RO (0x3UL << 6)
+
+#define TT_NS BIT5
+#define TT_AF BIT10
+
+#define TT_SH_NON_SHAREABLE (0x0 << 8)
+#define TT_SH_OUTER_SHAREABLE (0x2 << 8)
+#define TT_SH_INNER_SHAREABLE (0x3 << 8)
+#define TT_SH_MASK (0x3 << 8)
+
+#define TT_PXN_MASK BIT53
+#define TT_UXN_MASK BIT54 // EL1&0
+#define TT_XN_MASK BIT54 // EL2 / EL3
+
+#define TT_ATTRIBUTES_MASK ((0xFFFULL << 52) | (0x3FFULL << 2))
+
+#define TT_TABLE_PXN BIT59
+#define TT_TABLE_UXN BIT60 // EL1&0
+#define TT_TABLE_XN BIT60 // EL2 / EL3
+#define TT_TABLE_NS BIT63
+
+#define TT_TABLE_AP_MASK (BIT62 | BIT61)
+#define TT_TABLE_AP_NO_PERMISSION (0x0ULL << 61)
+#define TT_TABLE_AP_EL0_NO_ACCESS (0x1ULL << 61)
+#define TT_TABLE_AP_NO_WRITE_ACCESS (0x2ULL << 61)
//
// Translation Control Register
//
-#define TCR_T0SZ_MASK 0x3FUL
-
-#define TCR_PS_4GB (0UL << 16)
-#define TCR_PS_64GB (1UL << 16)
-#define TCR_PS_1TB (2UL << 16)
-#define TCR_PS_4TB (3UL << 16)
-#define TCR_PS_16TB (4UL << 16)
-#define TCR_PS_256TB (5UL << 16)
-
-#define TCR_TG0_4KB (0UL << 14)
-#define TCR_TG1_4KB (2UL << 30)
-
-#define TCR_IPS_4GB (0ULL << 32)
-#define TCR_IPS_64GB (1ULL << 32)
-#define TCR_IPS_1TB (2ULL << 32)
-#define TCR_IPS_4TB (3ULL << 32)
-#define TCR_IPS_16TB (4ULL << 32)
-#define TCR_IPS_256TB (5ULL << 32)
-
-#define TCR_EPD1 (1UL << 23)
-
-#define TTBR_ASID_FIELD (48)
-#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
-#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
-
-#define TCR_EL1_T0SZ_FIELD (0)
-#define TCR_EL1_EPD0_FIELD (7)
-#define TCR_EL1_IRGN0_FIELD (8)
-#define TCR_EL1_ORGN0_FIELD (10)
-#define TCR_EL1_SH0_FIELD (12)
-#define TCR_EL1_TG0_FIELD (14)
-#define TCR_EL1_T1SZ_FIELD (16)
-#define TCR_EL1_A1_FIELD (22)
-#define TCR_EL1_EPD1_FIELD (23)
-#define TCR_EL1_IRGN1_FIELD (24)
-#define TCR_EL1_ORGN1_FIELD (26)
-#define TCR_EL1_SH1_FIELD (28)
-#define TCR_EL1_TG1_FIELD (30)
-#define TCR_EL1_IPS_FIELD (32)
-#define TCR_EL1_AS_FIELD (36)
-#define TCR_EL1_TBI0_FIELD (37)
-#define TCR_EL1_TBI1_FIELD (38)
-#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
-#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
-#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
-#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
-#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
-#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
-#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
-#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
-#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
-#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
-#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
-#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
-#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
-#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
-#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
-#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
-#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
-
-
-#define TCR_EL23_T0SZ_FIELD (0)
-#define TCR_EL23_IRGN0_FIELD (8)
-#define TCR_EL23_ORGN0_FIELD (10)
-#define TCR_EL23_SH0_FIELD (12)
-#define TCR_EL23_TG0_FIELD (14)
-#define TCR_EL23_PS_FIELD (16)
-#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
-#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
-#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
-#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
-#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
-#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
-
-
-#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
-#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
-#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
-#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
-
-#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
-#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
-#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
-#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
-
-#define TCR_SH_NON_SHAREABLE (0x0UL << 12)
-#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
-#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
-
-#define TCR_PASZ_32BITS_4GB (0x0UL)
-#define TCR_PASZ_36BITS_64GB (0x1UL)
-#define TCR_PASZ_40BITS_1TB (0x2UL)
-#define TCR_PASZ_42BITS_4TB (0x3UL)
-#define TCR_PASZ_44BITS_16TB (0x4UL)
-#define TCR_PASZ_48BITS_256TB (0x5UL)
+#define TCR_T0SZ_MASK 0x3FUL
+
+#define TCR_PS_4GB (0UL << 16)
+#define TCR_PS_64GB (1UL << 16)
+#define TCR_PS_1TB (2UL << 16)
+#define TCR_PS_4TB (3UL << 16)
+#define TCR_PS_16TB (4UL << 16)
+#define TCR_PS_256TB (5UL << 16)
+
+#define TCR_TG0_4KB (0UL << 14)
+#define TCR_TG1_4KB (2UL << 30)
+
+#define TCR_IPS_4GB (0ULL << 32)
+#define TCR_IPS_64GB (1ULL << 32)
+#define TCR_IPS_1TB (2ULL << 32)
+#define TCR_IPS_4TB (3ULL << 32)
+#define TCR_IPS_16TB (4ULL << 32)
+#define TCR_IPS_256TB (5ULL << 32)
+
+#define TCR_EPD1 (1UL << 23)
+
+#define TTBR_ASID_FIELD (48)
+#define TTBR_ASID_MASK (0xFF << TTBR_ASID_FIELD)
+#define TTBR_BADDR_MASK (0xFFFFFFFFFFFF ) // The width of this field depends on the values in TxSZ. Addr occupies bottom 48bits
+
+#define TCR_EL1_T0SZ_FIELD (0)
+#define TCR_EL1_EPD0_FIELD (7)
+#define TCR_EL1_IRGN0_FIELD (8)
+#define TCR_EL1_ORGN0_FIELD (10)
+#define TCR_EL1_SH0_FIELD (12)
+#define TCR_EL1_TG0_FIELD (14)
+#define TCR_EL1_T1SZ_FIELD (16)
+#define TCR_EL1_A1_FIELD (22)
+#define TCR_EL1_EPD1_FIELD (23)
+#define TCR_EL1_IRGN1_FIELD (24)
+#define TCR_EL1_ORGN1_FIELD (26)
+#define TCR_EL1_SH1_FIELD (28)
+#define TCR_EL1_TG1_FIELD (30)
+#define TCR_EL1_IPS_FIELD (32)
+#define TCR_EL1_AS_FIELD (36)
+#define TCR_EL1_TBI0_FIELD (37)
+#define TCR_EL1_TBI1_FIELD (38)
+#define TCR_EL1_T0SZ_MASK (0x1FUL << TCR_EL1_T0SZ_FIELD)
+#define TCR_EL1_EPD0_MASK (0x01UL << TCR_EL1_EPD0_FIELD)
+#define TCR_EL1_IRGN0_MASK (0x03UL << TCR_EL1_IRGN0_FIELD)
+#define TCR_EL1_ORGN0_MASK (0x03UL << TCR_EL1_ORGN0_FIELD)
+#define TCR_EL1_SH0_MASK (0x03UL << TCR_EL1_SH0_FIELD)
+#define TCR_EL1_TG0_MASK (0x01UL << TCR_EL1_TG0_FIELD)
+#define TCR_EL1_T1SZ_MASK (0x1FUL << TCR_EL1_T1SZ_FIELD)
+#define TCR_EL1_A1_MASK (0x01UL << TCR_EL1_A1_FIELD)
+#define TCR_EL1_EPD1_MASK (0x01UL << TCR_EL1_EPD1_FIELD)
+#define TCR_EL1_IRGN1_MASK (0x03UL << TCR_EL1_IRGN1_FIELD)
+#define TCR_EL1_ORGN1_MASK (0x03UL << TCR_EL1_ORGN1_FIELD)
+#define TCR_EL1_SH1_MASK (0x03UL << TCR_EL1_SH1_FIELD)
+#define TCR_EL1_TG1_MASK (0x01UL << TCR_EL1_TG1_FIELD)
+#define TCR_EL1_IPS_MASK (0x07UL << TCR_EL1_IPS_FIELD)
+#define TCR_EL1_AS_MASK (0x01UL << TCR_EL1_AS_FIELD)
+#define TCR_EL1_TBI0_MASK (0x01UL << TCR_EL1_TBI0_FIELD)
+#define TCR_EL1_TBI1_MASK (0x01UL << TCR_EL1_TBI1_FIELD)
+
+#define TCR_EL23_T0SZ_FIELD (0)
+#define TCR_EL23_IRGN0_FIELD (8)
+#define TCR_EL23_ORGN0_FIELD (10)
+#define TCR_EL23_SH0_FIELD (12)
+#define TCR_EL23_TG0_FIELD (14)
+#define TCR_EL23_PS_FIELD (16)
+#define TCR_EL23_T0SZ_MASK (0x1FUL << TCR_EL23_T0SZ_FIELD)
+#define TCR_EL23_IRGN0_MASK (0x03UL << TCR_EL23_IRGN0_FIELD)
+#define TCR_EL23_ORGN0_MASK (0x03UL << TCR_EL23_ORGN0_FIELD)
+#define TCR_EL23_SH0_MASK (0x03UL << TCR_EL23_SH0_FIELD)
+#define TCR_EL23_TG0_MASK (0x01UL << TCR_EL23_TG0_FIELD)
+#define TCR_EL23_PS_MASK (0x07UL << TCR_EL23_PS_FIELD)
+
+#define TCR_RGN_OUTER_NON_CACHEABLE (0x0UL << 10)
+#define TCR_RGN_OUTER_WRITE_BACK_ALLOC (0x1UL << 10)
+#define TCR_RGN_OUTER_WRITE_THROUGH (0x2UL << 10)
+#define TCR_RGN_OUTER_WRITE_BACK_NO_ALLOC (0x3UL << 10)
+
+#define TCR_RGN_INNER_NON_CACHEABLE (0x0UL << 8)
+#define TCR_RGN_INNER_WRITE_BACK_ALLOC (0x1UL << 8)
+#define TCR_RGN_INNER_WRITE_THROUGH (0x2UL << 8)
+#define TCR_RGN_INNER_WRITE_BACK_NO_ALLOC (0x3UL << 8)
+
+#define TCR_SH_NON_SHAREABLE (0x0UL << 12)
+#define TCR_SH_OUTER_SHAREABLE (0x2UL << 12)
+#define TCR_SH_INNER_SHAREABLE (0x3UL << 12)
+
+#define TCR_PASZ_32BITS_4GB (0x0UL)
+#define TCR_PASZ_36BITS_64GB (0x1UL)
+#define TCR_PASZ_40BITS_1TB (0x2UL)
+#define TCR_PASZ_42BITS_4TB (0x3UL)
+#define TCR_PASZ_44BITS_16TB (0x4UL)
+#define TCR_PASZ_48BITS_256TB (0x5UL)
// The value written to the T*SZ fields are defined as 2^(64-T*SZ). So a 39Bit
// Virtual address range for 512GB of virtual space sets T*SZ to 25
-#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
+#define INPUT_ADDRESS_SIZE_TO_TXSZ(a) (64 - a)
// Uses LPAE Page Table format
#endif // AARCH64_MMU_H_
-
diff --git a/ArmPkg/Include/Chipset/ArmCortexA5x.h b/ArmPkg/Include/Chipset/ArmCortexA5x.h index e597eee947..cc8b23b964 100644 --- a/ArmPkg/Include/Chipset/ArmCortexA5x.h +++ b/ArmPkg/Include/Chipset/ArmCortexA5x.h @@ -12,7 +12,7 @@ //
// Cortex A5x feature bit definitions
//
-#define A5X_FEATURE_SMP (1 << 6)
+#define A5X_FEATURE_SMP (1 << 6)
//
// Helper functions to access CPU Extended Control Register
@@ -26,19 +26,19 @@ ArmReadCpuExCr ( VOID
EFIAPI
ArmWriteCpuExCr (
- IN UINT64 Val
+ IN UINT64 Val
);
VOID
EFIAPI
ArmSetCpuExCrBit (
- IN UINT64 Bits
+ IN UINT64 Bits
);
VOID
EFIAPI
ArmUnsetCpuExCrBit (
- IN UINT64 Bits
+ IN UINT64 Bits
);
#endif // ARM_CORTEX_A5X_H_
diff --git a/ArmPkg/Include/Chipset/ArmCortexA9.h b/ArmPkg/Include/Chipset/ArmCortexA9.h index cb937ebc8c..a89aeebd4a 100644 --- a/ArmPkg/Include/Chipset/ArmCortexA9.h +++ b/ArmPkg/Include/Chipset/ArmCortexA9.h @@ -26,28 +26,27 @@ //
// Cortex A9 Watchdog
//
-#define ARM_A9_WATCHDOG_REGION 0x600
+#define ARM_A9_WATCHDOG_REGION 0x600
-#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20
-#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28
+#define ARM_A9_WATCHDOG_LOAD_REGISTER 0x20
+#define ARM_A9_WATCHDOG_CONTROL_REGISTER 0x28
-#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)
-#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)
-#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)
-#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)
-#define ARM_A9_WATCHDOG_ENABLE 1
+#define ARM_A9_WATCHDOG_WATCHDOG_MODE (1 << 3)
+#define ARM_A9_WATCHDOG_TIMER_MODE (0 << 3)
+#define ARM_A9_WATCHDOG_SINGLE_SHOT (0 << 1)
+#define ARM_A9_WATCHDOG_AUTORELOAD (1 << 1)
+#define ARM_A9_WATCHDOG_ENABLE 1
//
// SCU register offsets & masks
//
-#define A9_SCU_CONTROL_OFFSET 0x0
-#define A9_SCU_CONFIG_OFFSET 0x4
-#define A9_SCU_INVALL_OFFSET 0xC
-#define A9_SCU_FILT_START_OFFSET 0x40
-#define A9_SCU_FILT_END_OFFSET 0x44
-#define A9_SCU_SACR_OFFSET 0x50
-#define A9_SCU_SSACR_OFFSET 0x54
-
+#define A9_SCU_CONTROL_OFFSET 0x0
+#define A9_SCU_CONFIG_OFFSET 0x4
+#define A9_SCU_INVALL_OFFSET 0xC
+#define A9_SCU_FILT_START_OFFSET 0x40
+#define A9_SCU_FILT_END_OFFSET 0x44
+#define A9_SCU_SACR_OFFSET 0x50
+#define A9_SCU_SSACR_OFFSET 0x54
UINTN
EFIAPI
@@ -56,4 +55,3 @@ ArmGetScuBaseAddress ( );
#endif // ARM_CORTEX_A9_H_
-
diff --git a/ArmPkg/Include/Chipset/ArmV7.h b/ArmPkg/Include/Chipset/ArmV7.h index 6b20b988e3..94620c087d 100644 --- a/ArmPkg/Include/Chipset/ArmV7.h +++ b/ArmPkg/Include/Chipset/ArmV7.h @@ -13,19 +13,19 @@ #include <Chipset/ArmV7Mmu.h>
// ARM Interrupt ID in Exception Table
-#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
+#define ARM_ARCH_EXCEPTION_IRQ EXCEPT_ARM_IRQ
// ID_PFR1 - ARM Processor Feature Register 1 definitions
-#define ARM_PFR1_SEC (0xFUL << 4)
-#define ARM_PFR1_TIMER (0xFUL << 16)
-#define ARM_PFR1_GIC (0xFUL << 28)
+#define ARM_PFR1_SEC (0xFUL << 4)
+#define ARM_PFR1_TIMER (0xFUL << 16)
+#define ARM_PFR1_GIC (0xFUL << 28)
// Domain Access Control Register
-#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
-#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MASK(a) (3UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_NONE(a) (0UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a) (1UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a) (3UL << (2 * (a)))
// CPSR - Coprocessor Status Register definitions
#define CPSR_MODE_USER 0x10
@@ -41,48 +41,47 @@ #define CPSR_IRQ (1 << 7)
#define CPSR_FIQ (1 << 6)
-
// CPACR - Coprocessor Access Control Register definitions
-#define CPACR_CP_DENIED(cp) 0x00
-#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
-#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
-#define CPACR_ASEDIS (1 << 31)
-#define CPACR_D32DIS (1 << 30)
-#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
+#define CPACR_CP_DENIED(cp) 0x00
+#define CPACR_CP_PRIV(cp) ((0x1 << ((cp) << 1)) & 0x0FFFFFFF)
+#define CPACR_CP_FULL(cp) ((0x3 << ((cp) << 1)) & 0x0FFFFFFF)
+#define CPACR_ASEDIS (1 << 31)
+#define CPACR_D32DIS (1 << 30)
+#define CPACR_CP_FULL_ACCESS 0x0FFFFFFF
// NSACR - Non-Secure Access Control Register definitions
-#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
-#define NSACR_NSD32DIS (1 << 14)
-#define NSACR_NSASEDIS (1 << 15)
-#define NSACR_PLE (1 << 16)
-#define NSACR_TL (1 << 17)
-#define NSACR_NS_SMP (1 << 18)
-#define NSACR_RFR (1 << 19)
+#define NSACR_CP(cp) ((1 << (cp)) & 0x3FFF)
+#define NSACR_NSD32DIS (1 << 14)
+#define NSACR_NSASEDIS (1 << 15)
+#define NSACR_PLE (1 << 16)
+#define NSACR_TL (1 << 17)
+#define NSACR_NS_SMP (1 << 18)
+#define NSACR_RFR (1 << 19)
// SCR - Secure Configuration Register definitions
-#define SCR_NS (1 << 0)
-#define SCR_IRQ (1 << 1)
-#define SCR_FIQ (1 << 2)
-#define SCR_EA (1 << 3)
-#define SCR_FW (1 << 4)
-#define SCR_AW (1 << 5)
+#define SCR_NS (1 << 0)
+#define SCR_IRQ (1 << 1)
+#define SCR_FIQ (1 << 2)
+#define SCR_EA (1 << 3)
+#define SCR_FW (1 << 4)
+#define SCR_AW (1 << 5)
// MIDR - Main ID Register definitions
-#define ARM_CPU_TYPE_SHIFT 4
-#define ARM_CPU_TYPE_MASK 0xFFF
-#define ARM_CPU_TYPE_AEMV8 0xD0F
-#define ARM_CPU_TYPE_A53 0xD03
-#define ARM_CPU_TYPE_A57 0xD07
-#define ARM_CPU_TYPE_A15 0xC0F
-#define ARM_CPU_TYPE_A12 0xC0D
-#define ARM_CPU_TYPE_A9 0xC09
-#define ARM_CPU_TYPE_A7 0xC07
-#define ARM_CPU_TYPE_A5 0xC05
-
-#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
-#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
-
-#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
+#define ARM_CPU_TYPE_SHIFT 4
+#define ARM_CPU_TYPE_MASK 0xFFF
+#define ARM_CPU_TYPE_AEMV8 0xD0F
+#define ARM_CPU_TYPE_A53 0xD03
+#define ARM_CPU_TYPE_A57 0xD07
+#define ARM_CPU_TYPE_A15 0xC0F
+#define ARM_CPU_TYPE_A12 0xC0D
+#define ARM_CPU_TYPE_A9 0xC09
+#define ARM_CPU_TYPE_A7 0xC07
+#define ARM_CPU_TYPE_A5 0xC05
+
+#define ARM_CPU_REV_MASK ((0xF << 20) | (0xF) )
+#define ARM_CPU_REV(rn, pn) ((((rn) & 0xF) << 20) | ((pn) & 0xF))
+
+#define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 5)-1)
VOID
EFIAPI
@@ -105,7 +104,7 @@ ArmReadTpidrurw ( VOID
EFIAPI
ArmWriteTpidrurw (
- UINTN Value
+ UINTN Value
);
UINT32
@@ -117,7 +116,7 @@ ArmReadNsacr ( VOID
EFIAPI
ArmWriteNsacr (
- IN UINT32 Nsacr
+ IN UINT32 Nsacr
);
#endif // ARM_V7_H_
diff --git a/ArmPkg/Include/Chipset/ArmV7Mmu.h b/ArmPkg/Include/Chipset/ArmV7Mmu.h index 87c443df3f..db99527d6e 100644 --- a/ArmPkg/Include/Chipset/ArmV7Mmu.h +++ b/ArmPkg/Include/Chipset/ArmV7Mmu.h @@ -9,183 +9,182 @@ #ifndef ARMV7_MMU_H_
#define ARMV7_MMU_H_
-#define TTBR_NOT_OUTER_SHAREABLE BIT5
-#define TTBR_RGN_OUTER_NON_CACHEABLE 0
-#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
-#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
-#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
-#define TTBR_SHAREABLE BIT1
-#define TTBR_NON_SHAREABLE 0
-#define TTBR_INNER_CACHEABLE BIT0
-#define TTBR_INNER_NON_CACHEABLE 0
-#define TTBR_RGN_INNER_NON_CACHEABLE 0
-#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
-#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
-#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
-
-#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
-#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
-#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
-#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
-
-#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
-#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
-#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
-#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
-
-
-#define TRANSLATION_TABLE_SECTION_COUNT 4096
-#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
-#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
-#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
-
-#define TRANSLATION_TABLE_PAGE_COUNT 256
-#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
-#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
-#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
-
-#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
+#define TTBR_NOT_OUTER_SHAREABLE BIT5
+#define TTBR_RGN_OUTER_NON_CACHEABLE 0
+#define TTBR_RGN_OUTER_WRITE_BACK_ALLOC BIT3
+#define TTBR_RGN_OUTER_WRITE_THROUGH BIT4
+#define TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC (BIT3|BIT4)
+#define TTBR_SHAREABLE BIT1
+#define TTBR_NON_SHAREABLE 0
+#define TTBR_INNER_CACHEABLE BIT0
+#define TTBR_INNER_NON_CACHEABLE 0
+#define TTBR_RGN_INNER_NON_CACHEABLE 0
+#define TTBR_RGN_INNER_WRITE_BACK_ALLOC BIT6
+#define TTBR_RGN_INNER_WRITE_THROUGH BIT0
+#define TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC (BIT0|BIT6)
+
+#define TTBR_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+#define TTBR_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+#define TTBR_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_INNER_NON_CACHEABLE )
+#define TTBR_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_INNER_CACHEABLE | TTBR_SHAREABLE)
+
+#define TTBR_MP_WRITE_THROUGH ( TTBR_RGN_OUTER_WRITE_THROUGH | TTBR_RGN_INNER_WRITE_THROUGH | TTBR_SHAREABLE)
+#define TTBR_MP_WRITE_BACK_NO_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_NO_ALLOC | TTBR_RGN_INNER_WRITE_BACK_NO_ALLOC | TTBR_SHAREABLE)
+#define TTBR_MP_NON_CACHEABLE ( TTBR_RGN_OUTER_NON_CACHEABLE | TTBR_RGN_INNER_NON_CACHEABLE )
+#define TTBR_MP_WRITE_BACK_ALLOC ( TTBR_RGN_OUTER_WRITE_BACK_ALLOC | TTBR_RGN_INNER_WRITE_BACK_ALLOC | TTBR_SHAREABLE)
+
+#define TRANSLATION_TABLE_SECTION_COUNT 4096
+#define TRANSLATION_TABLE_SECTION_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
+#define TRANSLATION_TABLE_SECTION_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_SECTION_COUNT)
+#define TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK (TRANSLATION_TABLE_SECTION_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_PAGE_COUNT 256
+#define TRANSLATION_TABLE_PAGE_SIZE (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
+#define TRANSLATION_TABLE_PAGE_ALIGNMENT (sizeof(UINT32) * TRANSLATION_TABLE_PAGE_COUNT)
+#define TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK (TRANSLATION_TABLE_PAGE_ALIGNMENT - 1)
+
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))
// Translation table descriptor types
-#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
-#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
-#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
-#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
-#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
-#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
+#define TT_DESCRIPTOR_SECTION_TYPE_MASK ((1UL << 18) | (3UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_FAULT (0UL << 0)
+#define TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE (1UL << 0)
+#define TT_DESCRIPTOR_SECTION_TYPE_SECTION ((0UL << 18) | (2UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))
+#define TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Desc) (((Desc) & 3UL) == TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE)
// Translation table descriptor types
-#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
-#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_MASK (3UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_FAULT (0UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE (2UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN (3UL << 0)
+#define TT_DESCRIPTOR_PAGE_TYPE_LARGEPAGE (1UL << 0)
// Section descriptor definitions
-#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
-
-#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
-#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
-
-#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
-#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
-#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
-
-#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
-#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
-#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
-
-#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
-#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
-#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
-
-#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
-#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
-#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
-
-#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
-#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
-
-#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
-#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
-
-#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
-#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
-#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
-
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
-
-#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
-
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_SIZE (0x00100000)
+
+#define TT_DESCRIPTOR_SECTION_NS_MASK (1UL << 19)
+#define TT_DESCRIPTOR_SECTION_NS (1UL << 19)
+
+#define TT_DESCRIPTOR_SECTION_NG_MASK (1UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL (0UL << 17)
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL (1UL << 17)
+
+#define TT_DESCRIPTOR_PAGE_NG_MASK (1UL << 11)
+#define TT_DESCRIPTOR_PAGE_NG_GLOBAL (0UL << 11)
+#define TT_DESCRIPTOR_PAGE_NG_LOCAL (1UL << 11)
+
+#define TT_DESCRIPTOR_SECTION_S_MASK (1UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED (0UL << 16)
+#define TT_DESCRIPTOR_SECTION_S_SHARED (1UL << 16)
+
+#define TT_DESCRIPTOR_PAGE_S_MASK (1UL << 10)
+#define TT_DESCRIPTOR_PAGE_S_NOT_SHARED (0UL << 10)
+#define TT_DESCRIPTOR_PAGE_S_SHARED (1UL << 10)
+
+#define TT_DESCRIPTOR_SECTION_AP_MASK ((1UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO ((0UL << 15) | (0UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO ((0UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO ((0UL << 15) | (2UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW ((0UL << 15) | (3UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO ((1UL << 15) | (1UL << 10))
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO ((1UL << 15) | (3UL << 10))
+
+#define TT_DESCRIPTOR_PAGE_AP_MASK ((1UL << 9) | (3UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_NO_NO ((0UL << 9) | (0UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_NO ((0UL << 9) | (1UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_RO ((0UL << 9) | (2UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RW_RW ((0UL << 9) | (3UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RO_NO ((1UL << 9) | (1UL << 4))
+#define TT_DESCRIPTOR_PAGE_AP_RO_RO ((1UL << 9) | (3UL << 4))
+
+#define TT_DESCRIPTOR_SECTION_XN_MASK (0x1UL << 4)
+#define TT_DESCRIPTOR_PAGE_XN_MASK (0x1UL << 0)
+#define TT_DESCRIPTOR_LARGEPAGE_XN_MASK (0x1UL << 15)
+
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHEABLE_MASK (1UL << 3)
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_PAGE_SIZE (0x00001000)
+
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK ((3UL << 6) | (1UL << 3) | (1UL << 2))
#define TT_DESCRIPTOR_PAGE_CACHEABLE_MASK (1UL << 3)
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
-
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
-#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
-
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc,IsLargePage) ((IsLargePage)? \
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 6) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 6) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 6) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 6) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 6) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 6) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK ((3UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_STRONGLY_ORDERED ((0UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_SHAREABLE_DEVICE ((0UL << 12) | (0UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_NO_ALLOC ((0UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_CACHEABLE ((1UL << 12) | (0UL << 3) | (0UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_WRITE_BACK_ALLOC ((1UL << 12) | (1UL << 3) | (1UL << 2))
+#define TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_NON_SHAREABLE_DEVICE ((2UL << 12) | (0UL << 3) | (0UL << 2))
+
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_AP(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_AP_MASK) >> 6) & TT_DESCRIPTOR_PAGE_AP_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_NG(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_NG_MASK) >> 6) & TT_DESCRIPTOR_PAGE_NG_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_S(Desc) ((((Desc) & TT_DESCRIPTOR_SECTION_S_MASK) >> 6) & TT_DESCRIPTOR_PAGE_S_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_XN(Desc, IsLargePage) ((IsLargePage)?\
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) << 11) & TT_DESCRIPTOR_LARGEPAGE_XN_MASK): \
((((Desc) & TT_DESCRIPTOR_SECTION_XN_MASK) >> 4) & TT_DESCRIPTOR_PAGE_XN_MASK))
-#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
+#define TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 12)) >> 6) | (Desc & (0x3 << 2)))))
-#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_AP(Desc) ((((Desc) & TT_DESCRIPTOR_PAGE_AP_MASK) << 6) & TT_DESCRIPTOR_SECTION_AP_MASK)
-#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc,IsLargePage) (IsLargePage? \
+#define TT_DESCRIPTOR_CONVERT_TO_SECTION_CACHE_POLICY(Desc, IsLargePage) (IsLargePage? \
(((Desc) & TT_DESCRIPTOR_LARGEPAGE_CACHE_POLICY_MASK) & TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK): \
(((((Desc) & (0x3 << 6)) << 6) | (Desc & (0x3 << 2)))))
-#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
+#define TT_DESCRIPTOR_SECTION_ATTRIBUTE_MASK (TT_DESCRIPTOR_SECTION_NS_MASK | TT_DESCRIPTOR_SECTION_NG_MASK | \
TT_DESCRIPTOR_SECTION_S_MASK | TT_DESCRIPTOR_SECTION_AP_MASK | \
TT_DESCRIPTOR_SECTION_XN_MASK | TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK)
-#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
+#define TT_DESCRIPTOR_PAGE_ATTRIBUTE_MASK (TT_DESCRIPTOR_PAGE_NG_MASK | TT_DESCRIPTOR_PAGE_S_MASK | \
TT_DESCRIPTOR_PAGE_AP_MASK | TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK)
-#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
-#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK (0x0FUL << 5)
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a) (((a) & 0x0FUL) << 5)
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
-#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
-#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
-#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK (0xFFF00000)
+#define TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK (0xFFFFFC00)
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)
+#define TT_DESCRIPTOR_SECTION_BASE_SHIFT 20
-#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
-#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
-#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
-#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
+#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK (0xFFFFF000)
+#define TT_DESCRIPTOR_PAGE_INDEX_MASK (0x000FF000)
+#define TT_DESCRIPTOR_PAGE_BASE_ADDRESS(a) ((a) & TT_DESCRIPTOR_PAGE_BASE_ADDRESS_MASK)
+#define TT_DESCRIPTOR_PAGE_BASE_SHIFT 12
-#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)
-#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_SHARED | \
TT_DESCRIPTOR_SECTION_DOMAIN(0) | \
TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
-#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+#define TT_DESCRIPTOR_SECTION_DEVICE(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
@@ -193,7 +192,7 @@ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_XN_MASK | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)
-#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
+#define TT_DESCRIPTOR_SECTION_UNCACHED(NonSecure) (TT_DESCRIPTOR_SECTION_TYPE_SECTION | \
((NonSecure) ? TT_DESCRIPTOR_SECTION_NS : 0) | \
TT_DESCRIPTOR_SECTION_NG_GLOBAL | \
TT_DESCRIPTOR_SECTION_S_NOT_SHARED | \
@@ -201,33 +200,33 @@ TT_DESCRIPTOR_SECTION_AP_RW_RW | \
TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)
-#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+#define TT_DESCRIPTOR_PAGE_WRITE_BACK (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC)
-#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+#define TT_DESCRIPTOR_PAGE_WRITE_THROUGH (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)
-#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+#define TT_DESCRIPTOR_PAGE_DEVICE (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_XN_MASK | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_SHAREABLE_DEVICE)
-#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
+#define TT_DESCRIPTOR_PAGE_UNCACHED (TT_DESCRIPTOR_PAGE_TYPE_PAGE | \
TT_DESCRIPTOR_PAGE_NG_GLOBAL | \
TT_DESCRIPTOR_PAGE_S_NOT_SHARED | \
TT_DESCRIPTOR_PAGE_AP_RW_RW | \
TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE)
// First Level Descriptors
-typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
+typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR;
// Second Level Descriptors
-typedef UINT32 ARM_PAGE_TABLE_ENTRY;
+typedef UINT32 ARM_PAGE_TABLE_ENTRY;
UINT32
ConvertSectionAttributesToPageAttributes (
diff --git a/ArmPkg/Include/Guid/ArmMpCoreInfo.h b/ArmPkg/Include/Guid/ArmMpCoreInfo.h index b810767879..06f9326ca0 100644 --- a/ArmPkg/Include/Guid/ArmMpCoreInfo.h +++ b/ArmPkg/Include/Guid/ArmMpCoreInfo.h @@ -9,52 +9,51 @@ #ifndef ARM_MP_CORE_INFO_GUID_H_
#define ARM_MP_CORE_INFO_GUID_H_
-#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
-#define SCU_CONFIG_REG_OFFSET 0x04
-#define MPIDR_U_BIT_MASK 0x40000000
+#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04
+#define SCU_CONFIG_REG_OFFSET 0x04
+#define MPIDR_U_BIT_MASK 0x40000000
typedef struct {
- UINT32 ClusterId;
- UINT32 CoreId;
+ UINT32 ClusterId;
+ UINT32 CoreId;
// MP Core Mailbox
- EFI_PHYSICAL_ADDRESS MailboxSetAddress;
- EFI_PHYSICAL_ADDRESS MailboxGetAddress;
- EFI_PHYSICAL_ADDRESS MailboxClearAddress;
- UINT64 MailboxClearValue;
+ EFI_PHYSICAL_ADDRESS MailboxSetAddress;
+ EFI_PHYSICAL_ADDRESS MailboxGetAddress;
+ EFI_PHYSICAL_ADDRESS MailboxClearAddress;
+ UINT64 MailboxClearValue;
} ARM_CORE_INFO;
-typedef struct{
- UINT64 Signature;
- UINT32 Length;
- UINT32 Revision;
- UINT64 OemId;
- UINT64 OemTableId;
- UINTN OemRevision;
- UINTN CreatorId;
- UINTN CreatorRevision;
- EFI_GUID Identifier;
- UINTN DataLen;
+typedef struct {
+ UINT64 Signature;
+ UINT32 Length;
+ UINT32 Revision;
+ UINT64 OemId;
+ UINT64 OemTableId;
+ UINTN OemRevision;
+ UINTN CreatorId;
+ UINTN CreatorRevision;
+ EFI_GUID Identifier;
+ UINTN DataLen;
} ARM_PROCESSOR_TABLE_HEADER;
typedef struct {
- ARM_PROCESSOR_TABLE_HEADER Header;
- UINTN NumberOfEntries;
- ARM_CORE_INFO *ArmCpus;
+ ARM_PROCESSOR_TABLE_HEADER Header;
+ UINTN NumberOfEntries;
+ ARM_CORE_INFO *ArmCpus;
} ARM_PROCESSOR_TABLE;
-
#define ARM_MP_CORE_INFO_GUID \
{ 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }
-#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
-#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0
-#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
-#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
-#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
-#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
-#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
+#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')
+#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000// 1.0
+#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')
+#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')
+#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001
-extern EFI_GUID gArmMpCoreInfoGuid;
+extern EFI_GUID gArmMpCoreInfoGuid;
#endif /* ARM_MP_CORE_INFO_GUID_H_ */
diff --git a/ArmPkg/Include/IndustryStandard/ArmCache.h b/ArmPkg/Include/IndustryStandard/ArmCache.h index f9de46b5bf..27a91fcda2 100644 --- a/ArmPkg/Include/IndustryStandard/ArmCache.h +++ b/ArmPkg/Include/IndustryStandard/ArmCache.h @@ -13,22 +13,21 @@ // The ARM Architecture Reference Manual for ARMv8-A defines up
// to 7 levels of cache, L1 through L7.
-#define MAX_ARM_CACHE_LEVEL 7
+#define MAX_ARM_CACHE_LEVEL 7
/// Defines the structure of the CSSELR (Cache Size Selection) register
typedef union {
struct {
- UINT32 InD :1; ///< Instruction not Data bit
- UINT32 Level :3; ///< Cache level (zero based)
- UINT32 TnD :1; ///< Allocation not Data bit
- UINT32 Reserved :27; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 InD : 1; ///< Instruction not Data bit
+ UINT32 Level : 3; ///< Cache level (zero based)
+ UINT32 TnD : 1; ///< Allocation not Data bit
+ UINT32 Reserved : 27; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CSSELR_DATA;
/// The cache type values for the InD field of the CSSELR register
-typedef enum
-{
+typedef enum {
/// Select the data or unified cache
CsselrCacheTypeDataOrUnified = 0,
/// Select the instruction cache
@@ -39,35 +38,35 @@ typedef enum /// Defines the structure of the CCSIDR (Current Cache Size ID) register
typedef union {
struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :10; ///< Associativity - 1
- UINT64 NumSets :15; ///< Number of sets in the cache -1
- UINT64 Unknown :4; ///< Reserved, UNKNOWN
- UINT64 Reserved :32; ///< Reserved, RES0
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity : 10; ///< Associativity - 1
+ UINT64 NumSets : 15; ///< Number of sets in the cache -1
+ UINT64 Unknown : 4; ///< Reserved, UNKNOWN
+ UINT64 Reserved : 32; ///< Reserved, RES0
} BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported.
struct {
- UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4)
- UINT64 Associativity :21; ///< Associativity - 1
- UINT64 Reserved1 :8; ///< Reserved, RES0
- UINT64 NumSets :24; ///< Number of sets in the cache -1
- UINT64 Reserved2 :8; ///< Reserved, RES0
+ UINT64 LineSize : 3; ///< Line size (Log2(Num bytes in cache) - 4)
+ UINT64 Associativity : 21; ///< Associativity - 1
+ UINT64 Reserved1 : 8; ///< Reserved, RES0
+ UINT64 NumSets : 24; ///< Number of sets in the cache -1
+ UINT64 Reserved2 : 8; ///< Reserved, RES0
} BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported.
struct {
- UINT64 LineSize : 3;
- UINT64 Associativity : 21;
- UINT64 Reserved : 8;
- UINT64 Unallocated : 32;
+ UINT64 LineSize : 3;
+ UINT64 Associativity : 21;
+ UINT64 Reserved : 8;
+ UINT64 Unallocated : 32;
} BitsCcidxAA32;
- UINT64 Data; ///< The entire 64-bit value
+ UINT64 Data; ///< The entire 64-bit value
} CCSIDR_DATA;
/// Defines the structure of the AARCH32 CCSIDR2 register.
typedef union {
struct {
- UINT32 NumSets :24; ///< Number of sets in the cache - 1
- UINT32 Reserved :8; ///< Reserved, RES0
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 NumSets : 24; ///< Number of sets in the cache - 1
+ UINT32 Reserved : 8; ///< Reserved, RES0
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CCSIDR2_DATA;
/** Defines the structure of the CLIDR (Cache Level ID) register.
@@ -77,19 +76,19 @@ typedef union { **/
typedef union {
struct {
- UINT32 Ctype1 : 3; ///< Level 1 cache type
- UINT32 Ctype2 : 3; ///< Level 2 cache type
- UINT32 Ctype3 : 3; ///< Level 3 cache type
- UINT32 Ctype4 : 3; ///< Level 4 cache type
- UINT32 Ctype5 : 3; ///< Level 5 cache type
- UINT32 Ctype6 : 3; ///< Level 6 cache type
- UINT32 Ctype7 : 3; ///< Level 7 cache type
- UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
- UINT32 LoC : 3; ///< Level of Coherency
- UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
- UINT32 Icb : 3; ///< Inner Cache Boundary
- } Bits; ///< Bitfield definition of the register
- UINT32 Data; ///< The entire 32-bit value
+ UINT32 Ctype1 : 3; ///< Level 1 cache type
+ UINT32 Ctype2 : 3; ///< Level 2 cache type
+ UINT32 Ctype3 : 3; ///< Level 3 cache type
+ UINT32 Ctype4 : 3; ///< Level 4 cache type
+ UINT32 Ctype5 : 3; ///< Level 5 cache type
+ UINT32 Ctype6 : 3; ///< Level 6 cache type
+ UINT32 Ctype7 : 3; ///< Level 7 cache type
+ UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable
+ UINT32 LoC : 3; ///< Level of Coherency
+ UINT32 LoUU : 3; ///< Level of Unification Uniprocessor
+ UINT32 Icb : 3; ///< Inner Cache Boundary
+ } Bits; ///< Bitfield definition of the register
+ UINT32 Data; ///< The entire 32-bit value
} CLIDR_DATA;
/// The cache types reported in the CLIDR register.
@@ -107,6 +106,6 @@ typedef enum { ClidrCacheTypeMax
} CLIDR_CACHE_TYPE;
-#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
+#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111)
#endif /* ARM_CACHE_H_ */
diff --git a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h index ebcb54b28b..4126a4985b 100644 --- a/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmFfaSvc.h @@ -16,34 +16,34 @@ #ifndef ARM_FFA_SVC_H_
#define ARM_FFA_SVC_H_
-#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
+#define ARM_SVC_ID_FFA_VERSION_AARCH32 0x84000063
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32 0x8400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32 0x84000070
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64 0xC400006F
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64 0xC4000070
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH64
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
-#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ ARM_SVC_ID_FFA_MSG_SEND_DIRECT_REQ_AARCH32
+#define ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP ARM_SVC_ID_FFA_MSG_SEND_DIRECT_RESP_AARCH32
#endif
-#define SPM_MAJOR_VERSION_FFA 1
-#define SPM_MINOR_VERSION_FFA 0
+#define SPM_MAJOR_VERSION_FFA 1
+#define SPM_MINOR_VERSION_FFA 0
-#define ARM_FFA_SPM_RET_SUCCESS 0
-#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
-#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
-#define ARM_FFA_SPM_RET_NO_MEMORY -3
-#define ARM_FFA_SPM_RET_BUSY -4
-#define ARM_FFA_SPM_RET_INTERRUPTED -5
-#define ARM_FFA_SPM_RET_DENIED -6
-#define ARM_FFA_SPM_RET_RETRY -7
-#define ARM_FFA_SPM_RET_ABORTED -8
+#define ARM_FFA_SPM_RET_SUCCESS 0
+#define ARM_FFA_SPM_RET_NOT_SUPPORTED -1
+#define ARM_FFA_SPM_RET_INVALID_PARAMETERS -2
+#define ARM_FFA_SPM_RET_NO_MEMORY -3
+#define ARM_FFA_SPM_RET_BUSY -4
+#define ARM_FFA_SPM_RET_INTERRUPTED -5
+#define ARM_FFA_SPM_RET_DENIED -6
+#define ARM_FFA_SPM_RET_RETRY -7
+#define ARM_FFA_SPM_RET_ABORTED -8
// For now, the destination id to be used in the FF-A calls
// is being hard-coded. Subsequently, support will be added
@@ -51,6 +51,6 @@ // This is the endpoint id used by the optee os's implementation
// of the spmc.
// https://github.com/OP-TEE/optee_os/blob/master/core/arch/arm/kernel/stmm_sp.c#L66
-#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
+#define ARM_FFA_DESTINATION_ENDPOINT_ID 3
#endif // ARM_FFA_SVC_H_
diff --git a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h index deb3bc99d2..11aa50e3ac 100644 --- a/ArmPkg/Include/IndustryStandard/ArmMmSvc.h +++ b/ArmPkg/Include/IndustryStandard/ArmMmSvc.h @@ -14,49 +14,49 @@ * delegated events and request the Secure partition manager to perform
* privileged operations on its behalf.
*/
-#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
-#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
+#define ARM_SVC_ID_SPM_VERSION_AARCH32 0x84000060
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32 0x84000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32 0x84000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32 0x84000065
+#define ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64 0xC4000061
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64 0xC4000064
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64 0xC4000065
/* Generic IDs when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH64
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH64
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
-#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
-#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_EVENT_COMPLETE ARM_SVC_ID_SP_EVENT_COMPLETE_AARCH32
+#define ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES ARM_SVC_ID_SP_GET_MEM_ATTRIBUTES_AARCH32
+#define ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES ARM_SVC_ID_SP_SET_MEM_ATTRIBUTES_AARCH32
#endif
#define SET_MEM_ATTR_DATA_PERM_MASK 0x3
-#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
-#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
-#define SET_MEM_ATTR_DATA_PERM_RW 1
-#define SET_MEM_ATTR_DATA_PERM_RO 3
+#define SET_MEM_ATTR_DATA_PERM_SHIFT 0
+#define SET_MEM_ATTR_DATA_PERM_NO_ACCESS 0
+#define SET_MEM_ATTR_DATA_PERM_RW 1
+#define SET_MEM_ATTR_DATA_PERM_RO 3
#define SET_MEM_ATTR_CODE_PERM_MASK 0x1
-#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
-#define SET_MEM_ATTR_CODE_PERM_X 0
-#define SET_MEM_ATTR_CODE_PERM_XN 1
+#define SET_MEM_ATTR_CODE_PERM_SHIFT 2
+#define SET_MEM_ATTR_CODE_PERM_X 0
+#define SET_MEM_ATTR_CODE_PERM_XN 1
#define SET_MEM_ATTR_MAKE_PERM_REQUEST(d_perm, c_perm) \
((((c_perm) & SET_MEM_ATTR_CODE_PERM_MASK) << SET_MEM_ATTR_CODE_PERM_SHIFT) | \
(( (d_perm) & SET_MEM_ATTR_DATA_PERM_MASK) << SET_MEM_ATTR_DATA_PERM_SHIFT))
/* MM SVC Return error codes */
-#define ARM_SVC_SPM_RET_SUCCESS 0
-#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
-#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
-#define ARM_SVC_SPM_RET_DENIED -3
-#define ARM_SVC_SPM_RET_NO_MEMORY -5
-
-#define SPM_MAJOR_VERSION 0
-#define SPM_MINOR_VERSION 1
+#define ARM_SVC_SPM_RET_SUCCESS 0
+#define ARM_SVC_SPM_RET_NOT_SUPPORTED -1
+#define ARM_SVC_SPM_RET_INVALID_PARAMS -2
+#define ARM_SVC_SPM_RET_DENIED -3
+#define ARM_SVC_SPM_RET_NO_MEMORY -5
+
+#define SPM_MAJOR_VERSION 0
+#define SPM_MINOR_VERSION 1
#endif // ARM_MM_SVC_H_
diff --git a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h index 9116a291da..655edc21b2 100644 --- a/ArmPkg/Include/IndustryStandard/ArmStdSmc.h +++ b/ArmPkg/Include/IndustryStandard/ArmStdSmc.h @@ -17,64 +17,64 @@ * SMC function IDs for Standard Service queries
*/
-#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
-#define ARM_SMC_ID_STD_UID 0x8400ff01
+#define ARM_SMC_ID_STD_CALL_COUNT 0x8400ff00
+#define ARM_SMC_ID_STD_UID 0x8400ff01
/* 0x8400ff02 is reserved */
-#define ARM_SMC_ID_STD_REVISION 0x8400ff03
+#define ARM_SMC_ID_STD_REVISION 0x8400ff03
/*
* The 'Standard Service Call UID' is supposed to return the Standard
* Service UUID. This is a 128-bit value.
*/
-#define ARM_SMC_STD_UUID0 0x108d905b
-#define ARM_SMC_STD_UUID1 0x47e8f863
-#define ARM_SMC_STD_UUID2 0xfbc02dae
-#define ARM_SMC_STD_UUID3 0xe2f64156
+#define ARM_SMC_STD_UUID0 0x108d905b
+#define ARM_SMC_STD_UUID1 0x47e8f863
+#define ARM_SMC_STD_UUID2 0xfbc02dae
+#define ARM_SMC_STD_UUID3 0xe2f64156
/*
* ARM Standard Service Calls revision numbers
* The current revision is: 0.1
*/
-#define ARM_SMC_STD_REVISION_MAJOR 0x0
-#define ARM_SMC_STD_REVISION_MINOR 0x1
+#define ARM_SMC_STD_REVISION_MAJOR 0x0
+#define ARM_SMC_STD_REVISION_MINOR 0x1
/*
* Management Mode (MM) calls cover a subset of the Standard Service Call range.
* The list below is not exhaustive.
*/
-#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
-#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
+#define ARM_SMC_ID_MM_VERSION_AARCH32 0x84000040
+#define ARM_SMC_ID_MM_VERSION_AARCH64 0xC4000040
// Request service from secure standalone MM environment
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
-#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH32 0x84000041
+#define ARM_SMC_ID_MM_COMMUNICATE_AARCH64 0xC4000041
/* Generic ID when using AArch32 or AArch64 execution state */
#ifdef MDE_CPU_AARCH64
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH64
#endif
#ifdef MDE_CPU_ARM
-#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
+#define ARM_SMC_ID_MM_COMMUNICATE ARM_SMC_ID_MM_COMMUNICATE_AARCH32
#endif
/* MM return error codes */
-#define ARM_SMC_MM_RET_SUCCESS 0
-#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
-#define ARM_SMC_MM_RET_INVALID_PARAMS -2
-#define ARM_SMC_MM_RET_DENIED -3
-#define ARM_SMC_MM_RET_NO_MEMORY -4
+#define ARM_SMC_MM_RET_SUCCESS 0
+#define ARM_SMC_MM_RET_NOT_SUPPORTED -1
+#define ARM_SMC_MM_RET_INVALID_PARAMS -2
+#define ARM_SMC_MM_RET_DENIED -3
+#define ARM_SMC_MM_RET_NO_MEMORY -4
// ARM Architecture Calls
-#define SMCCC_VERSION 0x80000000
-#define SMCCC_ARCH_FEATURES 0x80000001
-#define SMCCC_ARCH_SOC_ID 0x80000002
-#define SMCCC_ARCH_WORKAROUND_1 0x80008000
-#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
+#define SMCCC_VERSION 0x80000000
+#define SMCCC_ARCH_FEATURES 0x80000001
+#define SMCCC_ARCH_SOC_ID 0x80000002
+#define SMCCC_ARCH_WORKAROUND_1 0x80008000
+#define SMCCC_ARCH_WORKAROUND_2 0x80007FFF
#define SMC_ARCH_CALL_SUCCESS 0
-#define SMC_ARCH_CALL_NOT_SUPPORTED -1
-#define SMC_ARCH_CALL_NOT_REQUIRED -2
-#define SMC_ARCH_CALL_INVALID_PARAMETER -3
+#define SMC_ARCH_CALL_NOT_SUPPORTED -1
+#define SMC_ARCH_CALL_NOT_REQUIRED -2
+#define SMC_ARCH_CALL_INVALID_PARAMETER -3
/*
* Power State Coordination Interface (PSCI) calls cover a subset of the
@@ -101,15 +101,15 @@ ((ARM_SMC_PSCI_VERSION_MAJOR << 16) | ARM_SMC_PSCI_VERSION_MINOR)
/* PSCI return error codes */
-#define ARM_SMC_PSCI_RET_SUCCESS 0
-#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
-#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
-#define ARM_SMC_PSCI_RET_DENIED -3
-#define ARM_SMC_PSCI_RET_ALREADY_ON -4
-#define ARM_SMC_PSCI_RET_ON_PENDING -5
-#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
-#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
-#define ARM_SMC_PSCI_RET_DISABLED -8
+#define ARM_SMC_PSCI_RET_SUCCESS 0
+#define ARM_SMC_PSCI_RET_NOT_SUPPORTED -1
+#define ARM_SMC_PSCI_RET_INVALID_PARAMS -2
+#define ARM_SMC_PSCI_RET_DENIED -3
+#define ARM_SMC_PSCI_RET_ALREADY_ON -4
+#define ARM_SMC_PSCI_RET_ON_PENDING -5
+#define ARM_SMC_PSCI_RET_INTERN_FAIL -6
+#define ARM_SMC_PSCI_RET_NOT_PRESENT -7
+#define ARM_SMC_PSCI_RET_DISABLED -8
#define ARM_SMC_PSCI_TARGET_CPU32(Aff2, Aff1, Aff0) \
((((Aff2) & 0xFF) << 16) | (((Aff1) & 0xFF) << 8) | ((Aff0) & 0xFF))
@@ -120,10 +120,10 @@ #define ARM_SMC_PSCI_TARGET_GET_AFF0(TargetId) ((TargetId) & 0xFF)
#define ARM_SMC_PSCI_TARGET_GET_AFF1(TargetId) (((TargetId) >> 8) & 0xFF)
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
-#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_0 0
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_1 1
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_2 2
+#define ARM_SMC_ID_PSCI_AFFINITY_LEVEL_3 3
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_ON 0
#define ARM_SMC_ID_PSCI_AFFINITY_INFO_OFF 1
@@ -132,9 +132,9 @@ /*
* SMC function IDs for Trusted OS Service queries
*/
-#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
-#define ARM_SMC_ID_TOS_UID 0xbf00ff01
+#define ARM_SMC_ID_TOS_CALL_COUNT 0xbf00ff00
+#define ARM_SMC_ID_TOS_UID 0xbf00ff01
/* 0xbf00ff02 is reserved */
-#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
+#define ARM_SMC_ID_TOS_REVISION 0xbf00ff03
#endif // ARM_STD_SMC_H_
diff --git a/ArmPkg/Include/Library/ArmDisassemblerLib.h b/ArmPkg/Include/Library/ArmDisassemblerLib.h index d8c7af029d..f065ded5f3 100644 --- a/ArmPkg/Include/Library/ArmDisassemblerLib.h +++ b/ArmPkg/Include/Library/ArmDisassemblerLib.h @@ -26,12 +26,12 @@ **/
VOID
DisassembleInstruction (
- IN UINT8 **OpCodePtr,
- IN BOOLEAN Thumb,
- IN BOOLEAN Extended,
- IN OUT UINT32 *ItBlock,
- OUT CHAR8 *Buf,
- OUT UINTN Size
+ IN UINT8 **OpCodePtr,
+ IN BOOLEAN Thumb,
+ IN BOOLEAN Extended,
+ IN OUT UINT32 *ItBlock,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size
);
#endif // ARM_DISASSEMBLER_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h b/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h index 96bdffbf1e..45a32c6c2c 100644 --- a/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h +++ b/ArmPkg/Include/Library/ArmGenericTimerCounterLib.h @@ -43,7 +43,7 @@ ArmGenericTimerGetTimerFreq ( VOID
EFIAPI
ArmGenericTimerSetTimerVal (
- IN UINTN Value
+ IN UINTN Value
);
UINTN
@@ -67,7 +67,7 @@ ArmGenericTimerGetTimerCtrlReg ( VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
- UINTN Value
+ UINTN Value
);
UINT64
@@ -79,7 +79,7 @@ ArmGenericTimerGetCompareVal ( VOID
EFIAPI
ArmGenericTimerSetCompareVal (
- IN UINT64 Value
+ IN UINT64 Value
);
#endif // ARM_GENERIC_TIMER_COUNTER_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmGicArchLib.h b/ArmPkg/Include/Library/ArmGicArchLib.h index b3635d2268..72ac17e13b 100644 --- a/ArmPkg/Include/Library/ArmGicArchLib.h +++ b/ArmPkg/Include/Library/ArmGicArchLib.h @@ -17,7 +17,6 @@ typedef enum { ARM_GIC_ARCH_REVISION_3
} ARM_GIC_ARCH_REVISION;
-
ARM_GIC_ARCH_REVISION
EFIAPI
ArmGicGetSupportedArchRevision (
diff --git a/ArmPkg/Include/Library/ArmGicLib.h b/ArmPkg/Include/Library/ArmGicLib.h index b4c320be11..4ab6709675 100644 --- a/ArmPkg/Include/Library/ArmGicLib.h +++ b/ArmPkg/Include/Library/ArmGicLib.h @@ -12,36 +12,36 @@ #include <Library/ArmGicArchLib.h>
// GIC Distributor
-#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
-#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
-#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
+#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register
+#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register
+#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register
// Each reg base below repeats for Number of interrupts / 4 (see GIC spec)
-#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
-#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
-#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
-#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
-#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
-#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
+#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers
+#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers
+#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers
+#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers
+#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers
+#define ARM_GIC_ICDABR 0x300 // Active Bit Registers
// Each reg base below repeats for Number of interrupts / 4
-#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
+#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers
// Each reg base below repeats for Number of interrupts
-#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
-#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
+#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers
+#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers
-#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
+#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register
// just one of these
-#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
+#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register
// GICv3 specific registers
-#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
+#define ARM_GICD_IROUTER 0x6100 // Interrupt Routing Registers
// GICD_CTLR bits
-#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
-#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
+#define ARM_GIC_ICDDCR_ARE (1 << 4) // Affinity Routing Enable (ARE)
+#define ARM_GIC_ICDDCR_DS (1 << 6) // Disable Security (DS)
// GICD_ICDICFR bits
#define ARM_GIC_ICDICFR_WIDTH 32 // ICDICFR is a 32 bit register
@@ -52,125 +52,124 @@ #define ARM_GIC_ICDICFR_LEVEL_TRIGGERED 0x0 // Level triggered interrupt
#define ARM_GIC_ICDICFR_EDGE_TRIGGERED 0x1 // Edge triggered interrupt
-
// GIC Redistributor
-#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
-#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
-#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
-#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_CTLR_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_PPI_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_VLPI_FRAME_SIZE SIZE_64KB
+#define ARM_GICR_SGI_RESERVED_FRAME_SIZE SIZE_64KB
// GIC Redistributor Control frame
-#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
+#define ARM_GICR_TYPER 0x0008 // Redistributor Type Register
// GIC Redistributor TYPER bit assignments
-#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
-#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
-#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
-#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
-#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
+#define ARM_GICR_TYPER_PLPIS (1 << 0) // Physical LPIs
+#define ARM_GICR_TYPER_VLPIS (1 << 1) // Virtual LPIs
+#define ARM_GICR_TYPER_DIRECTLPI (1 << 3) // Direct LPIs
+#define ARM_GICR_TYPER_LAST (1 << 4) // Last Redistributor in series
+#define ARM_GICR_TYPER_DPGS (1 << 5) // Disable Processor Group
// Selection Support
-#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
-#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
-#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
+#define ARM_GICR_TYPER_PROCNO (0xFFFF << 8) // Processor Number
+#define ARM_GICR_TYPER_COMMONLPIAFF (0x3 << 24) // Common LPI Affinity
+#define ARM_GICR_TYPER_AFFINITY (0xFFFFFFFFULL << 32) // Redistributor Affinity
#define ARM_GICR_TYPER_GET_AFFINITY(TypeReg) (((TypeReg) & \
ARM_GICR_TYPER_AFFINITY) >> 32)
// GIC SGI & PPI Redistributor frame
-#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
-#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
+#define ARM_GICR_ISENABLER 0x0100 // Interrupt Set-Enable Registers
+#define ARM_GICR_ICENABLER 0x0180 // Interrupt Clear-Enable Registers
// GIC Cpu interface
-#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
-#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
-#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
-#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
-#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
-#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
-#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
-#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
-#define ARM_GIC_ICCIIDR 0xFC // Identification Register
-
-#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
-#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
-#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
+#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register
+#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register
+#define ARM_GIC_ICCBPR 0x08 // Binary Point Register
+#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register
+#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register
+#define ARM_GIC_ICCRPR 0x14 // Running Priority Register
+#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register
+#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register
+#define ARM_GIC_ICCIIDR 0xFC // Identification Register
+
+#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0
+#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1
+#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2
// Bit-masks to configure the CPU Interface Control register
-#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
-#define ARM_GIC_ICCICR_ENABLE_NS 0x02
-#define ARM_GIC_ICCICR_ACK_CTL 0x04
-#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
-#define ARM_GIC_ICCICR_USE_SBPR 0x10
+#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01
+#define ARM_GIC_ICCICR_ENABLE_NS 0x02
+#define ARM_GIC_ICCICR_ACK_CTL 0x04
+#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08
+#define ARM_GIC_ICCICR_USE_SBPR 0x10
// Bit Mask for GICC_IIDR
-#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
-#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
-#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
-#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
+#define ARM_GIC_ICCIIDR_GET_PRODUCT_ID(IccIidr) (((IccIidr) >> 20) & 0xFFF)
+#define ARM_GIC_ICCIIDR_GET_ARCH_VERSION(IccIidr) (((IccIidr) >> 16) & 0xF)
+#define ARM_GIC_ICCIIDR_GET_REVISION(IccIidr) (((IccIidr) >> 12) & 0xF)
+#define ARM_GIC_ICCIIDR_GET_IMPLEMENTER(IccIidr) ((IccIidr) & 0xFFF)
// Bit Mask for
-#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
+#define ARM_GIC_ICCIAR_ACKINTID 0x3FF
UINTN
EFIAPI
ArmGicGetInterfaceIdentification (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
// GIC Secure interfaces
VOID
EFIAPI
ArmGicSetupNonSecure (
- IN UINTN MpId,
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicSetSecureInterrupts (
- IN UINTN GicDistributorBase,
- IN UINTN* GicSecureInterruptMask,
- IN UINTN GicSecureInterruptMaskSize
+ IN UINTN GicDistributorBase,
+ IN UINTN *GicSecureInterruptMask,
+ IN UINTN GicSecureInterruptMaskSize
);
VOID
EFIAPI
ArmGicEnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicDisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicEnableDistributor (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
);
VOID
EFIAPI
ArmGicDisableDistributor (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
);
UINTN
EFIAPI
ArmGicGetMaxNumInterrupts (
- IN INTN GicDistributorBase
+ IN INTN GicDistributorBase
);
VOID
EFIAPI
ArmGicSendSgiTo (
- IN INTN GicDistributorBase,
- IN INTN TargetListFilter,
- IN INTN CPUTargetList,
- IN INTN SgiId
+ IN INTN GicDistributorBase,
+ IN INTN TargetListFilter,
+ IN INTN CPUTargetList,
+ IN INTN SgiId
);
/*
@@ -190,55 +189,55 @@ ArmGicSendSgiTo ( UINTN
EFIAPI
ArmGicAcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- OUT UINTN *InterruptId
+ IN UINTN GicInterruptInterfaceBase,
+ OUT UINTN *InterruptId
);
VOID
EFIAPI
ArmGicEndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
);
UINTN
EFIAPI
ArmGicSetPriorityMask (
- IN INTN GicInterruptInterfaceBase,
- IN INTN PriorityMask
+ IN INTN GicInterruptInterfaceBase,
+ IN INTN PriorityMask
);
VOID
EFIAPI
ArmGicSetInterruptPriority (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source,
- IN UINTN Priority
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source,
+ IN UINTN Priority
);
VOID
EFIAPI
ArmGicEnableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
);
VOID
EFIAPI
ArmGicDisableInterrupt (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
);
BOOLEAN
EFIAPI
ArmGicIsInterruptEnabled (
- IN UINTN GicDistributorBase,
- IN UINTN GicRedistributorBase,
- IN UINTN Source
+ IN UINTN GicDistributorBase,
+ IN UINTN GicRedistributorBase,
+ IN UINTN Source
);
// GIC revision 2 specific declarations
@@ -251,41 +250,41 @@ ArmGicIsInterruptEnabled ( VOID
EFIAPI
ArmGicV2SetupNonSecure (
- IN UINTN MpId,
- IN INTN GicDistributorBase,
- IN INTN GicInterruptInterfaceBase
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2EnableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2DisableInterruptInterface (
- IN INTN GicInterruptInterfaceBase
+ IN INTN GicInterruptInterfaceBase
);
UINTN
EFIAPI
ArmGicV2AcknowledgeInterrupt (
- IN UINTN GicInterruptInterfaceBase
+ IN UINTN GicInterruptInterfaceBase
);
VOID
EFIAPI
ArmGicV2EndOfInterrupt (
- IN UINTN GicInterruptInterfaceBase,
- IN UINTN Source
+ IN UINTN GicInterruptInterfaceBase,
+ IN UINTN Source
);
// GIC revision 3 specific declarations
-#define ICC_SRE_EL2_SRE (1 << 0)
+#define ICC_SRE_EL2_SRE (1 << 0)
-#define ARM_GICD_IROUTER_IRM BIT31
+#define ARM_GICD_IROUTER_IRM BIT31
UINT32
EFIAPI
@@ -296,7 +295,7 @@ ArmGicV3GetControlSystemRegisterEnable ( VOID
EFIAPI
ArmGicV3SetControlSystemRegisterEnable (
- IN UINT32 ControlSystemRegisterEnable
+ IN UINT32 ControlSystemRegisterEnable
);
VOID
@@ -320,17 +319,17 @@ ArmGicV3AcknowledgeInterrupt ( VOID
EFIAPI
ArmGicV3EndOfInterrupt (
- IN UINTN Source
+ IN UINTN Source
);
VOID
ArmGicV3SetBinaryPointer (
- IN UINTN BinaryPoint
+ IN UINTN BinaryPoint
);
VOID
ArmGicV3SetPriorityMask (
- IN UINTN Priority
+ IN UINTN Priority
);
#endif // ARMGIC_H_
diff --git a/ArmPkg/Include/Library/ArmHvcLib.h b/ArmPkg/Include/Library/ArmHvcLib.h index d202c2af6e..663ceb8e13 100644 --- a/ArmPkg/Include/Library/ArmHvcLib.h +++ b/ArmPkg/Include/Library/ArmHvcLib.h @@ -14,14 +14,14 @@ * The native size is used for the arguments.
*/
typedef struct {
- UINTN Arg0;
- UINTN Arg1;
- UINTN Arg2;
- UINTN Arg3;
- UINTN Arg4;
- UINTN Arg5;
- UINTN Arg6;
- UINTN Arg7;
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
} ARM_HVC_ARGS;
/**
@@ -34,7 +34,7 @@ typedef struct { **/
VOID
ArmCallHvc (
- IN OUT ARM_HVC_ARGS *Args
+ IN OUT ARM_HVC_ARGS *Args
);
#endif // ARM_HVC_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmLib.h b/ArmPkg/Include/Library/ArmLib.h index 79ea755777..e4d0476090 100644 --- a/ArmPkg/Include/Library/ArmLib.h +++ b/ArmPkg/Include/Library/ArmLib.h @@ -15,13 +15,13 @@ #ifdef MDE_CPU_ARM
#include <Chipset/ArmV7.h>
-#elif defined(MDE_CPU_AARCH64)
+#elif defined (MDE_CPU_AARCH64)
#include <Chipset/AArch64.h>
#else
- #error "Unknown chipset."
+ #error "Unknown chipset."
#endif
-#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
+#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \
EFI_MEMORY_WT | EFI_MEMORY_WB | \
EFI_MEMORY_UCE)
@@ -50,17 +50,21 @@ typedef enum { ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
} ARM_MEMORY_REGION_ATTRIBUTES;
-#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
+#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)
typedef struct {
- EFI_PHYSICAL_ADDRESS PhysicalBase;
- EFI_VIRTUAL_ADDRESS VirtualBase;
- UINT64 Length;
- ARM_MEMORY_REGION_ATTRIBUTES Attributes;
+ EFI_PHYSICAL_ADDRESS PhysicalBase;
+ EFI_VIRTUAL_ADDRESS VirtualBase;
+ UINT64 Length;
+ ARM_MEMORY_REGION_ATTRIBUTES Attributes;
} ARM_MEMORY_REGION_DESCRIPTOR;
-typedef VOID (*CACHE_OPERATION)(VOID);
-typedef VOID (*LINE_OPERATION)(UINTN);
+typedef VOID (*CACHE_OPERATION)(
+ VOID
+ );
+typedef VOID (*LINE_OPERATION)(
+ UINTN
+ );
//
// ARM Processor Mode
@@ -80,34 +84,34 @@ typedef enum { //
// ARM Cpu IDs
//
-#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
-#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
-#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
-#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
-#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
-#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
-
-#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
-#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
+#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)
+#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)
+#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)
+#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)
+#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)
+#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)
+
+#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)
+#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)
//
// ARM MP Core IDs
//
-#define ARM_CORE_AFF0 0xFF
-#define ARM_CORE_AFF1 (0xFF << 8)
-#define ARM_CORE_AFF2 (0xFF << 16)
-#define ARM_CORE_AFF3 (0xFFULL << 32)
-
-#define ARM_CORE_MASK ARM_CORE_AFF0
-#define ARM_CLUSTER_MASK ARM_CORE_AFF1
-#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
-#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
-#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
-#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
+#define ARM_CORE_AFF0 0xFF
+#define ARM_CORE_AFF1 (0xFF << 8)
+#define ARM_CORE_AFF2 (0xFF << 16)
+#define ARM_CORE_AFF3 (0xFFULL << 32)
+
+#define ARM_CORE_MASK ARM_CORE_AFF0
+#define ARM_CLUSTER_MASK ARM_CORE_AFF1
+#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)
+#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)
+#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) | (CoreId))
+#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)
/** Reads the CCSIDR register for the specified cache.
@@ -118,7 +122,7 @@ typedef enum { **/
UINTN
ReadCCSIDR (
- IN UINT32 CSSELR
+ IN UINT32 CSSELR
);
/** Reads the CCSIDR2 for the specified cache.
@@ -129,7 +133,7 @@ ReadCCSIDR ( **/
UINT32
ReadCCSIDR2 (
- IN UINT32 CSSELR
+ IN UINT32 CSSELR
);
/** Reads the Cache Level ID (CLIDR) register.
@@ -183,7 +187,6 @@ ArmInvalidateDataCache ( VOID
);
-
VOID
EFIAPI
ArmCleanInvalidateDataCache (
@@ -205,31 +208,31 @@ ArmInvalidateInstructionCache ( VOID
EFIAPI
ArmInvalidateDataCacheEntryByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryToPoUByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
EFIAPI
ArmInvalidateInstructionCacheEntryToPoUByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
EFIAPI
ArmCleanDataCacheEntryByMVA (
-IN UINTN Address
-);
+ IN UINTN Address
+ );
VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryByMVA (
- IN UINTN Address
+ IN UINTN Address
);
VOID
@@ -352,8 +355,8 @@ ArmInvalidateTlb ( VOID
EFIAPI
ArmUpdateTranslationTableEntry (
- IN VOID *TranslationTableEntry,
- IN VOID *Mva
+ IN VOID *TranslationTableEntry,
+ IN VOID *Mva
);
VOID
@@ -371,7 +374,7 @@ ArmSetTTBR0 ( VOID
EFIAPI
ArmSetTTBCR (
- IN UINT32 Bits
+ IN UINT32 Bits
);
VOID *
@@ -431,7 +434,7 @@ ArmInstructionSynchronizationBarrier ( VOID
EFIAPI
ArmWriteVBar (
- IN UINTN VectorBase
+ IN UINTN VectorBase
);
UINTN
@@ -443,7 +446,7 @@ ArmReadVBar ( VOID
EFIAPI
ArmWriteAuxCr (
- IN UINT32 Bit
+ IN UINT32 Bit
);
UINT32
@@ -455,13 +458,13 @@ ArmReadAuxCr ( VOID
EFIAPI
ArmSetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
);
VOID
EFIAPI
ArmUnsetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
);
VOID
@@ -504,7 +507,7 @@ ArmReadCpacr ( VOID
EFIAPI
ArmWriteCpacr (
- IN UINT32 Access
+ IN UINT32 Access
);
VOID
@@ -534,7 +537,7 @@ ArmReadScr ( VOID
EFIAPI
ArmWriteScr (
- IN UINT32 Value
+ IN UINT32 Value
);
UINT32
@@ -546,7 +549,7 @@ ArmReadMVBar ( VOID
EFIAPI
ArmWriteMVBar (
- IN UINT32 VectorMonitorBase
+ IN UINT32 VectorMonitorBase
);
UINT32
@@ -558,7 +561,7 @@ ArmReadSctlr ( VOID
EFIAPI
ArmWriteSctlr (
- IN UINT32 Value
+ IN UINT32 Value
);
UINTN
@@ -570,10 +573,9 @@ ArmReadHVBar ( VOID
EFIAPI
ArmWriteHVBar (
- IN UINTN HypModeVectorBase
+ IN UINTN HypModeVectorBase
);
-
//
// Helper functions for accessing CPU ACTLR
//
@@ -587,28 +589,28 @@ ArmReadCpuActlr ( VOID
EFIAPI
ArmWriteCpuActlr (
- IN UINTN Val
+ IN UINTN Val
);
VOID
EFIAPI
ArmSetCpuActlrBit (
- IN UINTN Bits
+ IN UINTN Bits
);
VOID
EFIAPI
ArmUnsetCpuActlrBit (
- IN UINTN Bits
+ IN UINTN Bits
);
//
// Accessors for the architected generic timer registers
//
-#define ARM_ARCH_TIMER_ENABLE (1 << 0)
-#define ARM_ARCH_TIMER_IMASK (1 << 1)
-#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
+#define ARM_ARCH_TIMER_ENABLE (1 << 0)
+#define ARM_ARCH_TIMER_IMASK (1 << 1)
+#define ARM_ARCH_TIMER_ISTATUS (1 << 2)
UINTN
EFIAPI
@@ -619,7 +621,7 @@ ArmReadCntFrq ( VOID
EFIAPI
ArmWriteCntFrq (
- UINTN FreqInHz
+ UINTN FreqInHz
);
UINT64
@@ -637,7 +639,7 @@ ArmReadCntkCtl ( VOID
EFIAPI
ArmWriteCntkCtl (
- UINTN Val
+ UINTN Val
);
UINTN
@@ -649,7 +651,7 @@ ArmReadCntpTval ( VOID
EFIAPI
ArmWriteCntpTval (
- UINTN Val
+ UINTN Val
);
UINTN
@@ -661,7 +663,7 @@ ArmReadCntpCtl ( VOID
EFIAPI
ArmWriteCntpCtl (
- UINTN Val
+ UINTN Val
);
UINTN
@@ -673,7 +675,7 @@ ArmReadCntvTval ( VOID
EFIAPI
ArmWriteCntvTval (
- UINTN Val
+ UINTN Val
);
UINTN
@@ -685,7 +687,7 @@ ArmReadCntvCtl ( VOID
EFIAPI
ArmWriteCntvCtl (
- UINTN Val
+ UINTN Val
);
UINT64
@@ -703,7 +705,7 @@ ArmReadCntpCval ( VOID
EFIAPI
ArmWriteCntpCval (
- UINT64 Val
+ UINT64 Val
);
UINT64
@@ -715,7 +717,7 @@ ArmReadCntvCval ( VOID
EFIAPI
ArmWriteCntvCval (
- UINT64 Val
+ UINT64 Val
);
UINT64
@@ -727,7 +729,7 @@ ArmReadCntvOff ( VOID
EFIAPI
ArmWriteCntvOff (
- UINT64 Val
+ UINT64 Val
);
UINTN
@@ -736,7 +738,6 @@ ArmGetPhysicalAddressBits ( VOID
);
-
///
/// ID Register Helper functions
///
@@ -768,6 +769,7 @@ ArmHasCcidx ( ///
/// AArch32-only ID Register Helper functions
///
+
/**
Check whether the CPU supports the Security extensions
@@ -779,6 +781,7 @@ EFIAPI ArmHasSecurityExtensions (
VOID
);
+
#endif // MDE_CPU_ARM
#endif // ARM_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmMmuLib.h b/ArmPkg/Include/Library/ArmMmuLib.h index 410f06ce37..7538a8274a 100644 --- a/ArmPkg/Include/Library/ArmMmuLib.h +++ b/ArmPkg/Include/Library/ArmMmuLib.h @@ -24,29 +24,29 @@ ArmConfigureMmu ( EFI_STATUS
EFIAPI
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
EFIAPI
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
VOID
@@ -59,9 +59,9 @@ ArmReplaceLiveTranslationEntry ( EFI_STATUS
ArmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
);
#endif // ARM_MMU_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmMtlLib.h b/ArmPkg/Include/Library/ArmMtlLib.h index 35059bf789..3050f06167 100644 --- a/ArmPkg/Include/Library/ArmMtlLib.h +++ b/ArmPkg/Include/Library/ArmMtlLib.h @@ -18,37 +18,37 @@ #pragma pack(1)
typedef struct {
- UINT32 Reserved1;
- UINT32 ChannelStatus;
- UINT64 Reserved2;
- UINT32 Flags;
- UINT32 Length;
- UINT32 MessageHeader;
+ UINT32 Reserved1;
+ UINT32 ChannelStatus;
+ UINT64 Reserved2;
+ UINT32 Flags;
+ UINT32 Length;
+ UINT32 MessageHeader;
// NOTE: Since EDK2 does not allow flexible array member [] we declare
// here array of 1 element length. However below is used as a variable
// length array.
- UINT32 Payload[1]; // size less object gives offset to payload.
+ UINT32 Payload[1]; // size less object gives offset to payload.
} MTL_MAILBOX;
#pragma pack()
// Channel Type, Low-priority, and High-priority
typedef enum {
- MTL_CHANNEL_TYPE_LOW = 0,
+ MTL_CHANNEL_TYPE_LOW = 0,
MTL_CHANNEL_TYPE_HIGH = 1
} MTL_CHANNEL_TYPE;
typedef struct {
- UINT64 PhysicalAddress;
- UINT32 ModifyMask;
- UINT32 PreserveMask;
+ UINT64 PhysicalAddress;
+ UINT32 ModifyMask;
+ UINT32 PreserveMask;
} MTL_DOORBELL;
typedef struct {
- MTL_CHANNEL_TYPE ChannelType;
- MTL_MAILBOX * CONST MailBox;
- MTL_DOORBELL DoorBell;
+ MTL_CHANNEL_TYPE ChannelType;
+ MTL_MAILBOX *CONST MailBox;
+ MTL_DOORBELL DoorBell;
} MTL_CHANNEL;
/** Wait until channel is free.
@@ -71,7 +71,7 @@ MtlWaitUntilChannelFree ( @retval UINT32* Pointer to the payload.
**/
-UINT32*
+UINT32 *
MtlGetChannelPayload (
IN MTL_CHANNEL *Channel
);
@@ -127,5 +127,4 @@ MtlReceiveMessage ( OUT UINT32 *PayloadLength
);
-#endif /* ARM_MTL_LIB_H_ */
-
+#endif /* ARM_MTL_LIB_H_ */
diff --git a/ArmPkg/Include/Library/ArmSmcLib.h b/ArmPkg/Include/Library/ArmSmcLib.h index ced60b3c11..f5b45f0a8c 100644 --- a/ArmPkg/Include/Library/ArmSmcLib.h +++ b/ArmPkg/Include/Library/ArmSmcLib.h @@ -14,14 +14,14 @@ * The native size is used for the arguments.
*/
typedef struct {
- UINTN Arg0;
- UINTN Arg1;
- UINTN Arg2;
- UINTN Arg3;
- UINTN Arg4;
- UINTN Arg5;
- UINTN Arg6;
- UINTN Arg7;
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
} ARM_SMC_ARGS;
/**
@@ -34,7 +34,7 @@ typedef struct { **/
VOID
ArmCallSmc (
- IN OUT ARM_SMC_ARGS *Args
+ IN OUT ARM_SMC_ARGS *Args
);
#endif // ARM_SMC_LIB_H_
diff --git a/ArmPkg/Include/Library/ArmSvcLib.h b/ArmPkg/Include/Library/ArmSvcLib.h index d4a1a8f118..71a640b9c9 100644 --- a/ArmPkg/Include/Library/ArmSvcLib.h +++ b/ArmPkg/Include/Library/ArmSvcLib.h @@ -14,14 +14,14 @@ * The native size is used for the arguments.
*/
typedef struct {
- UINTN Arg0;
- UINTN Arg1;
- UINTN Arg2;
- UINTN Arg3;
- UINTN Arg4;
- UINTN Arg5;
- UINTN Arg6;
- UINTN Arg7;
+ UINTN Arg0;
+ UINTN Arg1;
+ UINTN Arg2;
+ UINTN Arg3;
+ UINTN Arg4;
+ UINTN Arg5;
+ UINTN Arg6;
+ UINTN Arg7;
} ARM_SVC_ARGS;
/**
@@ -40,7 +40,7 @@ typedef struct { **/
VOID
ArmCallSvc (
- IN OUT ARM_SVC_ARGS *Args
+ IN OUT ARM_SVC_ARGS *Args
);
#endif // ARM_SVC_LIB_H_
diff --git a/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h b/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h index 57dc555e13..63d5dc78de 100644 --- a/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h +++ b/ArmPkg/Include/Library/DefaultExceptionHandlerLib.h @@ -18,8 +18,8 @@ **/
VOID
DefaultExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
);
#endif // DEFAULT_EXCEPTION_HANDLER_LIB_H_
diff --git a/ArmPkg/Include/Library/OemMiscLib.h b/ArmPkg/Include/Library/OemMiscLib.h index 0b03fe8d4d..569cd51352 100644 --- a/ArmPkg/Include/Library/OemMiscLib.h +++ b/ArmPkg/Include/Library/OemMiscLib.h @@ -8,15 +8,13 @@ *
**/
-
#ifndef OEM_MISC_LIB_H_
#define OEM_MISC_LIB_H_
#include <Uefi.h>
#include <IndustryStandard/SmBios.h>
-typedef enum
-{
+typedef enum {
CpuCacheL1 = 1,
CpuCacheL2,
CpuCacheL3,
@@ -27,37 +25,35 @@ typedef enum CpuCacheLevelMax
} OEM_MISC_CPU_CACHE_LEVEL;
-typedef struct
-{
- UINT8 Voltage; ///< Processor voltage
- UINT16 CurrentSpeed; ///< Current clock speed in MHz
- UINT16 MaxSpeed; ///< Maximum clock speed in MHz
- UINT16 ExternalClock; ///< External clock speed in MHz
- UINT16 CoreCount; ///< Number of cores available
- UINT16 CoresEnabled; ///< Number of cores enabled
- UINT16 ThreadCount; ///< Number of threads per processor
+typedef struct {
+ UINT8 Voltage; ///< Processor voltage
+ UINT16 CurrentSpeed; ///< Current clock speed in MHz
+ UINT16 MaxSpeed; ///< Maximum clock speed in MHz
+ UINT16 ExternalClock; ///< External clock speed in MHz
+ UINT16 CoreCount; ///< Number of cores available
+ UINT16 CoresEnabled; ///< Number of cores enabled
+ UINT16 ThreadCount; ///< Number of threads per processor
} OEM_MISC_PROCESSOR_DATA;
-typedef enum
-{
- ProductNameType01,
- SerialNumType01,
- UuidType01,
- SystemManufacturerType01,
- SkuNumberType01,
- FamilyType01,
- AssertTagType02,
- SerialNumberType02,
- BoardManufacturerType02,
- SkuNumberType02,
- ChassisLocationType02,
- AssetTagType03,
- SerialNumberType03,
- VersionType03,
- ChassisTypeType03,
- ManufacturerType03,
- SkuNumberType03,
- SmbiosHiiStringFieldMax
+typedef enum {
+ ProductNameType01,
+ SerialNumType01,
+ UuidType01,
+ SystemManufacturerType01,
+ SkuNumberType01,
+ FamilyType01,
+ AssertTagType02,
+ SerialNumberType02,
+ BoardManufacturerType02,
+ SkuNumberType02,
+ ChassisLocationType02,
+ AssetTagType03,
+ SerialNumberType03,
+ VersionType03,
+ ChassisTypeType03,
+ ManufacturerType03,
+ SkuNumberType03,
+ SmbiosHiiStringFieldMax
} OEM_MISC_SMBIOS_HII_STRING_FIELD;
/*
@@ -74,7 +70,7 @@ typedef enum UINTN
EFIAPI
OemGetCpuFreq (
- IN UINT8 ProcessorIndex
+ IN UINT8 ProcessorIndex
);
/** Gets information about the specified processor and stores it in
@@ -90,10 +86,10 @@ OemGetCpuFreq ( BOOLEAN
EFIAPI
OemGetProcessorInformation (
- IN UINTN ProcessorIndex,
- IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
- IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
- IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
+ IN UINTN ProcessorIndex,
+ IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
+ IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
+ IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
);
/** Gets information about the cache at the specified cache level.
@@ -109,11 +105,11 @@ OemGetProcessorInformation ( BOOLEAN
EFIAPI
OemGetCacheInformation (
- IN UINT8 ProcessorIndex,
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache,
- IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
+ IN UINT8 ProcessorIndex,
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache,
+ IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
);
/** Gets the maximum number of processors supported by the platform.
@@ -145,7 +141,7 @@ OemGetChassisType ( BOOLEAN
EFIAPI
OemIsProcessorPresent (
- IN UINTN ProcessorIndex
+ IN UINTN ProcessorIndex
);
/** Updates the HII string for the specified field.
@@ -157,9 +153,9 @@ OemIsProcessorPresent ( VOID
EFIAPI
OemUpdateSmbiosInfo (
- IN EFI_HII_HANDLE HiiHandle,
- IN EFI_STRING_ID TokenToUpdate,
- IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
+ IN EFI_HII_HANDLE HiiHandle,
+ IN EFI_STRING_ID TokenToUpdate,
+ IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
);
/** Fetches the Type 32 boot information status.
diff --git a/ArmPkg/Include/Library/OpteeLib.h b/ArmPkg/Include/Library/OpteeLib.h index b9399d2e18..593c32b135 100644 --- a/ArmPkg/Include/Library/OpteeLib.h +++ b/ArmPkg/Include/Library/OpteeLib.h @@ -15,24 +15,24 @@ * The 'Trusted OS Call UID' is supposed to return the following UUID for
* OP-TEE OS. This is a 128-bit value.
*/
-#define OPTEE_OS_UID0 0x384fb3e0
-#define OPTEE_OS_UID1 0xe7f811e3
-#define OPTEE_OS_UID2 0xaf630002
-#define OPTEE_OS_UID3 0xa5d5c51b
+#define OPTEE_OS_UID0 0x384fb3e0
+#define OPTEE_OS_UID1 0xe7f811e3
+#define OPTEE_OS_UID2 0xaf630002
+#define OPTEE_OS_UID3 0xa5d5c51b
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE 0x0
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT 0x1
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT 0x2
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT 0x3
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT 0x9
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT 0xa
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT 0xb
-#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff
+#define OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK 0xff
-#define OPTEE_SUCCESS 0x00000000
-#define OPTEE_ORIGIN_COMMUNICATION 0x00000002
-#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E
+#define OPTEE_SUCCESS 0x00000000
+#define OPTEE_ORIGIN_COMMUNICATION 0x00000002
+#define OPTEE_ERROR_COMMUNICATION 0xFFFF000E
typedef struct {
UINT64 BufferAddress;
@@ -47,44 +47,44 @@ typedef struct { } OPTEE_MESSAGE_PARAM_VALUE;
typedef union {
- OPTEE_MESSAGE_PARAM_MEMORY Memory;
- OPTEE_MESSAGE_PARAM_VALUE Value;
+ OPTEE_MESSAGE_PARAM_MEMORY Memory;
+ OPTEE_MESSAGE_PARAM_VALUE Value;
} OPTEE_MESSAGE_PARAM_UNION;
typedef struct {
- UINT64 Attribute;
- OPTEE_MESSAGE_PARAM_UNION Union;
+ UINT64 Attribute;
+ OPTEE_MESSAGE_PARAM_UNION Union;
} OPTEE_MESSAGE_PARAM;
-#define OPTEE_MAX_CALL_PARAMS 4
+#define OPTEE_MAX_CALL_PARAMS 4
typedef struct {
- UINT32 Command;
- UINT32 Function;
- UINT32 Session;
- UINT32 CancelId;
- UINT32 Pad;
- UINT32 Return;
- UINT32 ReturnOrigin;
- UINT32 NumParams;
+ UINT32 Command;
+ UINT32 Function;
+ UINT32 Session;
+ UINT32 CancelId;
+ UINT32 Pad;
+ UINT32 Return;
+ UINT32 ReturnOrigin;
+ UINT32 NumParams;
// NumParams tells the actual number of element in Params
- OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];
+ OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS];
} OPTEE_MESSAGE_ARG;
typedef struct {
- EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application
- UINT32 Session; // [out] Session id
- UINT32 Return; // [out] Return value
- UINT32 ReturnOrigin; // [out] Origin of the return value
+ EFI_GUID Uuid; // [in] GUID/UUID of the Trusted Application
+ UINT32 Session; // [out] Session id
+ UINT32 Return; // [out] Return value
+ UINT32 ReturnOrigin; // [out] Origin of the return value
} OPTEE_OPEN_SESSION_ARG;
typedef struct {
- UINT32 Function; // [in] Trusted Application function, specific to the TA
- UINT32 Session; // [in] Session id
- UINT32 Return; // [out] Return value
- UINT32 ReturnOrigin; // [out] Origin of the return value
- OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked
+ UINT32 Function; // [in] Trusted Application function, specific to the TA
+ UINT32 Session; // [in] Session id
+ UINT32 Return; // [out] Return value
+ UINT32 ReturnOrigin; // [out] Origin of the return value
+ OPTEE_MESSAGE_PARAM Params[OPTEE_MAX_CALL_PARAMS]; // Params for function to be invoked
} OPTEE_INVOKE_FUNCTION_ARG;
BOOLEAN
@@ -102,19 +102,19 @@ OpteeInit ( EFI_STATUS
EFIAPI
OpteeOpenSession (
- IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
+ IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
);
EFI_STATUS
EFIAPI
OpteeCloseSession (
- IN UINT32 Session
+ IN UINT32 Session
);
EFI_STATUS
EFIAPI
OpteeInvokeFunction (
- IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
+ IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
);
#endif // OPTEE_LIB_H_
diff --git a/ArmPkg/Include/Library/SemihostLib.h b/ArmPkg/Include/Library/SemihostLib.h index 590728c804..e0ff9251cb 100644 --- a/ArmPkg/Include/Library/SemihostLib.h +++ b/ArmPkg/Include/Library/SemihostLib.h @@ -17,12 +17,12 @@ *
*/
-#define SEMIHOST_FILE_MODE_READ (0 << 2)
-#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
-#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
-#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)
-#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
-#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
+#define SEMIHOST_FILE_MODE_READ (0 << 2)
+#define SEMIHOST_FILE_MODE_WRITE (1 << 2)
+#define SEMIHOST_FILE_MODE_APPEND (2 << 2)
+#define SEMIHOST_FILE_MODE_UPDATE (1 << 1)
+#define SEMIHOST_FILE_MODE_BINARY (1 << 0)
+#define SEMIHOST_FILE_MODE_ASCII (0 << 0)
BOOLEAN
SemihostConnectionSupported (
@@ -31,9 +31,9 @@ SemihostConnectionSupported ( RETURN_STATUS
SemihostFileOpen (
- IN CHAR8 *FileName,
- IN UINT32 Mode,
- OUT UINTN *FileHandle
+ IN CHAR8 *FileName,
+ IN UINT32 Mode,
+ OUT UINTN *FileHandle
);
RETURN_STATUS
@@ -81,7 +81,7 @@ SemihostFileLength ( **/
RETURN_STATUS
-SemihostFileTmpName(
+SemihostFileTmpName (
OUT VOID *Buffer,
IN UINT8 Identifier,
IN UINTN Length
@@ -89,7 +89,7 @@ SemihostFileTmpName( RETURN_STATUS
SemihostFileRemove (
- IN CHAR8 *FileName
+ IN CHAR8 *FileName
);
/**
@@ -104,7 +104,7 @@ SemihostFileRemove ( **/
RETURN_STATUS
-SemihostFileRename(
+SemihostFileRename (
IN CHAR8 *FileName,
IN CHAR8 *NewFileName
);
@@ -116,17 +116,17 @@ SemihostReadCharacter ( VOID
SemihostWriteCharacter (
- IN CHAR8 Character
+ IN CHAR8 Character
);
VOID
SemihostWriteString (
- IN CHAR8 *String
+ IN CHAR8 *String
);
UINT32
SemihostSystem (
- IN CHAR8 *CommandLine
+ IN CHAR8 *CommandLine
);
#endif // SEMIHOSTING_LIB_H_
diff --git a/ArmPkg/Include/Library/StandaloneMmMmuLib.h b/ArmPkg/Include/Library/StandaloneMmMmuLib.h index ccc016d035..c27020def0 100644 --- a/ArmPkg/Include/Library/StandaloneMmMmuLib.h +++ b/ArmPkg/Include/Library/StandaloneMmMmuLib.h @@ -11,26 +11,26 @@ EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
);
#endif /* STANDALONE_MM_MMU_LIB_ */
diff --git a/ArmPkg/Include/Ppi/ArmMpCoreInfo.h b/ArmPkg/Include/Ppi/ArmMpCoreInfo.h index b1e404ce13..c9f2ac6fc1 100644 --- a/ArmPkg/Include/Ppi/ArmMpCoreInfo.h +++ b/ArmPkg/Include/Ppi/ArmMpCoreInfo.h @@ -32,10 +32,10 @@ **/
typedef
EFI_STATUS
-(EFIAPI * ARM_MP_CORE_INFO_GET) (
+(EFIAPI *ARM_MP_CORE_INFO_GET)(
OUT UINTN *ArmCoreCount,
OUT ARM_CORE_INFO **ArmCoreTable
-);
+ );
///
/// This service abstracts the ability to migrate contents of the platform early memory store.
@@ -43,10 +43,10 @@ EFI_STATUS /// This PPI was optional.
///
typedef struct {
- ARM_MP_CORE_INFO_GET GetMpCoreInfo;
+ ARM_MP_CORE_INFO_GET GetMpCoreInfo;
} ARM_MP_CORE_INFO_PPI;
-extern EFI_GUID gArmMpCoreInfoPpiGuid;
-extern EFI_GUID gArmMpCoreInfoGuid;
+extern EFI_GUID gArmMpCoreInfoPpiGuid;
+extern EFI_GUID gArmMpCoreInfoGuid;
#endif // ARM_MP_CORE_INFO_PPI_H_
diff --git a/ArmPkg/Include/Protocol/ArmScmi.h b/ArmPkg/Include/Protocol/ArmScmi.h index aedea8f61f..93edec769c 100644 --- a/ArmPkg/Include/Protocol/ArmScmi.h +++ b/ArmPkg/Include/Protocol/ArmScmi.h @@ -15,7 +15,6 @@ /* As per SCMI specification, maximum allowed ASCII string length
for various return values/parameters of a SCMI message.
*/
-#define SCMI_MAX_STR_LEN 16
+#define SCMI_MAX_STR_LEN 16
#endif /* ARM_SCMI_H_ */
-
diff --git a/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h b/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h index c4b81c0f56..f6d97dd6da 100644 --- a/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiBaseProtocol.h @@ -17,24 +17,24 @@ #define BASE_PROTOCOL_VERSION_V1 0x10000
#define BASE_PROTOCOL_VERSION_V2 0x20000
-#define NUM_PROTOCOL_MASK 0xFFU
-#define NUM_AGENT_MASK 0xFFU
+#define NUM_PROTOCOL_MASK 0xFFU
+#define NUM_AGENT_MASK 0xFFU
-#define NUM_AGENT_SHIFT 0x8
+#define NUM_AGENT_SHIFT 0x8
/** Returns total number of protocols that are
implemented (excluding the Base protocol)
*/
-#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)
+#define SCMI_TOTAL_PROTOCOLS(Attr) (Attr & NUM_PROTOCOL_MASK)
// Returns total number of agents in the system.
-#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)
+#define SCMI_TOTAL_AGENTS(Attr) ((Attr >> NUM_AGENT_SHIFT) & NUM_AGENT_MASK)
#define ARM_SCMI_BASE_PROTOCOL_GUID { \
0xd7e5abe9, 0x33ab, 0x418e, {0x9f, 0x91, 0x72, 0xda, 0xe2, 0xba, 0x8e, 0x2f} \
}
-extern EFI_GUID gArmScmiBaseProtocolGuid;
+extern EFI_GUID gArmScmiBaseProtocolGuid;
typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL;
@@ -50,7 +50,7 @@ typedef struct _SCMI_BASE_PROTOCOL SCMI_BASE_PROTOCOL; **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_GET_VERSION) (
+(EFIAPI *SCMI_BASE_GET_VERSION)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *Version
);
@@ -67,7 +67,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS) (
+(EFIAPI *SCMI_BASE_GET_TOTAL_PROTOCOLS)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *TotalProtocols
);
@@ -85,7 +85,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_DISCOVER_VENDOR) (
+(EFIAPI *SCMI_BASE_DISCOVER_VENDOR)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
);
@@ -103,7 +103,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR) (
+(EFIAPI *SCMI_BASE_DISCOVER_SUB_VENDOR)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT8 VendorIdentifier[SCMI_MAX_STR_LEN]
);
@@ -120,7 +120,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION) (
+(EFIAPI *SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION)(
IN SCMI_BASE_PROTOCOL *This,
OUT UINT32 *ImplementationVersion
);
@@ -141,7 +141,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS) (
+(EFIAPI *SCMI_BASE_DISCOVER_LIST_PROTOCOLS)(
IN SCMI_BASE_PROTOCOL *This,
IN OUT UINT32 *ProtocolListSize,
OUT UINT8 *ProtocolList
@@ -149,20 +149,20 @@ EFI_STATUS // Base protocol.
typedef struct _SCMI_BASE_PROTOCOL {
- SCMI_BASE_GET_VERSION GetVersion;
- SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;
- SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;
- SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;
- SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;
- SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;
+ SCMI_BASE_GET_VERSION GetVersion;
+ SCMI_BASE_GET_TOTAL_PROTOCOLS GetTotalProtocols;
+ SCMI_BASE_DISCOVER_VENDOR DiscoverVendor;
+ SCMI_BASE_DISCOVER_SUB_VENDOR DiscoverSubVendor;
+ SCMI_BASE_DISCOVER_IMPLEMENTATION_VERSION DiscoverImplementationVersion;
+ SCMI_BASE_DISCOVER_LIST_PROTOCOLS DiscoverListProtocols;
} SCMI_BASE_PROTOCOL;
// SCMI Message IDs for Base protocol.
typedef enum {
- ScmiMessageIdBaseDiscoverVendor = 0x3,
- ScmiMessageIdBaseDiscoverSubVendor = 0x4,
- ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
- ScmiMessageIdBaseDiscoverListProtocols = 0x6
+ ScmiMessageIdBaseDiscoverVendor = 0x3,
+ ScmiMessageIdBaseDiscoverSubVendor = 0x4,
+ ScmiMessageIdBaseDiscoverImplementationVersion = 0x5,
+ ScmiMessageIdBaseDiscoverListProtocols = 0x6
} SCMI_MESSAGE_ID_BASE;
#endif /* ARM_SCMI_BASE_PROTOCOL_H_ */
diff --git a/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h b/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h index 0e26491a62..d37d23f40c 100644 --- a/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiClock2Protocol.h @@ -15,13 +15,13 @@ #include <Protocol/ArmScmi.h>
#include <Protocol/ArmScmiClockProtocol.h>
-#define ARM_SCMI_CLOCK2_PROTOCOL_GUID { \
+#define ARM_SCMI_CLOCK2_PROTOCOL_GUID {\
0xb8d8caf2, 0x9e94, 0x462c, { 0xa8, 0x34, 0x6c, 0x99, 0xfc, 0x05, 0xef, 0xcf } \
}
-extern EFI_GUID gArmScmiClock2ProtocolGuid;
+extern EFI_GUID gArmScmiClock2ProtocolGuid;
-#define SCMI_CLOCK2_PROTOCOL_VERSION 1
+#define SCMI_CLOCK2_PROTOCOL_VERSION 1
typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL;
@@ -39,7 +39,7 @@ typedef struct _SCMI_CLOCK2_PROTOCOL SCMI_CLOCK2_PROTOCOL; **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_GET_VERSION) (
+(EFIAPI *SCMI_CLOCK2_GET_VERSION)(
IN SCMI_CLOCK2_PROTOCOL *This,
OUT UINT32 *Version
);
@@ -57,7 +57,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS) (
+(EFIAPI *SCMI_CLOCK2_GET_TOTAL_CLOCKS)(
IN SCMI_CLOCK2_PROTOCOL *This,
OUT UINT32 *TotalClocks
);
@@ -77,7 +77,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES) (
+(EFIAPI *SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT BOOLEAN *Enabled,
@@ -109,7 +109,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES) (
+(EFIAPI *SCMI_CLOCK2_DESCRIBE_RATES)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format,
@@ -131,7 +131,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_RATE_GET) (
+(EFIAPI *SCMI_CLOCK2_RATE_GET)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
OUT UINT64 *Rate
@@ -149,7 +149,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_RATE_SET) (
+(EFIAPI *SCMI_CLOCK2_RATE_SET)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
IN UINT64 Rate
@@ -168,24 +168,24 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK2_ENABLE) (
+(EFIAPI *SCMI_CLOCK2_ENABLE)(
IN SCMI_CLOCK2_PROTOCOL *This,
IN UINT32 ClockId,
IN BOOLEAN Enable
);
typedef struct _SCMI_CLOCK2_PROTOCOL {
- SCMI_CLOCK2_GET_VERSION GetVersion;
- SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;
- SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;
- SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;
- SCMI_CLOCK2_RATE_GET RateGet;
- SCMI_CLOCK2_RATE_SET RateSet;
+ SCMI_CLOCK2_GET_VERSION GetVersion;
+ SCMI_CLOCK2_GET_TOTAL_CLOCKS GetTotalClocks;
+ SCMI_CLOCK2_GET_CLOCK_ATTRIBUTES GetClockAttributes;
+ SCMI_CLOCK2_DESCRIBE_RATES DescribeRates;
+ SCMI_CLOCK2_RATE_GET RateGet;
+ SCMI_CLOCK2_RATE_SET RateSet;
// Extension to original ClockProtocol, added here so SCMI_CLOCK2_PROTOCOL
// can be cast to SCMI_CLOCK_PROTOCOL
- UINTN Version; // For future expandability
- SCMI_CLOCK2_ENABLE Enable;
+ UINTN Version; // For future expandability
+ SCMI_CLOCK2_ENABLE Enable;
} SCMI_CLOCK2_PROTOCOL;
#endif /* ARM_SCMI_CLOCK2_PROTOCOL_H_ */
diff --git a/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h b/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h index 4210a53cf9..7cdc61ff7c 100644 --- a/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiClockProtocol.h @@ -14,11 +14,11 @@ #include <Protocol/ArmScmi.h>
-#define ARM_SCMI_CLOCK_PROTOCOL_GUID { \
+#define ARM_SCMI_CLOCK_PROTOCOL_GUID {\
0x91ce67a8, 0xe0aa, 0x4012, {0xb9, 0x9f, 0xb6, 0xfc, 0xf3, 0x4, 0x8e, 0xaa} \
}
-extern EFI_GUID gArmScmiClockProtocolGuid;
+extern EFI_GUID gArmScmiClockProtocolGuid;
// Message Type for clock management protocol.
typedef enum {
@@ -35,21 +35,21 @@ typedef enum { } SCMI_CLOCK_RATE_FORMAT;
// Clock management protocol version.
-#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000
+#define SCMI_CLOCK_PROTOCOL_VERSION 0x10000
-#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU
-#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16
-#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU
+#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK 0xFFU
+#define SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT 16
+#define SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK 0xFFFFU
/** Total number of pending asynchronous clock rates changes
supported by the SCP, Attr Bits[23:16]
*/
-#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \
+#define SCMI_CLOCK_PROTOCOL_MAX_ASYNC_CLK_RATES(Attr) ( \
(Attr >> SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_SHIFT) && \
SCMI_CLOCK_PROTOCOL_PENDING_ASYNC_RATES_MASK)
// Total of clock devices supported by the SCP, Attr Bits[15:0]
-#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)
+#define SCMI_CLOCK_PROTOCOL_TOTAL_CLKS(Attr) (Attr & SCMI_CLOCK_PROTOCOL_NUM_CLOCKS_MASK)
#pragma pack(1)
@@ -57,18 +57,18 @@ typedef enum { either Rate or Min/Max/Step triplet is valid.
*/
typedef struct {
- UINT64 Min;
- UINT64 Max;
- UINT64 Step;
+ UINT64 Min;
+ UINT64 Max;
+ UINT64 Step;
} SCMI_CLOCK_RATE_CONTINUOUS;
typedef struct {
- UINT64 Rate;
+ UINT64 Rate;
} SCMI_CLOCK_RATE_DISCRETE;
typedef union {
- SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
- SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
+ SCMI_CLOCK_RATE_CONTINUOUS ContinuousRate;
+ SCMI_CLOCK_RATE_DISCRETE DiscreteRate;
} SCMI_CLOCK_RATE;
#pragma pack()
@@ -89,7 +89,7 @@ typedef struct _SCMI_CLOCK_PROTOCOL SCMI_CLOCK_PROTOCOL; **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_GET_VERSION) (
+(EFIAPI *SCMI_CLOCK_GET_VERSION)(
IN SCMI_CLOCK_PROTOCOL *This,
OUT UINT32 *Version
);
@@ -107,7 +107,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS) (
+(EFIAPI *SCMI_CLOCK_GET_TOTAL_CLOCKS)(
IN SCMI_CLOCK_PROTOCOL *This,
OUT UINT32 *TotalClocks
);
@@ -127,7 +127,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES) (
+(EFIAPI *SCMI_CLOCK_GET_CLOCK_ATTRIBUTES)(
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT BOOLEAN *Enabled,
@@ -159,7 +159,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES) (
+(EFIAPI *SCMI_CLOCK_DESCRIBE_RATES)(
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT SCMI_CLOCK_RATE_FORMAT *Format,
@@ -181,7 +181,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_RATE_GET) (
+(EFIAPI *SCMI_CLOCK_RATE_GET)(
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
OUT UINT64 *Rate
@@ -199,20 +199,19 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_CLOCK_RATE_SET) (
+(EFIAPI *SCMI_CLOCK_RATE_SET)(
IN SCMI_CLOCK_PROTOCOL *This,
IN UINT32 ClockId,
IN UINT64 Rate
);
typedef struct _SCMI_CLOCK_PROTOCOL {
- SCMI_CLOCK_GET_VERSION GetVersion;
- SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;
- SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;
- SCMI_CLOCK_DESCRIBE_RATES DescribeRates;
- SCMI_CLOCK_RATE_GET RateGet;
- SCMI_CLOCK_RATE_SET RateSet;
+ SCMI_CLOCK_GET_VERSION GetVersion;
+ SCMI_CLOCK_GET_TOTAL_CLOCKS GetTotalClocks;
+ SCMI_CLOCK_GET_CLOCK_ATTRIBUTES GetClockAttributes;
+ SCMI_CLOCK_DESCRIBE_RATES DescribeRates;
+ SCMI_CLOCK_RATE_GET RateGet;
+ SCMI_CLOCK_RATE_SET RateSet;
} SCMI_CLOCK_PROTOCOL;
#endif /* ARM_SCMI_CLOCK_PROTOCOL_H_ */
-
diff --git a/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h b/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h index 8c70aa7528..7e548e4765 100644 --- a/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h +++ b/ArmPkg/Include/Protocol/ArmScmiPerformanceProtocol.h @@ -20,15 +20,15 @@ 0x9b8ba84, 0x3dd3, 0x49a6, {0xa0, 0x5a, 0x31, 0x34, 0xa5, 0xf0, 0x7b, 0xad} \
}
-extern EFI_GUID gArmScmiPerformanceProtocolGuid;
+extern EFI_GUID gArmScmiPerformanceProtocolGuid;
typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL;
#pragma pack(1)
-#define POWER_IN_MW_SHIFT 16
-#define POWER_IN_MW_MASK 0x1
-#define NUM_PERF_DOMAINS_MASK 0xFFFF
+#define POWER_IN_MW_SHIFT 16
+#define POWER_IN_MW_MASK 0x1
+#define NUM_PERF_DOMAINS_MASK 0xFFFF
// Total number of performance domains, Attr Bits [15:0]
#define SCMI_PERF_TOTAL_DOMAINS(Attr) (Attr & NUM_PERF_DOMAINS_MASK)
@@ -39,41 +39,41 @@ typedef struct _SCMI_PERFORMANCE_PROTOCOL SCMI_PERFORMANCE_PROTOCOL; // Performance protocol attributes return values.
typedef struct {
- UINT32 Attributes;
- UINT64 StatisticsAddress;
- UINT32 StatisticsLen;
+ UINT32 Attributes;
+ UINT64 StatisticsAddress;
+ UINT32 StatisticsLen;
} SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES;
-#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)
-#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)
-#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)
-#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)
-#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)
+#define SCMI_PERF_SUPPORT_LVL_CHANGE_NOTIFY(Attr) ((Attr >> 28) & 0x1)
+#define SCMI_PERF_SUPPORT_LIM_CHANGE_NOTIFY(Attr) ((Attr >> 29) & 0x1)
+#define SCMI_PERF_SUPPORT_SET_LVL(Attr) ((Attr >> 30) & 0x1)
+#define SCMI_PERF_SUPPORT_SET_LIM(Attr) ((Attr >> 31) & 0x1)
+#define SCMI_PERF_RATE_LIMIT(RateLimit) (RateLimit & 0xFFF)
// Performance protocol domain attributes.
typedef struct {
- UINT32 Attributes;
- UINT32 RateLimit;
- UINT32 SustainedFreq;
- UINT32 SustainedPerfLevel;
- UINT8 Name[SCMI_MAX_STR_LEN];
+ UINT32 Attributes;
+ UINT32 RateLimit;
+ UINT32 SustainedFreq;
+ UINT32 SustainedPerfLevel;
+ UINT8 Name[SCMI_MAX_STR_LEN];
} SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES;
// Worst case latency in microseconds, Bits[15:0]
-#define PERF_LATENCY_MASK 0xFFFF
-#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)
+#define PERF_LATENCY_MASK 0xFFFF
+#define SCMI_PERFORMANCE_PROTOCOL_LATENCY(Latency) (Latency & PERF_LATENCY_MASK)
// Performance protocol performance level.
typedef struct {
- UINT32 Level;
- UINT32 PowerCost;
- UINT32 Latency;
+ UINT32 Level;
+ UINT32 PowerCost;
+ UINT32 Latency;
} SCMI_PERFORMANCE_LEVEL;
// Performance protocol performance limit.
typedef struct {
- UINT32 RangeMax;
- UINT32 RangeMin;
+ UINT32 RangeMax;
+ UINT32 RangeMin;
} SCMI_PERFORMANCE_LIMITS;
#pragma pack()
@@ -92,7 +92,7 @@ typedef struct { **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_GET_VERSION) (
+(EFIAPI *SCMI_PERFORMANCE_GET_VERSION)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT UINT32 *Version
);
@@ -109,7 +109,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES) (
+(EFIAPI *SCMI_PERFORMANCE_GET_ATTRIBUTES)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
OUT SCMI_PERFORMANCE_PROTOCOL_ATTRIBUTES *Attributes
@@ -128,7 +128,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES) (
+(EFIAPI *SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT SCMI_PERFORMANCE_DOMAIN_ATTRIBUTES *DomainAttributes
@@ -153,7 +153,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS) (
+(EFIAPI *SCMI_PERFORMANCE_DESCRIBE_LEVELS)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT UINT32 *NumLevels,
@@ -173,7 +173,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET) (
+(EFIAPI *SCMI_PERFORMANCE_LIMITS_SET)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN SCMI_PERFORMANCE_LIMITS *Limits
@@ -192,7 +192,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET) (
+(EFIAPI *SCMI_PERFORMANCE_LIMITS_GET)(
SCMI_PERFORMANCE_PROTOCOL *This,
UINT32 DomainId,
SCMI_PERFORMANCE_LIMITS *Limits
@@ -210,7 +210,7 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET) (
+(EFIAPI *SCMI_PERFORMANCE_LEVEL_SET)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
IN UINT32 Level
@@ -229,21 +229,21 @@ EFI_STATUS **/
typedef
EFI_STATUS
-(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET) (
+(EFIAPI *SCMI_PERFORMANCE_LEVEL_GET)(
IN SCMI_PERFORMANCE_PROTOCOL *This,
IN UINT32 DomainId,
OUT UINT32 *Level
);
typedef struct _SCMI_PERFORMANCE_PROTOCOL {
- SCMI_PERFORMANCE_GET_VERSION GetVersion;
- SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;
- SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;
- SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;
- SCMI_PERFORMANCE_LIMITS_SET LimitsSet;
- SCMI_PERFORMANCE_LIMITS_GET LimitsGet;
- SCMI_PERFORMANCE_LEVEL_SET LevelSet;
- SCMI_PERFORMANCE_LEVEL_GET LevelGet;
+ SCMI_PERFORMANCE_GET_VERSION GetVersion;
+ SCMI_PERFORMANCE_GET_ATTRIBUTES GetProtocolAttributes;
+ SCMI_PERFORMANCE_GET_DOMAIN_ATTRIBUTES GetDomainAttributes;
+ SCMI_PERFORMANCE_DESCRIBE_LEVELS DescribeLevels;
+ SCMI_PERFORMANCE_LIMITS_SET LimitsSet;
+ SCMI_PERFORMANCE_LIMITS_GET LimitsGet;
+ SCMI_PERFORMANCE_LEVEL_SET LevelSet;
+ SCMI_PERFORMANCE_LEVEL_GET LevelGet;
} SCMI_PERFORMANCE_PROTOCOL;
typedef enum {
@@ -256,4 +256,3 @@ typedef enum { } SCMI_MESSAGE_ID_PERFORMANCE;
#endif /* ARM_SCMI_PERFORMANCE_PROTOCOL_H_ */
-
diff --git a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c index 4b1c9ac49e..d663a76a9b 100644 --- a/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c +++ b/ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.c @@ -7,7 +7,6 @@ **/
-
#include <Base.h>
#include <Library/ArmLib.h>
#include <Library/BaseLib.h>
@@ -16,16 +15,15 @@ #include <Library/PcdLib.h>
#include <Library/ArmGenericTimerCounterLib.h>
-#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)
+#define TICKS_PER_MICRO_SEC (PcdGet32 (PcdArmArchTimerFreqInHz)/1000000U)
// Select appropriate multiply function for platform architecture.
#ifdef MDE_CPU_ARM
-#define MULT_U64_X_N MultU64x32
+#define MULT_U64_X_N MultU64x32
#else
-#define MULT_U64_X_N MultU64x64
+#define MULT_U64_X_N MultU64x64
#endif
-
RETURN_STATUS
EFIAPI
TimerConstructor (
@@ -36,7 +34,6 @@ TimerConstructor ( // Check if the ARM Generic Timer Extension is implemented.
//
if (ArmIsArchTimerImplemented ()) {
-
//
// Check if Architectural Timer frequency is pre-determined by the platform
// (ie. nonzero).
@@ -49,7 +46,7 @@ TimerConstructor ( //
ASSERT (TICKS_PER_MICRO_SEC);
-#ifdef MDE_CPU_ARM
+ #ifdef MDE_CPU_ARM
//
// Only set the frequency for ARMv7. We expect the secure firmware to
// have already done it.
@@ -59,7 +56,8 @@ TimerConstructor ( if (ArmHasSecurityExtensions ()) {
ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
}
-#endif
+
+ #endif
}
//
@@ -68,7 +66,6 @@ TimerConstructor ( // If the reset value (0) is returned, just ASSERT.
//
ASSERT (ArmGenericTimerGetTimerFreq () != 0);
-
} else {
DEBUG ((DEBUG_ERROR, "ARM Architectural Timer is not available in the CPU, hence this library cannot be used.\n"));
ASSERT (0);
@@ -90,16 +87,16 @@ EFIAPI GetPlatformTimerFreq (
)
{
- UINTN TimerFreq;
+ UINTN TimerFreq;
TimerFreq = PcdGet32 (PcdArmArchTimerFreqInHz);
if (TimerFreq == 0) {
TimerFreq = ArmGenericTimerGetTimerFreq ();
}
+
return TimerFreq;
}
-
/**
Stalls the CPU for the number of microseconds specified by MicroSeconds.
@@ -111,11 +108,11 @@ GetPlatformTimerFreq ( UINTN
EFIAPI
MicroSecondDelay (
- IN UINTN MicroSeconds
+ IN UINTN MicroSeconds
)
{
- UINT64 TimerTicks64;
- UINT64 SystemCounterVal;
+ UINT64 TimerTicks64;
+ UINT64 SystemCounterVal;
// Calculate counter ticks that represent requested delay:
// = MicroSeconds x TICKS_PER_MICRO_SEC
@@ -141,7 +138,6 @@ MicroSecondDelay ( return MicroSeconds;
}
-
/**
Stalls the CPU for at least the given number of nanoseconds.
@@ -158,13 +154,13 @@ MicroSecondDelay ( UINTN
EFIAPI
NanoSecondDelay (
- IN UINTN NanoSeconds
+ IN UINTN NanoSeconds
)
{
UINTN MicroSeconds;
// Round up to 1us Tick Number
- MicroSeconds = NanoSeconds / 1000;
+ MicroSeconds = NanoSeconds / 1000;
MicroSeconds += ((NanoSeconds % 1000) == 0) ? 0 : 1;
MicroSecondDelay (MicroSeconds);
@@ -219,13 +215,13 @@ GetPerformanceCounter ( UINT64
EFIAPI
GetPerformanceCounterProperties (
- OUT UINT64 *StartValue OPTIONAL,
- OUT UINT64 *EndValue OPTIONAL
+ OUT UINT64 *StartValue OPTIONAL,
+ OUT UINT64 *EndValue OPTIONAL
)
{
if (StartValue != NULL) {
// Timer starts at 0
- *StartValue = (UINT64)0ULL ;
+ *StartValue = (UINT64)0ULL;
}
if (EndValue != NULL) {
@@ -250,7 +246,7 @@ GetPerformanceCounterProperties ( UINT64
EFIAPI
GetTimeInNanoSecond (
- IN UINT64 Ticks
+ IN UINT64 Ticks
)
{
UINT64 NanoSeconds;
@@ -267,7 +263,8 @@ GetTimeInNanoSecond ( DivU64x32Remainder (
Ticks,
TimerFreq,
- &Remainder),
+ &Remainder
+ ),
1000000000U
);
@@ -277,8 +274,9 @@ GetTimeInNanoSecond ( //
NanoSeconds += DivU64x32 (
MULT_U64_X_N (
- (UINT64) Remainder,
- 1000000000U),
+ (UINT64)Remainder,
+ 1000000000U
+ ),
TimerFreq
);
diff --git a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c index db9290f275..bad5d244cb 100644 --- a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c +++ b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c @@ -20,20 +20,21 @@ CacheRangeOperation ( IN UINTN LineLength
)
{
- UINTN ArmCacheLineAlignmentMask;
+ UINTN ArmCacheLineAlignmentMask;
// Align address (rounding down)
- UINTN AlignedAddress;
- UINTN EndAddress;
+ UINTN AlignedAddress;
+ UINTN EndAddress;
ArmCacheLineAlignmentMask = LineLength - 1;
- AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
- EndAddress = (UINTN)Start + Length;
+ AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
+ EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
- LineOperation(AlignedAddress);
+ LineOperation (AlignedAddress);
AlignedAddress += LineLength;
}
+
ArmDataSynchronizationBarrier ();
}
@@ -58,15 +59,22 @@ InvalidateDataCache ( VOID *
EFIAPI
InvalidateInstructionCacheRange (
- IN VOID *Address,
- IN UINTN Length
+ IN VOID *Address,
+ IN UINTN Length
)
{
- CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryToPoUByMVA,
- ArmDataCacheLineLength ());
- CacheRangeOperation (Address, Length,
+ CacheRangeOperation (
+ Address,
+ Length,
+ ArmCleanDataCacheEntryToPoUByMVA,
+ ArmDataCacheLineLength ()
+ );
+ CacheRangeOperation (
+ Address,
+ Length,
ArmInvalidateInstructionCacheEntryToPoUByMVA,
- ArmInstructionCacheLineLength ());
+ ArmInstructionCacheLineLength ()
+ );
ArmInstructionSynchronizationBarrier ();
@@ -85,12 +93,16 @@ WriteBackInvalidateDataCache ( VOID *
EFIAPI
WriteBackInvalidateDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
+ IN VOID *Address,
+ IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA,
- ArmDataCacheLineLength ());
+ CacheRangeOperation (
+ Address,
+ Length,
+ ArmCleanInvalidateDataCacheEntryByMVA,
+ ArmDataCacheLineLength ()
+ );
return Address;
}
@@ -106,23 +118,31 @@ WriteBackDataCache ( VOID *
EFIAPI
WriteBackDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
+ IN VOID *Address,
+ IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA,
- ArmDataCacheLineLength ());
+ CacheRangeOperation (
+ Address,
+ Length,
+ ArmCleanDataCacheEntryByMVA,
+ ArmDataCacheLineLength ()
+ );
return Address;
}
VOID *
EFIAPI
InvalidateDataCacheRange (
- IN VOID *Address,
- IN UINTN Length
+ IN VOID *Address,
+ IN UINTN Length
)
{
- CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA,
- ArmDataCacheLineLength ());
+ CacheRangeOperation (
+ Address,
+ Length,
+ ArmInvalidateDataCacheEntryByMVA,
+ ArmDataCacheLineLength ()
+ );
return Address;
}
diff --git a/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c b/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c index 353f41bfba..ac334f0ebf 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/Aarch64Disassembler.c @@ -26,12 +26,12 @@ **/
VOID
DisassembleInstruction (
- IN UINT8 **OpCodePtr,
- IN BOOLEAN Thumb,
- IN BOOLEAN Extended,
- IN OUT UINT32 *ItBlock,
- OUT CHAR8 *Buf,
- OUT UINTN Size
+ IN UINT8 **OpCodePtr,
+ IN BOOLEAN Thumb,
+ IN BOOLEAN Extended,
+ IN OUT UINT32 *ItBlock,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size
)
{
// Not yet supported for AArch64.
diff --git a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c index 03a9f1fbe2..0e09062957 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/ArmDisassembler.c @@ -13,7 +13,7 @@ #include <Library/PrintLib.h>
#include <Library/ArmDisassemblerLib.h>
-CHAR8 *gCondition[] = {
+CHAR8 *gCondition[] = {
"EQ",
"NE",
"CS",
@@ -34,7 +34,7 @@ CHAR8 *gCondition[] = { #define COND(_a) gCondition[((_a) >> 28)]
-CHAR8 *gReg[] = {
+CHAR8 *gReg[] = {
"r0",
"r1",
"r2",
@@ -53,37 +53,36 @@ CHAR8 *gReg[] = { "pc"
};
-CHAR8 *gLdmAdr[] = {
+CHAR8 *gLdmAdr[] = {
"DA",
"IA",
"DB",
"IB"
};
-CHAR8 *gLdmStack[] = {
+CHAR8 *gLdmStack[] = {
"FA",
"FD",
"EA",
"ED"
};
-#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
+#define LDM_EXT(_reg, _off) ((_reg == 13) ? gLdmStack[(_off)] : gLdmAdr[(_off)])
+#define SIGN(_U) ((_U) ? "" : "-")
+#define WRITE(_Write) ((_Write) ? "!" : "")
+#define BYTE(_B) ((_B) ? "B":"")
+#define USER(_B) ((_B) ? "^" : "")
-#define SIGN(_U) ((_U) ? "" : "-")
-#define WRITE(_Write) ((_Write) ? "!" : "")
-#define BYTE(_B) ((_B) ? "B":"")
-#define USER(_B) ((_B) ? "^" : "")
-
-CHAR8 mMregListStr[4*15 + 1];
+CHAR8 mMregListStr[4*15 + 1];
CHAR8 *
MRegList (
UINT32 OpCode
)
{
- UINTN Index, Start, End;
- BOOLEAN First;
+ UINTN Index, Start, End;
+ BOOLEAN First;
mMregListStr[0] = '\0';
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "{");
@@ -110,9 +109,11 @@ MRegList ( }
}
}
+
if (First) {
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "ERROR");
}
+
AsciiStrCatS (mMregListStr, sizeof mMregListStr, "}");
// BugBug: Make caller pass in buffer it is cleaner
@@ -129,14 +130,13 @@ FieldMask ( UINT32
RotateRight (
- IN UINT32 Op,
- IN UINT32 Shift
+ IN UINT32 Op,
+ IN UINT32 Shift
)
{
return (Op >> Shift) | (Op << (32 - Shift));
}
-
/**
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
@@ -152,39 +152,38 @@ RotateRight ( **/
VOID
DisassembleArmInstruction (
- IN UINT32 **OpCodePtr,
- OUT CHAR8 *Buf,
- OUT UINTN Size,
- IN BOOLEAN Extended
+ IN UINT32 **OpCodePtr,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size,
+ IN BOOLEAN Extended
)
{
- UINT32 OpCode;
- CHAR8 *Type;
- CHAR8 *Root;
- BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
- UINT32 Rn, Rd, Rm;
- UINT32 IMod, Offset8, Offset12;
- UINT32 Index;
- UINT32 ShiftImm, Shift;
+ UINT32 OpCode;
+ CHAR8 *Type;
+ CHAR8 *Root;
+ BOOLEAN Imm, Pre, Up, WriteBack, Write, Load, Sign, Half;
+ UINT32 Rn, Rd, Rm;
+ UINT32 IMod, Offset8, Offset12;
+ UINT32 Index;
+ UINT32 ShiftImm, Shift;
OpCode = **OpCodePtr;
- Imm = (OpCode & BIT25) == BIT25; // I
- Pre = (OpCode & BIT24) == BIT24; // P
- Up = (OpCode & BIT23) == BIT23; // U
+ Imm = (OpCode & BIT25) == BIT25; // I
+ Pre = (OpCode & BIT24) == BIT24; // P
+ Up = (OpCode & BIT23) == BIT23; // U
WriteBack = (OpCode & BIT22) == BIT22; // B, also called S
- Write = (OpCode & BIT21) == BIT21; // W
- Load = (OpCode & BIT20) == BIT20; // L
- Sign = (OpCode & BIT6) == BIT6; // S
- Half = (OpCode & BIT5) == BIT5; // H
- Rn = (OpCode >> 16) & 0xf;
- Rd = (OpCode >> 12) & 0xf;
- Rm = (OpCode & 0xf);
-
+ Write = (OpCode & BIT21) == BIT21; // W
+ Load = (OpCode & BIT20) == BIT20; // L
+ Sign = (OpCode & BIT6) == BIT6; // S
+ Half = (OpCode & BIT5) == BIT5; // H
+ Rn = (OpCode >> 16) & 0xf;
+ Rd = (OpCode >> 12) & 0xf;
+ Rm = (OpCode & 0xf);
if (Extended) {
Index = AsciiSPrint (Buf, Size, "0x%08x ", OpCode);
- Buf += Index;
+ Buf += Index;
Size -= Index;
}
@@ -194,9 +193,10 @@ DisassembleArmInstruction ( // A4.1.27 LDREX{<cond>} <Rd>, [<Rn>]
AsciiSPrint (Buf, Size, "LDREX%a %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn]);
} else {
- // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
+ // A4.1.103 STREX{<cond>} <Rd>, <Rm>, [<Rn>]
AsciiSPrint (Buf, Size, "STREX%a %a, %a, [%a]", COND (OpCode), gReg[Rd], gReg[Rn], gReg[Rn]);
}
+
return;
}
@@ -206,23 +206,25 @@ DisassembleArmInstruction ( // A4.1.20 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.21 LDM{<cond>}<addressing_mode> <Rn>, <registers_without_pc>^
// A4.1.22 LDM{<cond>}<addressing_mode> <Rn>{!}, <registers_and_pc>^
- AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
+ AsciiSPrint (Buf, Size, "LDM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
} else {
// A4.1.97 STM{<cond>}<addressing_mode> <Rn>{!}, <registers>
// A4.1.98 STM{<cond>}<addressing_mode> <Rn>, <registers>^
- AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn ,(OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
+ AsciiSPrint (Buf, Size, "STM%a%a, %a%a, %a", COND (OpCode), LDM_EXT (Rn, (OpCode >> 23) & 3), gReg[Rn], WRITE (Write), MRegList (OpCode), USER (WriteBack));
}
+
return;
}
// LDR/STR Address Mode 2
- if ( ((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000 ) == 0xf550f000) ) {
+ if (((OpCode & 0x0c000000) == 0x04000000) || ((OpCode & 0xfd70f000) == 0xf550f000)) {
Offset12 = OpCode & 0xfff;
- if ((OpCode & 0xfd70f000 ) == 0xf550f000) {
+ if ((OpCode & 0xfd70f000) == 0xf550f000) {
Index = AsciiSPrint (Buf, Size, "PLD");
} else {
- Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T":"", gReg[Rd]);
+ Index = AsciiSPrint (Buf, Size, "%a%a%a%a %a, ", Load ? "LDR" : "STR", COND (OpCode), BYTE (WriteBack), (!(Pre) && Write) ? "T" : "", gReg[Rd]);
}
+
if (Pre) {
if (!Imm) {
// A5.2.2 [<Rn>, #+/-<offset_12>]
@@ -236,7 +238,7 @@ DisassembleArmInstruction ( // A5.2.4 [<Rn>, +/-<Rm>, LSL #<shift_imm>]
// A5.2.7 [<Rn>, +/-<Rm>, LSL #<shift_imm>]!
ShiftImm = (OpCode >> 7) & 0x1f;
- Shift = (OpCode >> 5) & 0x3;
+ Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) {
Type = "LSL";
} else if (Shift == 0x1) {
@@ -255,7 +257,8 @@ DisassembleArmInstruction ( AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%a, %a, #%d]%a", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm, WRITE (Write));
}
- } else { // !Pre
+ } else {
+ // !Pre
if (!Imm) {
// A5.2.8 [<Rn>], #+/-<offset_12>
AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x", gReg[Rn], SIGN (Up), Offset12);
@@ -265,7 +268,7 @@ DisassembleArmInstruction ( } else {
// A5.2.10 [<Rn>], +/-<Rm>, LSL #<shift_imm>
ShiftImm = (OpCode >> 7) & 0x1f;
- Shift = (OpCode >> 5) & 0x3;
+ Shift = (OpCode >> 5) & 0x3;
if (Shift == 0x0) {
Type = "LSL";
@@ -287,6 +290,7 @@ DisassembleArmInstruction ( AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a, %a, #%d", gReg[Rn], SIGN (Up), gReg[Rm], Type, ShiftImm);
}
}
+
return;
}
@@ -313,30 +317,31 @@ DisassembleArmInstruction ( Index = AsciiSPrint (Buf, Size, Root, COND (OpCode), gReg[Rd]);
- Sign = (OpCode & BIT6) == BIT6;
- Half = (OpCode & BIT5) == BIT5;
+ Sign = (OpCode & BIT6) == BIT6;
+ Half = (OpCode & BIT5) == BIT5;
Offset8 = ((OpCode >> 4) | (OpCode * 0xf)) & 0xff;
if (Pre & !Write) {
// Immediate offset/index
if (WriteBack) {
// A5.3.2 [<Rn>, #+/-<offset_8>]
// A5.3.4 [<Rn>, #+/-<offset_8>]!
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%d]%a", gReg[Rn], SIGN (Up), Offset8, WRITE (Write));
} else {
// A5.3.3 [<Rn>, +/-<Rm>]
// A5.3.5 [<Rn>, +/-<Rm>]!
- AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a%]a", gReg[Rn], SIGN (Up), gReg[Rm], WRITE (Write));
}
} else {
// Register offset/index
if (WriteBack) {
// A5.3.6 [<Rn>], #+/-<offset_8>
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%d", gReg[Rn], SIGN (Up), Offset8);
} else {
// A5.3.7 [<Rn>], +/-<Rm>
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a%a", gReg[Rn], SIGN (Up), gReg[Rm]);
}
}
+
return;
}
@@ -370,16 +375,21 @@ DisassembleArmInstruction ( if (((OpCode >> 6) & 0x7) == 0) {
AsciiSPrint (Buf, Size, "CPS #0x%x", (OpCode & 0x2f));
} else {
- IMod = (OpCode >> 18) & 0x3;
- Index = AsciiSPrint (Buf, Size, "CPS%a %a%a%a",
- (IMod == 3) ? "ID":"IE",
- ((OpCode & BIT8) != 0) ? "A":"",
- ((OpCode & BIT7) != 0) ? "I":"",
- ((OpCode & BIT6) != 0) ? "F":"");
+ IMod = (OpCode >> 18) & 0x3;
+ Index = AsciiSPrint (
+ Buf,
+ Size,
+ "CPS%a %a%a%a",
+ (IMod == 3) ? "ID" : "IE",
+ ((OpCode & BIT8) != 0) ? "A" : "",
+ ((OpCode & BIT7) != 0) ? "I" : "",
+ ((OpCode & BIT6) != 0) ? "F" : ""
+ );
if ((OpCode & BIT17) != 0) {
AsciiSPrint (&Buf[Index], Size - Index, ", #0x%x", OpCode & 0x1f);
}
}
+
return;
}
@@ -395,16 +405,16 @@ DisassembleArmInstruction ( return;
}
-
if ((OpCode & 0x0db00000) == 0x01200000) {
// A4.1.38 MSR{<cond>} CPSR_<fields>, #<immediate> MSR{<cond>} CPSR_<fields>, <Rm>
if (Imm) {
// MSR{<cond>} CPSR_<fields>, #<immediate>
- AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
+ AsciiSPrint (Buf, Size, "MRS%a %a_%a, #0x%x", COND (OpCode), WriteBack ? "SPSR" : "CPSR", FieldMask ((OpCode >> 16) & 0xf), RotateRight (OpCode & 0xf, ((OpCode >> 8) & 0xf) *2));
} else {
// MSR{<cond>} CPSR_<fields>, <Rm>
AsciiSPrint (Buf, Size, "MRS%a %a_%a, %a", COND (OpCode), WriteBack ? "SPSR" : "CPSR", gReg[Rd]);
}
+
return;
}
@@ -417,35 +427,34 @@ DisassembleArmInstruction ( if ((OpCode & 0x0e000000) == 0x0c000000) {
// A4.1.19 LDC and A4.1.96 SDC
if ((OpCode & 0xf0000000) == 0xf0000000) {
- Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC":"SDC", (OpCode >> 8) & 0xf, Rd);
+ Index = AsciiSPrint (Buf, Size, "%a2 0x%x, CR%d, ", Load ? "LDC" : "SDC", (OpCode >> 8) & 0xf, Rd);
} else {
- Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC":"SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
+ Index = AsciiSPrint (Buf, Size, "%a%a 0x%x, CR%d, ", Load ? "LDC" : "SDC", COND (OpCode), (OpCode >> 8) & 0xf, Rd);
}
if (!Pre) {
if (!Write) {
// A5.5.5.5 [<Rn>], <option>
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], {0x%x}", gReg[Rn], OpCode & 0xff);
} else {
// A.5.5.4 [<Rn>], #+/-<offset_8>*4
- AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
+ AsciiSPrint (&Buf[Index], Size - Index, "[%a], #%a0x%x*4", gReg[Rn], SIGN (Up), OpCode & 0xff);
}
} else {
// A5.5.5.2 [<Rn>, #+/-<offset_8>*4 ]!
AsciiSPrint (&Buf[Index], Size - Index, "[%a, #%a0x%x*4]%a", gReg[Rn], SIGN (Up), OpCode & 0xff, WRITE (Write));
}
-
}
if ((OpCode & 0x0f000010) == 0x0e000010) {
// A4.1.32 MRC2, MCR2
- AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC":"MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
+ AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, CR%d, CR%d, 0x%x", Load ? "MRC" : "MCR", COND (OpCode), (OpCode >> 8) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], Rn, Rm, (OpCode >> 5) &0x7);
return;
}
if ((OpCode & 0x0ff00000) == 0x0c400000) {
// A4.1.33 MRRC2, MCRR2
- AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC":"MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
+ AsciiSPrint (Buf, Size, "%a%a 0x%x, 0x%x, %a, %a, CR%d", Load ? "MRRC" : "MCRR", COND (OpCode), (OpCode >> 4) & 0xf, (OpCode >> 20) & 0xf, gReg[Rd], gReg[Rn], Rm);
return;
}
@@ -454,4 +463,3 @@ DisassembleArmInstruction ( *OpCodePtr += 1;
return;
}
-
diff --git a/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c b/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c index 3129ec6b92..6dae7a9121 100644 --- a/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c +++ b/ArmPkg/Library/ArmDisassemblerLib/ThumbDisassembler.c @@ -20,24 +20,24 @@ #include <Library/DebugLib.h>
#include <Library/PrintLib.h>
-extern CHAR8 *gCondition[];
+extern CHAR8 *gCondition[];
-extern CHAR8 *gReg[];
+extern CHAR8 *gReg[];
// Thumb address modes
-#define LOAD_STORE_FORMAT1 1
-#define LOAD_STORE_FORMAT1_H 101
-#define LOAD_STORE_FORMAT1_B 111
-#define LOAD_STORE_FORMAT2 2
-#define LOAD_STORE_FORMAT3 3
-#define LOAD_STORE_FORMAT4 4
-#define LOAD_STORE_MULTIPLE_FORMAT1 5
-#define PUSH_FORMAT 6
-#define POP_FORMAT 106
-#define IMMED_8 7
-#define CONDITIONAL_BRANCH 8
-#define UNCONDITIONAL_BRANCH 9
-#define UNCONDITIONAL_BRANCH_SHORT 109
+#define LOAD_STORE_FORMAT1 1
+#define LOAD_STORE_FORMAT1_H 101
+#define LOAD_STORE_FORMAT1_B 111
+#define LOAD_STORE_FORMAT2 2
+#define LOAD_STORE_FORMAT3 3
+#define LOAD_STORE_FORMAT4 4
+#define LOAD_STORE_MULTIPLE_FORMAT1 5
+#define PUSH_FORMAT 6
+#define POP_FORMAT 106
+#define IMMED_8 7
+#define CONDITIONAL_BRANCH 8
+#define UNCONDITIONAL_BRANCH 9
+#define UNCONDITIONAL_BRANCH_SHORT 109
#define BRANCH_EXCHANGE 10
#define DATA_FORMAT1 11
#define DATA_FORMAT2 12
@@ -45,7 +45,7 @@ extern CHAR8 *gReg[]; #define DATA_FORMAT4 14
#define DATA_FORMAT5 15
#define DATA_FORMAT6_SP 16
-#define DATA_FORMAT6_PC 116
+#define DATA_FORMAT6_PC 116
#define DATA_FORMAT7 17
#define DATA_FORMAT8 19
#define CPS_FORMAT 20
@@ -55,344 +55,338 @@ extern CHAR8 *gReg[]; #define IT_BLOCK 24
// Thumb2 address modes
-#define B_T3 200
-#define B_T4 201
-#define BL_T2 202
-#define POP_T2 203
-#define POP_T3 204
-#define STM_FORMAT 205
-#define LDM_REG_IMM12_SIGNED 206
-#define LDM_REG_IMM12_LSL 207
-#define LDM_REG_IMM8 208
-#define LDM_REG_IMM12 209
-#define LDM_REG_INDIRECT_LSL 210
-#define LDM_REG_IMM8_SIGNED 211
-#define LDRD_REG_IMM8 212
-#define LDREXB 213
-#define LDREXD 214
-#define SRS_FORMAT 215
-#define RFE_FORMAT 216
-#define LDRD_REG_IMM8_SIGNED 217
-#define ADD_IMM12 218
-#define ADD_IMM5 219
-#define ADR_THUMB2 220
-#define CMN_THUMB2 221
-#define ASR_IMM5 222
-#define ASR_3REG 223
-#define BFC_THUMB2 224
-#define CDP_THUMB2 225
-#define THUMB2_NO_ARGS 226
-#define THUMB2_2REGS 227
-#define ADD_IMM5_2REG 228
-#define CPD_THUMB2 229
-#define THUMB2_4REGS 230
-#define ADD_IMM12_1REG 231
-#define THUMB2_IMM16 232
-#define MRC_THUMB2 233
-#define MRRC_THUMB2 234
-#define THUMB2_MRS 235
-#define THUMB2_MSR 236
-
-
-
+#define B_T3 200
+#define B_T4 201
+#define BL_T2 202
+#define POP_T2 203
+#define POP_T3 204
+#define STM_FORMAT 205
+#define LDM_REG_IMM12_SIGNED 206
+#define LDM_REG_IMM12_LSL 207
+#define LDM_REG_IMM8 208
+#define LDM_REG_IMM12 209
+#define LDM_REG_INDIRECT_LSL 210
+#define LDM_REG_IMM8_SIGNED 211
+#define LDRD_REG_IMM8 212
+#define LDREXB 213
+#define LDREXD 214
+#define SRS_FORMAT 215
+#define RFE_FORMAT 216
+#define LDRD_REG_IMM8_SIGNED 217
+#define ADD_IMM12 218
+#define ADD_IMM5 219
+#define ADR_THUMB2 220
+#define CMN_THUMB2 221
+#define ASR_IMM5 222
+#define ASR_3REG 223
+#define BFC_THUMB2 224
+#define CDP_THUMB2 225
+#define THUMB2_NO_ARGS 226
+#define THUMB2_2REGS 227
+#define ADD_IMM5_2REG 228
+#define CPD_THUMB2 229
+#define THUMB2_4REGS 230
+#define ADD_IMM12_1REG 231
+#define THUMB2_IMM16 232
+#define MRC_THUMB2 233
+#define MRRC_THUMB2 234
+#define THUMB2_MRS 235
+#define THUMB2_MSR 236
typedef struct {
- CHAR8 *Start;
- UINT32 OpCode;
- UINT32 Mask;
- UINT32 AddressMode;
+ CHAR8 *Start;
+ UINT32 OpCode;
+ UINT32 Mask;
+ UINT32 AddressMode;
} THUMB_INSTRUCTIONS;
-THUMB_INSTRUCTIONS gOpThumb[] = {
-// Thumb 16-bit instructions
-// Op Mask Format
- { "ADC" , 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>
- { "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>
- { "ADD" , 0x1c00, 0xfe00, DATA_FORMAT2 },
- { "ADD" , 0x3000, 0xf800, DATA_FORMAT3 },
- { "ADD" , 0x1800, 0xfe00, DATA_FORMAT1 },
- { "ADD" , 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
- { "ADD" , 0xa000, 0xf100, DATA_FORMAT6_PC },
- { "ADD" , 0xa800, 0xf800, DATA_FORMAT6_SP },
- { "ADD" , 0xb000, 0xff80, DATA_FORMAT7 },
-
- { "AND" , 0x4000, 0xffc0, DATA_FORMAT5 },
-
- { "ASR" , 0x1000, 0xf800, DATA_FORMAT4 },
- { "ASR" , 0x4100, 0xffc0, DATA_FORMAT5 },
-
- { "B" , 0xd000, 0xf000, CONDITIONAL_BRANCH },
- { "B" , 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT },
- { "BLX" , 0x4780, 0xff80, BRANCH_EXCHANGE },
- { "BX" , 0x4700, 0xff87, BRANCH_EXCHANGE },
-
- { "BIC" , 0x4380, 0xffc0, DATA_FORMAT5 },
- { "BKPT", 0xdf00, 0xff00, IMMED_8 },
- { "CBZ", 0xb100, 0xfd00, DATA_CBZ },
- { "CBNZ", 0xb900, 0xfd00, DATA_CBZ },
- { "CMN" , 0x42c0, 0xffc0, DATA_FORMAT5 },
-
- { "CMP" , 0x2800, 0xf800, DATA_FORMAT3 },
- { "CMP" , 0x4280, 0xffc0, DATA_FORMAT5 },
- { "CMP" , 0x4500, 0xff00, DATA_FORMAT8 },
-
- { "CPS" , 0xb660, 0xffe8, CPS_FORMAT },
- { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
- { "EOR" , 0x4040, 0xffc0, DATA_FORMAT5 },
-
- { "LDMIA" , 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
- { "LDR" , 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
- { "LDR" , 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
- { "LDR" , 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
- { "LDR" , 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]
- { "LDRB" , 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },
- { "LDRB" , 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
- { "LDRH" , 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },
- { "LDRH" , 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
- { "LDRSB" , 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
- { "LDRSH" , 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
-
- { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
- { "LSL" , 0x0000, 0xf800, DATA_FORMAT4 },
- { "LSL" , 0x4080, 0xffc0, DATA_FORMAT5 },
- { "LSR" , 0x0001, 0xf800, DATA_FORMAT4 },
- { "LSR" , 0x40c0, 0xffc0, DATA_FORMAT5 },
- { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>
-
- { "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },
- { "MOV" , 0x1c00, 0xffc0, DATA_FORMAT3 },
- { "MOV" , 0x4600, 0xff00, DATA_FORMAT8 },
-
- { "MUL" , 0x4340, 0xffc0, DATA_FORMAT5 },
- { "MVN" , 0x41c0, 0xffc0, DATA_FORMAT5 },
- { "NEG" , 0x4240, 0xffc0, DATA_FORMAT5 },
- { "ORR" , 0x4300, 0xffc0, DATA_FORMAT5 },
- { "POP" , 0xbc00, 0xfe00, POP_FORMAT },
- { "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },
-
- { "REV" , 0xba00, 0xffc0, DATA_FORMAT5 },
- { "REV16" , 0xba40, 0xffc0, DATA_FORMAT5 },
- { "REVSH" , 0xbac0, 0xffc0, DATA_FORMAT5 },
-
- { "ROR" , 0x41c0, 0xffc0, DATA_FORMAT5 },
- { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
- { "SETEND" , 0xb650, 0xfff0, ENDIAN_FORMAT },
-
- { "STMIA" , 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
- { "STR" , 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
- { "STR" , 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
- { "STR" , 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]
- { "STRB" , 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
- { "STRB" , 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
- { "STRH" , 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]
- { "STRH" , 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]
-
- { "SUB" , 0x1e00, 0xfe00, DATA_FORMAT2 },
- { "SUB" , 0x3800, 0xf800, DATA_FORMAT3 },
- { "SUB" , 0x1a00, 0xfe00, DATA_FORMAT1 },
- { "SUB" , 0xb080, 0xff80, DATA_FORMAT7 },
-
- { "SBC" , 0x4180, 0xffc0, DATA_FORMAT5 },
-
- { "SWI" , 0xdf00, 0xff00, IMMED_8 },
- { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
- { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
- { "TST" , 0x4200, 0xffc0, DATA_FORMAT5 },
- { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
- { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 },
-
- { "IT", 0xbf00, 0xff00, IT_BLOCK }
-
+THUMB_INSTRUCTIONS gOpThumb[] = {
+ // Thumb 16-bit instructions
+ // Op Mask Format
+ { "ADC", 0x4140, 0xffc0, DATA_FORMAT5 }, // ADC <Rndn>, <Rm>
+ { "ADR", 0xa000, 0xf800, ADR_FORMAT }, // ADR <Rd>, <label>
+ { "ADD", 0x1c00, 0xfe00, DATA_FORMAT2 },
+ { "ADD", 0x3000, 0xf800, DATA_FORMAT3 },
+ { "ADD", 0x1800, 0xfe00, DATA_FORMAT1 },
+ { "ADD", 0x4400, 0xff00, DATA_FORMAT8 }, // A8.6.9
+ { "ADD", 0xa000, 0xf100, DATA_FORMAT6_PC },
+ { "ADD", 0xa800, 0xf800, DATA_FORMAT6_SP },
+ { "ADD", 0xb000, 0xff80, DATA_FORMAT7 },
+
+ { "AND", 0x4000, 0xffc0, DATA_FORMAT5 },
+
+ { "ASR", 0x1000, 0xf800, DATA_FORMAT4 },
+ { "ASR", 0x4100, 0xffc0, DATA_FORMAT5 },
+
+ { "B", 0xd000, 0xf000, CONDITIONAL_BRANCH },
+ { "B", 0xe000, 0xf800, UNCONDITIONAL_BRANCH_SHORT },
+ { "BLX", 0x4780, 0xff80, BRANCH_EXCHANGE },
+ { "BX", 0x4700, 0xff87, BRANCH_EXCHANGE },
+
+ { "BIC", 0x4380, 0xffc0, DATA_FORMAT5 },
+ { "BKPT", 0xdf00, 0xff00, IMMED_8 },
+ { "CBZ", 0xb100, 0xfd00, DATA_CBZ },
+ { "CBNZ", 0xb900, 0xfd00, DATA_CBZ },
+ { "CMN", 0x42c0, 0xffc0, DATA_FORMAT5 },
+
+ { "CMP", 0x2800, 0xf800, DATA_FORMAT3 },
+ { "CMP", 0x4280, 0xffc0, DATA_FORMAT5 },
+ { "CMP", 0x4500, 0xff00, DATA_FORMAT8 },
+
+ { "CPS", 0xb660, 0xffe8, CPS_FORMAT },
+ { "MOV", 0x4600, 0xff00, DATA_FORMAT8 },
+ { "EOR", 0x4040, 0xffc0, DATA_FORMAT5 },
+
+ { "LDMIA", 0xc800, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
+ { "LDR", 0x6800, 0xf800, LOAD_STORE_FORMAT1 }, // LDR <Rt>, [<Rn> {,#<imm>}]
+ { "LDR", 0x5800, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
+ { "LDR", 0x4800, 0xf800, LOAD_STORE_FORMAT3 },
+ { "LDR", 0x9800, 0xf800, LOAD_STORE_FORMAT4 }, // LDR <Rt>, [SP, #<imm>]
+ { "LDRB", 0x7800, 0xf800, LOAD_STORE_FORMAT1_B },
+ { "LDRB", 0x5c00, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
+ { "LDRH", 0x8800, 0xf800, LOAD_STORE_FORMAT1_H },
+ { "LDRH", 0x7a00, 0xfe00, LOAD_STORE_FORMAT2 },
+ { "LDRSB", 0x5600, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
+ { "LDRSH", 0x5e00, 0xfe00, LOAD_STORE_FORMAT2 },
+
+ { "MOVS", 0x0000, 0xffc0, DATA_FORMAT5 }, // LSL with imm5 == 0 is a MOVS, so this must go before LSL
+ { "LSL", 0x0000, 0xf800, DATA_FORMAT4 },
+ { "LSL", 0x4080, 0xffc0, DATA_FORMAT5 },
+ { "LSR", 0x0001, 0xf800, DATA_FORMAT4 },
+ { "LSR", 0x40c0, 0xffc0, DATA_FORMAT5 },
+ { "LSRS", 0x0800, 0xf800, DATA_FORMAT4 }, // LSRS <Rd>, <Rm>, #<imm5>
+
+ { "MOVS", 0x2000, 0xf800, DATA_FORMAT3 },
+ { "MOV", 0x1c00, 0xffc0, DATA_FORMAT3 },
+ { "MOV", 0x4600, 0xff00, DATA_FORMAT8 },
+
+ { "MUL", 0x4340, 0xffc0, DATA_FORMAT5 },
+ { "MVN", 0x41c0, 0xffc0, DATA_FORMAT5 },
+ { "NEG", 0x4240, 0xffc0, DATA_FORMAT5 },
+ { "ORR", 0x4300, 0xffc0, DATA_FORMAT5 },
+ { "POP", 0xbc00, 0xfe00, POP_FORMAT },
+ { "PUSH", 0xb400, 0xfe00, PUSH_FORMAT },
+
+ { "REV", 0xba00, 0xffc0, DATA_FORMAT5 },
+ { "REV16", 0xba40, 0xffc0, DATA_FORMAT5 },
+ { "REVSH", 0xbac0, 0xffc0, DATA_FORMAT5 },
+
+ { "ROR", 0x41c0, 0xffc0, DATA_FORMAT5 },
+ { "SBC", 0x4180, 0xffc0, DATA_FORMAT5 },
+ { "SETEND", 0xb650, 0xfff0, ENDIAN_FORMAT },
+
+ { "STMIA", 0xc000, 0xf800, LOAD_STORE_MULTIPLE_FORMAT1 },
+ { "STR", 0x6000, 0xf800, LOAD_STORE_FORMAT1 }, // STR <Rt>, [<Rn> {,#<imm>}]
+ { "STR", 0x5000, 0xfe00, LOAD_STORE_FORMAT2 }, // STR <Rt>, [<Rn>, <Rm>]
+ { "STR", 0x9000, 0xf800, LOAD_STORE_FORMAT4 }, // STR <Rt>, [SP, #<imm>]
+ { "STRB", 0x7000, 0xf800, LOAD_STORE_FORMAT1_B }, // STRB <Rt>, [<Rn>, #<imm5>]
+ { "STRB", 0x5400, 0xfe00, LOAD_STORE_FORMAT2 }, // STRB <Rt>, [<Rn>, <Rm>]
+ { "STRH", 0x8000, 0xf800, LOAD_STORE_FORMAT1_H }, // STRH <Rt>, [<Rn>{,#<imm>}]
+ { "STRH", 0x5200, 0xfe00, LOAD_STORE_FORMAT2 }, // STRH <Rt>, [<Rn>, <Rm>]
+
+ { "SUB", 0x1e00, 0xfe00, DATA_FORMAT2 },
+ { "SUB", 0x3800, 0xf800, DATA_FORMAT3 },
+ { "SUB", 0x1a00, 0xfe00, DATA_FORMAT1 },
+ { "SUB", 0xb080, 0xff80, DATA_FORMAT7 },
+
+ { "SBC", 0x4180, 0xffc0, DATA_FORMAT5 },
+
+ { "SWI", 0xdf00, 0xff00, IMMED_8 },
+ { "SXTB", 0xb240, 0xffc0, DATA_FORMAT5 },
+ { "SXTH", 0xb200, 0xffc0, DATA_FORMAT5 },
+ { "TST", 0x4200, 0xffc0, DATA_FORMAT5 },
+ { "UXTB", 0xb2c0, 0xffc0, DATA_FORMAT5 },
+ { "UXTH", 0xb280, 0xffc0, DATA_FORMAT5 },
+
+ { "IT", 0xbf00, 0xff00, IT_BLOCK }
};
-THUMB_INSTRUCTIONS gOpThumb2[] = {
-//Instruct OpCode OpCode Mask Addressig Mode
-
- { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
- { "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD
- { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
- { "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
- { "TEQ", 0xf0900f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
- { "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
- { "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
- { "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}
-
- { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>
- { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>
- { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>
-
- { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
- { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>
- { "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "ADDW", 0xf2000000, 0xfbe08000, ADD_IMM12 }, // ADDW{S} <Rd>, <Rn>, #<const>
- { "AND", 0xf0000000, 0xfbe08000, ADD_IMM12 }, // AND{S} <Rd>, <Rn>, #<const>
- { "AND", 0xea000000, 0xffe08000, ADD_IMM5 }, // AND{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "BIC", 0xf0200000, 0xfbe08000, ADD_IMM12 }, // BIC{S} <Rd>, <Rn>, #<const>
- { "BIC", 0xea200000, 0xffe08000, ADD_IMM5 }, // BIC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "EOR", 0xf0800000, 0xfbe08000, ADD_IMM12 }, // EOR{S} <Rd>, <Rn>, #<const>
- { "EOR", 0xea800000, 0xffe08000, ADD_IMM5 }, // EOR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "ORN", 0xf0600000, 0xfbe08000, ADD_IMM12 }, // ORN{S} <Rd>, <Rn>, #<const>
- { "ORN", 0xea600000, 0xffe08000, ADD_IMM5 }, // ORN{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "ORR", 0xf0400000, 0xfbe08000, ADD_IMM12 }, // ORR{S} <Rd>, <Rn>, #<const>
- { "ORR", 0xea400000, 0xffe08000, ADD_IMM5 }, // ORR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "RSB", 0xf1c00000, 0xfbe08000, ADD_IMM12 }, // RSB{S} <Rd>, <Rn>, #<const>
- { "RSB", 0xebc00000, 0xffe08000, ADD_IMM5 }, // RSB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "SBC", 0xf1600000, 0xfbe08000, ADD_IMM12 }, // SBC{S} <Rd>, <Rn>, #<const>
- { "SBC", 0xeb600000, 0xffe08000, ADD_IMM5 }, // SBC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
- { "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>
- { "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
-
- { "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2
- { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>
- { "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2
- { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>
- { "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2
- { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>
-
- { "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>
- { "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>
- { "SBFX", 0xf3400000, 0xfff08010, BFC_THUMB2 }, // SBFX <Rn>, <Rd>, #<lsb>, #<width>
- { "UBFX", 0xf3c00000, 0xfff08010, BFC_THUMB2 }, // UBFX <Rn>, <Rd>, #<lsb>, #<width>
-
- { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
-
- { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
- { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
- { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
- { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
-
- { "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS <Rd>, CPSR
- { "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, <Rn>
-
- { "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX
-
- { "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>
- { "MOV", 0xec4f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOV <Rd>,<Rm>
- { "MOVS", 0xec5f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOVS <Rd>,<Rm>
- { "RBIT", 0xfb90f0a0, 0xfff0f0f0, THUMB2_2REGS }, // RBIT <Rd>,<Rm>
- { "REV", 0xfb90f080, 0xfff0f0f0, THUMB2_2REGS }, // REV <Rd>,<Rm>
- { "REV16", 0xfa90f090, 0xfff0f0f0, THUMB2_2REGS }, // REV16 <Rd>,<Rm>
- { "REVSH", 0xfa90f0b0, 0xfff0f0f0, THUMB2_2REGS }, // REVSH <Rd>,<Rm>
- { "RRX", 0xea4f0030, 0xfffff0f0, THUMB2_2REGS }, // RRX <Rd>,<Rm>
- { "RRXS", 0xea5f0030, 0xfffff0f0, THUMB2_2REGS }, // RRXS <Rd>,<Rm>
-
- { "MLA", 0xfb000000, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
- { "MLS", 0xfb000010, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
-
-
- { "SMLABB", 0xfb100000, 0xfff000f0, THUMB2_4REGS }, // SMLABB <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX <Rd>, <Rn>, <Rm>, <Ra>
- { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA <Rd>, <Rn>, <Rm>, <Ra>
- { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR <Rd>, <Rn>, <Rm>, <Ra>
- { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS <Rd>, <Rn>, <Rm>, <Ra>
- { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR <Rd>, <Rn>, <Rm>, <Ra>
- { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD <Rd>, <Rn>, <Rm>, <Ra>
- { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX <Rd>, <Rn>, <Rm>, <Ra>
-
-
- { "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>
- { "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>
- { "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>
- { "BLX", 0xf000c000, 0xf800d000, BL_T2 }, // BLX<c> <label>
-
- { "POP", 0xe8bd0000, 0xffff2000, POP_T2 }, // POP <registers>
- { "POP", 0xf85d0b04, 0xffff0fff, POP_T3 }, // POP <register>
- { "PUSH", 0xe8ad0000, 0xffffa000, POP_T2 }, // PUSH <registers>
- { "PUSH", 0xf84d0d04, 0xffff0fff, POP_T3 }, // PUSH <register>
- { "STM" , 0xe8800000, 0xffd0a000, STM_FORMAT }, // STM <Rn>{!},<registers>
- { "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>
- { "LDM" , 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>
- { "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>
-
- { "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}
- { "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}
- { "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}
- { "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}
- { "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}
-
- { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>
- { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>
- { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>
- { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
- { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
-
- { "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "LDRSH", 0xf9300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
-
- { "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}
- { "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}
- { "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}
- { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?
- { "LDRSBT",0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?
- { "LDRSH" ,0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}
- { "LDRSHT",0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}
- { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}
-
- { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
- { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>
-
- { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]
- { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]
- { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]
-
- { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]
-
- { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}
- { "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}
- { "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}
-
- { "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- { "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
-
- { "STR", 0xf8400800, 0xfff00800, LDM_REG_IMM8 }, // STR <rt>, [<rn>, {, #<imm8>]}
- { "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}
- { "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}
- { "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}
- { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}
-
- { "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
-
- { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]
- { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]
- { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]
-
- { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]
-
- { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
- { "SRS" , 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
- { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}
- { "RFE" , 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}
+THUMB_INSTRUCTIONS gOpThumb2[] = {
+ // Instruct OpCode OpCode Mask Addressig Mode
+
+ { "ADR", 0xf2af0000, 0xfbff8000, ADR_THUMB2 }, // ADDR <Rd>, <label> ;Needs to go before ADDW
+ { "CMN", 0xf1100f00, 0xfff08f00, CMN_THUMB2 }, // CMN <Rn>, #<const> ;Needs to go before ADD
+ { "CMN", 0xeb100f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
+ { "CMP", 0xf1a00f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
+ { "TEQ", 0xf0900f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
+ { "TEQ", 0xea900f00, 0xfff08f00, ADD_IMM5_2REG }, // CMN <Rn>, <Rm> {,<shift> #<const>}
+ { "TST", 0xf0100f00, 0xfff08f00, CMN_THUMB2 }, // CMP <Rn>, #<const>
+ { "TST", 0xea100f00, 0xfff08f00, ADD_IMM5_2REG }, // TST <Rn>, <Rm> {,<shift> #<const>}
+
+ { "MOV", 0xf04f0000, 0xfbef8000, ADD_IMM12_1REG }, // MOV <Rd>, #<const>
+ { "MOVW", 0xf2400000, 0xfbe08000, THUMB2_IMM16 }, // MOVW <Rd>, #<const>
+ { "MOVT", 0xf2c00000, 0xfbe08000, THUMB2_IMM16 }, // MOVT <Rd>, #<const>
+
+ { "ADC", 0xf1400000, 0xfbe08000, ADD_IMM12 }, // ADC{S} <Rd>, <Rn>, #<const>
+ { "ADC", 0xeb400000, 0xffe08000, ADD_IMM5 }, // ADC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "ADD", 0xf1000000, 0xfbe08000, ADD_IMM12 }, // ADD{S} <Rd>, <Rn>, #<const>
+ { "ADD", 0xeb000000, 0xffe08000, ADD_IMM5 }, // ADD{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "ADDW", 0xf2000000, 0xfbe08000, ADD_IMM12 }, // ADDW{S} <Rd>, <Rn>, #<const>
+ { "AND", 0xf0000000, 0xfbe08000, ADD_IMM12 }, // AND{S} <Rd>, <Rn>, #<const>
+ { "AND", 0xea000000, 0xffe08000, ADD_IMM5 }, // AND{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "BIC", 0xf0200000, 0xfbe08000, ADD_IMM12 }, // BIC{S} <Rd>, <Rn>, #<const>
+ { "BIC", 0xea200000, 0xffe08000, ADD_IMM5 }, // BIC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "EOR", 0xf0800000, 0xfbe08000, ADD_IMM12 }, // EOR{S} <Rd>, <Rn>, #<const>
+ { "EOR", 0xea800000, 0xffe08000, ADD_IMM5 }, // EOR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "ORN", 0xf0600000, 0xfbe08000, ADD_IMM12 }, // ORN{S} <Rd>, <Rn>, #<const>
+ { "ORN", 0xea600000, 0xffe08000, ADD_IMM5 }, // ORN{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "ORR", 0xf0400000, 0xfbe08000, ADD_IMM12 }, // ORR{S} <Rd>, <Rn>, #<const>
+ { "ORR", 0xea400000, 0xffe08000, ADD_IMM5 }, // ORR{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "RSB", 0xf1c00000, 0xfbe08000, ADD_IMM12 }, // RSB{S} <Rd>, <Rn>, #<const>
+ { "RSB", 0xebc00000, 0xffe08000, ADD_IMM5 }, // RSB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "SBC", 0xf1600000, 0xfbe08000, ADD_IMM12 }, // SBC{S} <Rd>, <Rn>, #<const>
+ { "SBC", 0xeb600000, 0xffe08000, ADD_IMM5 }, // SBC{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+ { "SUB", 0xf1a00000, 0xfbe08000, ADD_IMM12 }, // SUB{S} <Rd>, <Rn>, #<const>
+ { "SUB", 0xeba00000, 0xffe08000, ADD_IMM5 }, // SUB{S} <Rd>, <Rn>, <Rm> {,<shift> #<const>}
+
+ { "ASR", 0xea4f0020, 0xffef8030, ASR_IMM5 }, // ARS <Rd>, <Rm> #<const>} imm3:imm2
+ { "ASR", 0xfa40f000, 0xffe0f0f0, ASR_3REG }, // ARS <Rd>, <Rn>, <Rm>
+ { "LSR", 0xea4f0010, 0xffef8030, ASR_IMM5 }, // LSR <Rd>, <Rm> #<const>} imm3:imm2
+ { "LSR", 0xfa20f000, 0xffe0f0f0, ASR_3REG }, // LSR <Rd>, <Rn>, <Rm>
+ { "ROR", 0xea4f0030, 0xffef8030, ASR_IMM5 }, // ROR <Rd>, <Rm> #<const>} imm3:imm2
+ { "ROR", 0xfa60f000, 0xffe0f0f0, ASR_3REG }, // ROR <Rd>, <Rn>, <Rm>
+
+ { "BFC", 0xf36f0000, 0xffff8010, BFC_THUMB2 }, // BFC <Rd>, #<lsb>, #<width>
+ { "BIC", 0xf3600000, 0xfff08010, BFC_THUMB2 }, // BIC <Rn>, <Rd>, #<lsb>, #<width>
+ { "SBFX", 0xf3400000, 0xfff08010, BFC_THUMB2 }, // SBFX <Rn>, <Rd>, #<lsb>, #<width>
+ { "UBFX", 0xf3c00000, 0xfff08010, BFC_THUMB2 }, // UBFX <Rn>, <Rd>, #<lsb>, #<width>
+
+ { "CPD", 0xee000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
+ { "CPD2", 0xfe000000, 0xff000010, CPD_THUMB2 }, // CPD <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
+
+ { "MRC", 0xee100000, 0xff100000, MRC_THUMB2 }, // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
+ { "MRC2", 0xfe100000, 0xff100000, MRC_THUMB2 }, // MRC2 <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
+ { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+ { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
+
+ { "MRS", 0xf3ef8000, 0xfffff0ff, THUMB2_MRS }, // MRS <Rd>, CPSR
+ { "MSR", 0xf3808000, 0xfff0fcff, THUMB2_MSR }, // MSR CPSR_fs, <Rn>
+
+ { "CLREX", 0xf3bf8f2f, 0xfffffff, THUMB2_NO_ARGS }, // CLREX
+
+ { "CLZ", 0xfab0f080, 0xfff0f0f0, THUMB2_2REGS }, // CLZ <Rd>,<Rm>
+ { "MOV", 0xec4f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOV <Rd>,<Rm>
+ { "MOVS", 0xec5f0000, 0xfff0f0f0, THUMB2_2REGS }, // MOVS <Rd>,<Rm>
+ { "RBIT", 0xfb90f0a0, 0xfff0f0f0, THUMB2_2REGS }, // RBIT <Rd>,<Rm>
+ { "REV", 0xfb90f080, 0xfff0f0f0, THUMB2_2REGS }, // REV <Rd>,<Rm>
+ { "REV16", 0xfa90f090, 0xfff0f0f0, THUMB2_2REGS }, // REV16 <Rd>,<Rm>
+ { "REVSH", 0xfa90f0b0, 0xfff0f0f0, THUMB2_2REGS }, // REVSH <Rd>,<Rm>
+ { "RRX", 0xea4f0030, 0xfffff0f0, THUMB2_2REGS }, // RRX <Rd>,<Rm>
+ { "RRXS", 0xea5f0030, 0xfffff0f0, THUMB2_2REGS }, // RRXS <Rd>,<Rm>
+
+ { "MLA", 0xfb000000, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
+ { "MLS", 0xfb000010, 0xfff000f0, THUMB2_4REGS }, // MLA <Rd>, <Rn>, <Rm>, <Ra>
+
+ { "SMLABB", 0xfb100000, 0xfff000f0, THUMB2_4REGS }, // SMLABB <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLABT", 0xfb100010, 0xfff000f0, THUMB2_4REGS }, // SMLABT <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLABB", 0xfb100020, 0xfff000f0, THUMB2_4REGS }, // SMLATB <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLATT", 0xfb100030, 0xfff000f0, THUMB2_4REGS }, // SMLATT <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLAWB", 0xfb300000, 0xfff000f0, THUMB2_4REGS }, // SMLAWB <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLAWT", 0xfb300010, 0xfff000f0, THUMB2_4REGS }, // SMLAWT <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLSD", 0xfb400000, 0xfff000f0, THUMB2_4REGS }, // SMLSD <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLSDX", 0xfb400010, 0xfff000f0, THUMB2_4REGS }, // SMLSDX <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMMLA", 0xfb500000, 0xfff000f0, THUMB2_4REGS }, // SMMLA <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMMLAR", 0xfb500010, 0xfff000f0, THUMB2_4REGS }, // SMMLAR <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMMLS", 0xfb600000, 0xfff000f0, THUMB2_4REGS }, // SMMLS <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMMLSR", 0xfb600010, 0xfff000f0, THUMB2_4REGS }, // SMMLSR <Rd>, <Rn>, <Rm>, <Ra>
+ { "USADA8", 0xfb700000, 0xfff000f0, THUMB2_4REGS }, // USADA8 <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLAD", 0xfb200000, 0xfff000f0, THUMB2_4REGS }, // SMLAD <Rd>, <Rn>, <Rm>, <Ra>
+ { "SMLADX", 0xfb200010, 0xfff000f0, THUMB2_4REGS }, // SMLADX <Rd>, <Rn>, <Rm>, <Ra>
+
+ { "B", 0xf0008000, 0xf800d000, B_T3 }, // B<c> <label>
+ { "B", 0xf0009000, 0xf800d000, B_T4 }, // B<c> <label>
+ { "BL", 0xf000d000, 0xf800d000, B_T4 }, // BL<c> <label>
+ { "BLX", 0xf000c000, 0xf800d000, BL_T2 }, // BLX<c> <label>
+
+ { "POP", 0xe8bd0000, 0xffff2000, POP_T2 }, // POP <registers>
+ { "POP", 0xf85d0b04, 0xffff0fff, POP_T3 }, // POP <register>
+ { "PUSH", 0xe8ad0000, 0xffffa000, POP_T2 }, // PUSH <registers>
+ { "PUSH", 0xf84d0d04, 0xffff0fff, POP_T3 }, // PUSH <register>
+ { "STM", 0xe8800000, 0xffd0a000, STM_FORMAT }, // STM <Rn>{!},<registers>
+ { "STMDB", 0xe9800000, 0xffd0a000, STM_FORMAT }, // STMDB <Rn>{!},<registers>
+ { "LDM", 0xe8900000, 0xffd02000, STM_FORMAT }, // LDM <Rn>{!},<registers>
+ { "LDMDB", 0xe9100000, 0xffd02000, STM_FORMAT }, // LDMDB <Rn>{!},<registers>
+
+ { "LDR", 0xf8d00000, 0xfff00000, LDM_REG_IMM12 }, // LDR <rt>, [<rn>, {, #<imm12>]}
+ { "LDRB", 0xf8900000, 0xfff00000, LDM_REG_IMM12 }, // LDRB <rt>, [<rn>, {, #<imm12>]}
+ { "LDRH", 0xf8b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRH <rt>, [<rn>, {, #<imm12>]}
+ { "LDRSB", 0xf9900000, 0xfff00000, LDM_REG_IMM12 }, // LDRSB <rt>, [<rn>, {, #<imm12>]}
+ { "LDRSH", 0xf9b00000, 0xfff00000, LDM_REG_IMM12 }, // LDRSH <rt>, [<rn>, {, #<imm12>]}
+
+ { "LDR", 0xf85f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDR <Rt>, <label>
+ { "LDRB", 0xf81f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRB <Rt>, <label>
+ { "LDRH", 0xf83f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRH <Rt>, <label>
+ { "LDRSB", 0xf91f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
+ { "LDRSH", 0xf93f0000, 0xff7f0000, LDM_REG_IMM12_SIGNED }, // LDRSB <Rt>, <label>
+
+ { "LDR", 0xf8500000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "LDRB", 0xf8100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "LDRH", 0xf8300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "LDRSB", 0xf9100000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "LDRSH", 0xf9300000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // LDRSH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+
+ { "LDR", 0xf8500800, 0xfff00800, LDM_REG_IMM8 }, // LDR <rt>, [<rn>, {, #<imm8>]}
+ { "LDRBT", 0xf8100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRBT <rt>, [<rn>, {, #<imm8>]}
+ { "LDRHT", 0xf8300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]}
+ { "LDRSB", 0xf9100800, 0xfff00800, LDM_REG_IMM8 }, // LDRHT <rt>, [<rn>, {, #<imm8>]} {!} form?
+ { "LDRSBT", 0xf9100e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRHBT <rt>, [<rn>, {, #<imm8>]} {!} form?
+ { "LDRSH", 0xf9300800, 0xfff00800, LDM_REG_IMM8 }, // LDRSH <rt>, [<rn>, {, #<imm8>]}
+ { "LDRSHT", 0xf9300e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRSHT <rt>, [<rn>, {, #<imm8>]}
+ { "LDRT", 0xf8500e00, 0xfff00f00, LDM_REG_IMM8 }, // LDRT <rt>, [<rn>, {, #<imm8>]}
+
+ { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
+ { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>
+
+ { "LDREX", 0xe8500f00, 0xfff00f00, LDM_REG_IMM8 }, // LDREX <Rt>, [Rn, {#imm8}]]
+ { "LDREXB", 0xe8d00f4f, 0xfff00fff, LDREXB }, // LDREXB <Rt>, [<Rn>]
+ { "LDREXH", 0xe8d00f5f, 0xfff00fff, LDREXB }, // LDREXH <Rt>, [<Rn>]
+
+ { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]
+
+ { "STR", 0xf8c00000, 0xfff00000, LDM_REG_IMM12 }, // STR <rt>, [<rn>, {, #<imm12>]}
+ { "STRB", 0xf8800000, 0xfff00000, LDM_REG_IMM12 }, // STRB <rt>, [<rn>, {, #<imm12>]}
+ { "STRH", 0xf8a00000, 0xfff00000, LDM_REG_IMM12 }, // STRH <rt>, [<rn>, {, #<imm12>]}
+
+ { "STR", 0xf8400000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STR <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "STRB", 0xf8000000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRB <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ { "STRH", 0xf8200000, 0xfff00fc0, LDM_REG_INDIRECT_LSL }, // STRH <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+
+ { "STR", 0xf8400800, 0xfff00800, LDM_REG_IMM8 }, // STR <rt>, [<rn>, {, #<imm8>]}
+ { "STRH", 0xf8200800, 0xfff00800, LDM_REG_IMM8 }, // STRH <rt>, [<rn>, {, #<imm8>]}
+ { "STRBT", 0xf8000e00, 0xfff00f00, LDM_REG_IMM8 }, // STRBT <rt>, [<rn>, {, #<imm8>]}
+ { "STRHT", 0xf8200e00, 0xfff00f00, LDM_REG_IMM8 }, // STRHT <rt>, [<rn>, {, #<imm8>]}
+ { "STRT", 0xf8400e00, 0xfff00f00, LDM_REG_IMM8 }, // STRT <rt>, [<rn>, {, #<imm8>]}
+
+ { "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
+
+ { "STREX", 0xe8400f00, 0xfff00f00, LDM_REG_IMM8 }, // STREX <Rt>, [Rn, {#imm8}]]
+ { "STREXB", 0xe8c00f4f, 0xfff00fff, LDREXB }, // STREXB <Rd>, <Rt>, [<Rn>]
+ { "STREXH", 0xe8c00f5f, 0xfff00fff, LDREXB }, // STREXH <Rd>, <Rt>, [<Rn>]
+
+ { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]
+
+ { "SRSDB", 0xe80dc000, 0xffdffff0, SRS_FORMAT }, // SRSDB<c> SP{!},#<mode>
+ { "SRS", 0xe98dc000, 0xffdffff0, SRS_FORMAT }, // SRS{IA}<c> SP{!},#<mode>
+ { "RFEDB", 0xe810c000, 0xffd0ffff, RFE_FORMAT }, // RFEDB<c> <Rn>{!}
+ { "RFE", 0xe990c000, 0xffd0ffff, RFE_FORMAT } // RFE{IA}<c> <Rn>{!}
};
-CHAR8 *gShiftType[] = {
+CHAR8 *gShiftType[] = {
"LSL",
"LSR",
"ASR",
"ROR"
};
-CHAR8 mThumbMregListStr[4*15 + 1];
+CHAR8 mThumbMregListStr[4*15 + 1];
CHAR8 *
ThumbMRegList (
UINT32 RegBitMask
)
{
- UINTN Index, Start, End;
- BOOLEAN First;
+ UINTN Index, Start, End;
+ BOOLEAN First;
mThumbMregListStr[0] = '\0';
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "{");
@@ -419,9 +413,11 @@ ThumbMRegList ( }
}
}
+
if (First) {
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "ERROR");
}
+
AsciiStrCatS (mThumbMregListStr, sizeof mThumbMregListStr, "}");
// BugBug: Make caller pass in buffer it is cleaner
@@ -440,7 +436,7 @@ SignExtend32 ( do {
TopBit <<= 1;
- Data |= TopBit;
+ Data |= TopBit;
} while ((TopBit & BIT31) != BIT31);
return Data;
@@ -474,53 +470,54 @@ PcAlign4 ( **/
VOID
DisassembleThumbInstruction (
- IN UINT16 **OpCodePtrPtr,
- OUT CHAR8 *Buf,
- OUT UINTN Size,
- OUT UINT32 *ItBlock,
- IN BOOLEAN Extended
+ IN UINT16 **OpCodePtrPtr,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size,
+ OUT UINT32 *ItBlock,
+ IN BOOLEAN Extended
)
{
- UINT16 *OpCodePtr;
- UINT16 OpCode;
- UINT32 OpCode32;
- UINT32 Index;
- UINT32 Offset;
- UINT16 Rd, Rn, Rm, Rt, Rt2;
- BOOLEAN H1Bit; // H1
- BOOLEAN H2Bit; // H2
- BOOLEAN IMod; // imod
- //BOOLEAN ItFlag;
- UINT32 Pc, Target, MsBit, LsBit;
- CHAR8 *Cond;
- BOOLEAN Sign; // S
- BOOLEAN J1Bit; // J1
- BOOLEAN J2Bit; // J2
- BOOLEAN Pre; // P
- BOOLEAN UAdd; // U
- BOOLEAN WriteBack; // W
- UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
- UINT32 Mask;
+ UINT16 *OpCodePtr;
+ UINT16 OpCode;
+ UINT32 OpCode32;
+ UINT32 Index;
+ UINT32 Offset;
+ UINT16 Rd, Rn, Rm, Rt, Rt2;
+ BOOLEAN H1Bit; // H1
+ BOOLEAN H2Bit; // H2
+ BOOLEAN IMod; // imod
+ // BOOLEAN ItFlag;
+ UINT32 Pc, Target, MsBit, LsBit;
+ CHAR8 *Cond;
+ BOOLEAN Sign; // S
+ BOOLEAN J1Bit; // J1
+ BOOLEAN J2Bit; // J2
+ BOOLEAN Pre; // P
+ BOOLEAN UAdd; // U
+ BOOLEAN WriteBack; // W
+ UINT32 Coproc, Opc1, Opc2, CRd, CRn, CRm;
+ UINT32 Mask;
OpCodePtr = *OpCodePtrPtr;
- OpCode = **OpCodePtrPtr;
+ OpCode = **OpCodePtrPtr;
// Thumb2 is a stream of 16-bit instructions not a 32-bit instruction.
OpCode32 = (((UINT32)OpCode) << 16) | *(OpCodePtr + 1);
// These register names match branch form, but not others
- Rd = OpCode & 0x7;
- Rn = (OpCode >> 3) & 0x7;
- Rm = (OpCode >> 6) & 0x7;
+ Rd = OpCode & 0x7;
+ Rn = (OpCode >> 3) & 0x7;
+ Rm = (OpCode >> 6) & 0x7;
H1Bit = (OpCode & BIT7) != 0;
H2Bit = (OpCode & BIT6) != 0;
- IMod = (OpCode & BIT4) != 0;
- Pc = (UINT32)(UINTN)OpCodePtr;
+ IMod = (OpCode & BIT4) != 0;
+ Pc = (UINT32)(UINTN)OpCodePtr;
// Increment by the minimum instruction size, Thumb2 could be bigger
*OpCodePtrPtr += 1;
// Manage IT Block ItFlag TRUE means we are in an IT block
+
/*if (*ItBlock != 0) {
ItFlag = TRUE;
*ItBlock -= 1;
@@ -535,169 +532,169 @@ DisassembleThumbInstruction ( } else {
Offset = AsciiSPrint (Buf, Size, "%-6a", gOpThumb[Index].Start);
}
+
switch (gOpThumb[Index].AddressMode) {
- case LOAD_STORE_FORMAT1:
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
- return;
- case LOAD_STORE_FORMAT1_H:
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);
- return;
- case LOAD_STORE_FORMAT1_B:
- // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);
- return;
-
- case LOAD_STORE_FORMAT2:
- // A6.5.1 <Rd>, [<Rn>, <Rm>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
- return;
- case LOAD_STORE_FORMAT3:
- // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
- Target = (OpCode & 0xff) << 2;
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
- return;
- case LOAD_STORE_FORMAT4:
- // Rt, [SP, #imm8]
- Target = (OpCode & 0xff) << 2;
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);
- return;
-
- case LOAD_STORE_MULTIPLE_FORMAT1:
- // <Rn>!, {r0-r7}
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
- return;
-
- case POP_FORMAT:
- // POP {r0-r7,pc}
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
- return;
-
- case PUSH_FORMAT:
- // PUSH {r0-r7,lr}
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
- return;
-
-
- case IMMED_8:
- // A6.7 <immed_8>
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
- return;
-
- case CONDITIONAL_BRANCH:
- // A6.3.1 B<cond> <target_address>
- // Patch in the condition code. A little hack but based on "%-6a"
- Cond = gCondition[(OpCode >> 8) & 0xf];
- Buf[Offset-5] = *Cond++;
- Buf[Offset-4] = *Cond;
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
- return;
- case UNCONDITIONAL_BRANCH_SHORT:
- // A6.3.2 B <target_address>
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
- return;
-
- case BRANCH_EXCHANGE:
- // A6.3.3 BX|BLX <Rm>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8:0)]);
- return;
-
- case DATA_FORMAT1:
- // A6.4.3 <Rd>, <Rn>, <Rm>
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
- return;
- case DATA_FORMAT2:
- // A6.4.3 <Rd>, <Rn>, #3_bit_immed
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
- return;
- case DATA_FORMAT3:
- // A6.4.3 <Rd>|<Rn>, #imm8
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
- return;
- case DATA_FORMAT4:
- // A6.4.3 <Rd>|<Rm>, #immed_5
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
- return;
- case DATA_FORMAT5:
- // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
- return;
- case DATA_FORMAT6_SP:
- // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
- return;
- case DATA_FORMAT6_PC:
- // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
- AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
- return;
- case DATA_FORMAT7:
- // A6.4.3 SP, SP, #<7_Bit_immed>
- AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
- return;
- case DATA_FORMAT8:
- // A6.4.3 <Rd>|<Rn>, <Rm>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8:0)], gReg[Rn | (H2Bit ? 8:0)]);
- return;
-
- case CPS_FORMAT:
- // A7.1.24
- AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID":"IE", ((OpCode & BIT2) == 0) ? "":"a", ((OpCode & BIT1) == 0) ? "":"i", ((OpCode & BIT0) == 0) ? "":"f");
- return;
-
- case ENDIAN_FORMAT:
- // A7.1.24
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE":"BE");
- return;
-
- case DATA_CBZ:
- // CB{N}Z <Rn>, <Lable>
- Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
- return;
-
- case ADR_FORMAT:
- // ADR <Rd>, <Label>
- Target = (OpCode & 0xff) << 2;
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
- return;
-
- case IT_BLOCK:
- // ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]
- // ITSTATE[7:5] == cond[3:1]
- // ITSTATE[4] == 1st Instruction cond[0]
- // ITSTATE[3] == 2st Instruction cond[0]
- // ITSTATE[2] == 3st Instruction cond[0]
- // ITSTATE[1] == 4st Instruction cond[0]
- // ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions
- // 1st one in ITSTATE low bits defines the number of instructions
- Mask = (OpCode & 0xf);
- if ((Mask & 0x1) == 0x1) {
- *ItBlock = 4;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a%a", (Mask & BIT3)?"T":"E", (Mask & BIT2)?"T":"E", (Mask & BIT1)?"T":"E");
- } else if ((OpCode & 0x3) == 0x2) {
- *ItBlock = 3;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a", (Mask & BIT3)?"T":"E", (Mask & BIT2)?"T":"E");
- } else if ((OpCode & 0x7) == 0x4) {
- *ItBlock = 2;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a", (Mask & BIT3)?"T":"E");
- } else if ((OpCode & 0xf) == 0x8) {
- *ItBlock = 1;
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);
- return;
+ case LOAD_STORE_FORMAT1:
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 4) & 0x7c);
+ return;
+ case LOAD_STORE_FORMAT1_H:
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 5) & 0x3e);
+ return;
+ case LOAD_STORE_FORMAT1_B:
+ // A6.5.1 <Rd>, [<Rn>, #<5_bit_offset>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d #0x%x]", Rd, Rn, (OpCode >> 6) & 0x1f);
+ return;
+
+ case LOAD_STORE_FORMAT2:
+ // A6.5.1 <Rd>, [<Rn>, <Rm>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [r%d, r%d]", Rd, Rn, Rm);
+ return;
+ case LOAD_STORE_FORMAT3:
+ // A6.5.1 <Rd>, [PC, #<8_bit_offset>]
+ Target = (OpCode & 0xff) << 2;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [pc, #0x%x] ;0x%08x", (OpCode >> 8) & 7, Target, PcAlign4 (Pc) + Target);
+ return;
+ case LOAD_STORE_FORMAT4:
+ // Rt, [SP, #imm8]
+ Target = (OpCode & 0xff) << 2;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, [sp, #0x%x]", (OpCode >> 8) & 7, Target);
+ return;
+
+ case LOAD_STORE_MULTIPLE_FORMAT1:
+ // <Rn>!, {r0-r7}
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d!, %a", (OpCode >> 8) & 7, ThumbMRegList (OpCode & 0xff));
+ return;
+
+ case POP_FORMAT:
+ // POP {r0-r7,pc}
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT15 : 0)));
+ return;
+
+ case PUSH_FORMAT:
+ // PUSH {r0-r7,lr}
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList ((OpCode & 0xff) | ((OpCode & BIT8) == BIT8 ? BIT14 : 0)));
+ return;
+
+ case IMMED_8:
+ // A6.7 <immed_8>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%x", OpCode & 0xff);
+ return;
+
+ case CONDITIONAL_BRANCH:
+ // A6.3.1 B<cond> <target_address>
+ // Patch in the condition code. A little hack but based on "%-6a"
+ Cond = gCondition[(OpCode >> 8) & 0xf];
+ Buf[Offset-5] = *Cond++;
+ Buf[Offset-4] = *Cond;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0xff) << 1, BIT8));
+ return;
+ case UNCONDITIONAL_BRANCH_SHORT:
+ // A6.3.2 B <target_address>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%04x", Pc + 4 + SignExtend32 ((OpCode & 0x3ff) << 1, BIT11));
+ return;
+
+ case BRANCH_EXCHANGE:
+ // A6.3.3 BX|BLX <Rm>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[Rn | (H2Bit ? 8 : 0)]);
+ return;
+
+ case DATA_FORMAT1:
+ // A6.4.3 <Rd>, <Rn>, <Rm>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, r%d", Rd, Rn, Rm);
+ return;
+ case DATA_FORMAT2:
+ // A6.4.3 <Rd>, <Rn>, #3_bit_immed
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rd, Rn, Rm);
+ return;
+ case DATA_FORMAT3:
+ // A6.4.3 <Rd>|<Rn>, #imm8
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, #0x%x", (OpCode >> 8) & 7, OpCode & 0xff);
+ return;
+ case DATA_FORMAT4:
+ // A6.4.3 <Rd>|<Rm>, #immed_5
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d, 0x%x", Rn, Rd, (OpCode >> 6) & 0x1f);
+ return;
+ case DATA_FORMAT5:
+ // A6.4.3 <Rd>|<Rm>, <Rm>|<Rs>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, r%d", Rd, Rn);
+ return;
+ case DATA_FORMAT6_SP:
+ // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, sp, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
+ return;
+ case DATA_FORMAT6_PC:
+ // A6.4.3 <Rd>, <reg>, #<8_Bit_immed>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " r%d, pc, 0x%x", (OpCode >> 8) & 7, (OpCode & 0xff) << 2);
+ return;
+ case DATA_FORMAT7:
+ // A6.4.3 SP, SP, #<7_Bit_immed>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " sp, sp, 0x%x", (OpCode & 0x7f)*4);
+ return;
+ case DATA_FORMAT8:
+ // A6.4.3 <Rd>|<Rn>, <Rm>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd | (H1Bit ? 8 : 0)], gReg[Rn | (H2Bit ? 8 : 0)]);
+ return;
+
+ case CPS_FORMAT:
+ // A7.1.24
+ AsciiSPrint (&Buf[Offset], Size - Offset, "%a %a%a%a", IMod ? "ID" : "IE", ((OpCode & BIT2) == 0) ? "" : "a", ((OpCode & BIT1) == 0) ? "" : "i", ((OpCode & BIT0) == 0) ? "" : "f");
+ return;
+
+ case ENDIAN_FORMAT:
+ // A7.1.24
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", (OpCode & BIT3) == 0 ? "LE" : "BE");
+ return;
+
+ case DATA_CBZ:
+ // CB{N}Z <Rn>, <Lable>
+ Target = ((OpCode >> 2) & 0x3e) | (((OpCode & BIT9) == BIT9) ? BIT6 : 0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[Rd], Pc + 4 + Target);
+ return;
+
+ case ADR_FORMAT:
+ // ADR <Rd>, <Label>
+ Target = (OpCode & 0xff) << 2;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %08x", gReg[(OpCode >> 8) & 7], PcAlign4 (Pc) + Target);
+ return;
+
+ case IT_BLOCK:
+ // ITSTATE = cond:mask OpCode[7:4]:OpCode[3:0]
+ // ITSTATE[7:5] == cond[3:1]
+ // ITSTATE[4] == 1st Instruction cond[0]
+ // ITSTATE[3] == 2st Instruction cond[0]
+ // ITSTATE[2] == 3st Instruction cond[0]
+ // ITSTATE[1] == 4st Instruction cond[0]
+ // ITSTATE[0] == 1 4 instruction IT block. 0 means 0,1,2 or 3 instructions
+ // 1st one in ITSTATE low bits defines the number of instructions
+ Mask = (OpCode & 0xf);
+ if ((Mask & 0x1) == 0x1) {
+ *ItBlock = 4;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a%a", (Mask & BIT3) ? "T" : "E", (Mask & BIT2) ? "T" : "E", (Mask & BIT1) ? "T" : "E");
+ } else if ((OpCode & 0x3) == 0x2) {
+ *ItBlock = 3;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a%a", (Mask & BIT3) ? "T" : "E", (Mask & BIT2) ? "T" : "E");
+ } else if ((OpCode & 0x7) == 0x4) {
+ *ItBlock = 2;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, "%a", (Mask & BIT3) ? "T" : "E");
+ } else if ((OpCode & 0xf) == 0x8) {
+ *ItBlock = 1;
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gCondition[(OpCode >> 4) & 0xf]);
+ return;
}
}
}
-
// Thumb2 are 32-bit instructions
*OpCodePtrPtr += 1;
- Rt = (OpCode32 >> 12) & 0xf;
- Rt2 = (OpCode32 >> 8) & 0xf;
- Rd = (OpCode32 >> 8) & 0xf;
- Rm = (OpCode32 & 0xf);
- Rn = (OpCode32 >> 16) & 0xf;
+ Rt = (OpCode32 >> 12) & 0xf;
+ Rt2 = (OpCode32 >> 8) & 0xf;
+ Rd = (OpCode32 >> 8) & 0xf;
+ Rm = (OpCode32 & 0xf);
+ Rn = (OpCode32 >> 16) & 0xf;
for (Index = 0; Index < sizeof (gOpThumb2)/sizeof (THUMB_INSTRUCTIONS); Index++) {
if ((OpCode32 & gOpThumb2[Index].Mask) == gOpThumb2[Index].OpCode) {
if (Extended) {
@@ -705,313 +702,329 @@ DisassembleThumbInstruction ( } else {
Offset = AsciiSPrint (Buf, Size, " %-6a", gOpThumb2[Index].Start);
}
+
switch (gOpThumb2[Index].AddressMode) {
- case B_T3:
- Cond = gCondition[(OpCode32 >> 22) & 0xf];
- Buf[Offset-5] = *Cond++;
- Buf[Offset-4] = *Cond;
- // S:J2:J1:imm6:imm11:0
- Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3f000);
- Target |= ((OpCode32 & BIT11) == BIT11)? BIT19 : 0; // J2
- Target |= ((OpCode32 & BIT13) == BIT13)? BIT18 : 0; // J1
- Target |= ((OpCode32 & BIT26) == BIT26)? BIT20 : 0; // S
- Target = SignExtend32 (Target, BIT20);
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
- return;
- case B_T4:
- // S:I1:I2:imm10:imm11:0
- Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
- Sign = (OpCode32 & BIT26) == BIT26;
- J1Bit = (OpCode32 & BIT13) == BIT13;
- J2Bit = (OpCode32 & BIT11) == BIT11;
- Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
- Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
- Target |= (Sign ? BIT24 : 0); // S
- Target = SignExtend32 (Target, BIT24);
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
- return;
-
- case BL_T2:
- // BLX S:I1:I2:imm10:imm11:0
- Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
- Sign = (OpCode32 & BIT26) == BIT26;
- J1Bit = (OpCode32 & BIT13) == BIT13;
- J2Bit = (OpCode32 & BIT11) == BIT11;
- Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
- Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
- Target |= (Sign ? BIT25 : 0); // S
- Target = SignExtend32 (Target, BIT25);
- AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
- return;
-
- case POP_T2:
- // <reglist> some must be zero, handled in table
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList (OpCode32 & 0xffff));
- return;
-
- case POP_T3:
- // <register>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);
- return;
-
- case STM_FORMAT:
- // <Rn>{!}, <registers>
- WriteBack = (OpCode32 & BIT21) == BIT21;
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!":"", ThumbMRegList (OpCode32 & 0xffff));
- return;
-
- case LDM_REG_IMM12_SIGNED:
- // <rt>, <label>
- Target = OpCode32 & 0xfff;
- if ((OpCode32 & BIT23) == 0) {
- // U == 0 means subtrack, U == 1 means add
- Target = -Target;
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
- return;
-
- case LDM_REG_INDIRECT_LSL:
- // <rt>, [<rn>, <rm> {, LSL #<imm2>]}
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a, %a", gReg[Rt], gReg[Rn], gReg[Rm]);
- if (((OpCode32 >> 4) & 3) == 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, "]");
- } else {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);
- }
- return;
-
- case LDM_REG_IMM12:
- // <rt>, [<rn>, {, #<imm12>]}
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
- if ((OpCode32 & 0xfff) == 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, "]");
- } else {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #0x%x]", OpCode32 & 0xfff);
- }
- return;
-
- case LDM_REG_IMM8:
- // <rt>, [<rn>, {, #<imm8>}]{!}
- WriteBack = (OpCode32 & BIT8) == BIT8;
- UAdd = (OpCode32 & BIT9) == BIT9;
- Pre = (OpCode32 & BIT10) == BIT10;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
- if (Pre) {
- if ((OpCode32 & 0xff) == 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack?"!":"");
+ case B_T3:
+ Cond = gCondition[(OpCode32 >> 22) & 0xf];
+ Buf[Offset-5] = *Cond++;
+ Buf[Offset-4] = *Cond;
+ // S:J2:J1:imm6:imm11:0
+ Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3f000);
+ Target |= ((OpCode32 & BIT11) == BIT11) ? BIT19 : 0; // J2
+ Target |= ((OpCode32 & BIT13) == BIT13) ? BIT18 : 0; // J1
+ Target |= ((OpCode32 & BIT26) == BIT26) ? BIT20 : 0; // S
+ Target = SignExtend32 (Target, BIT20);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
+ return;
+ case B_T4:
+ // S:I1:I2:imm10:imm11:0
+ Target = ((OpCode32 << 1) & 0xffe) + ((OpCode32 >> 4) & 0x3ff000);
+ Sign = (OpCode32 & BIT26) == BIT26;
+ J1Bit = (OpCode32 & BIT13) == BIT13;
+ J2Bit = (OpCode32 & BIT11) == BIT11;
+ Target |= (!(J2Bit ^ Sign) ? BIT22 : 0); // I2
+ Target |= (!(J1Bit ^ Sign) ? BIT23 : 0); // I1
+ Target |= (Sign ? BIT24 : 0); // S
+ Target = SignExtend32 (Target, BIT24);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", Pc + 4 + Target);
+ return;
+
+ case BL_T2:
+ // BLX S:I1:I2:imm10:imm11:0
+ Target = ((OpCode32 << 1) & 0xffc) + ((OpCode32 >> 4) & 0x3ff000);
+ Sign = (OpCode32 & BIT26) == BIT26;
+ J1Bit = (OpCode32 & BIT13) == BIT13;
+ J2Bit = (OpCode32 & BIT11) == BIT11;
+ Target |= (!(J2Bit ^ Sign) ? BIT23 : 0); // I2
+ Target |= (!(J1Bit ^ Sign) ? BIT24 : 0); // I1
+ Target |= (Sign ? BIT25 : 0); // S
+ Target = SignExtend32 (Target, BIT25);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " 0x%08x", PcAlign4 (Pc) + Target);
+ return;
+
+ case POP_T2:
+ // <reglist> some must be zero, handled in table
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", ThumbMRegList (OpCode32 & 0xffff));
+ return;
+
+ case POP_T3:
+ // <register>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a", gReg[(OpCode32 >> 12) & 0xf]);
+ return;
+
+ case STM_FORMAT:
+ // <Rn>{!}, <registers>
+ WriteBack = (OpCode32 & BIT21) == BIT21;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, %a", gReg[(OpCode32 >> 16) & 0xf], WriteBack ? "!" : "", ThumbMRegList (OpCode32 & 0xffff));
+ return;
+
+ case LDM_REG_IMM12_SIGNED:
+ // <rt>, <label>
+ Target = OpCode32 & 0xfff;
+ if ((OpCode32 & BIT23) == 0) {
+ // U == 0 means subtrack, U == 1 means add
+ Target = -Target;
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[(OpCode32 >> 12) & 0xf], PcAlign4 (Pc) + Target);
+ return;
+
+ case LDM_REG_INDIRECT_LSL:
+ // <rt>, [<rn>, <rm> {, LSL #<imm2>]}
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a, %a", gReg[Rt], gReg[Rn], gReg[Rm]);
+ if (((OpCode32 >> 4) & 3) == 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");
} else {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-" , OpCode32 & 0xff, WriteBack?"!":"");
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL #%d]", (OpCode32 >> 4) & 3);
}
- } else {
- AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd?"":"-", OpCode32 & 0xff);
- }
- return;
-
- case LDRD_REG_IMM8_SIGNED:
- // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
- Pre = (OpCode32 & BIT24) == BIT24; // index = P
- UAdd = (OpCode32 & BIT23) == BIT23;
- WriteBack = (OpCode32 & BIT21) == BIT21;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
- if (Pre) {
- if ((OpCode32 & 0xff) == 0) {
+
+ return;
+
+ case LDM_REG_IMM12:
+ // <rt>, [<rn>, {, #<imm12>]}
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
+ if ((OpCode32 & 0xfff) == 0) {
AsciiSPrint (&Buf[Offset], Size - Offset, "]");
} else {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd?"":"-", (OpCode32 & 0xff) << 2, WriteBack?"!":"");
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #0x%x]", OpCode32 & 0xfff);
+ }
+
+ return;
+
+ case LDM_REG_IMM8:
+ // <rt>, [<rn>, {, #<imm8>}]{!}
+ WriteBack = (OpCode32 & BIT8) == BIT8;
+ UAdd = (OpCode32 & BIT9) == BIT9;
+ Pre = (OpCode32 & BIT10) == BIT10;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a", gReg[Rt], gReg[Rn]);
+ if (Pre) {
+ if ((OpCode32 & 0xff) == 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]%a", WriteBack ? "!" : "");
+ } else {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd ? "" : "-", OpCode32 & 0xff, WriteBack ? "!" : "");
+ }
+ } else {
+ AsciiSPrint (&Buf[Offset], Size - Offset, "], #%a0x%x", UAdd ? "" : "-", OpCode32 & 0xff);
}
- } else {
- if ((OpCode32 & 0xff) != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd?"":"-", (OpCode32 & 0xff) << 2);
+
+ return;
+
+ case LDRD_REG_IMM8_SIGNED:
+ // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
+ Pre = (OpCode32 & BIT24) == BIT24; // index = P
+ UAdd = (OpCode32 & BIT23) == BIT23;
+ WriteBack = (OpCode32 & BIT21) == BIT21;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, [%a", gReg[Rt], gReg[Rt2], gReg[Rn]);
+ if (Pre) {
+ if ((OpCode32 & 0xff) == 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, "]");
+ } else {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x]%a", UAdd ? "" : "-", (OpCode32 & 0xff) << 2, WriteBack ? "!" : "");
+ }
+ } else {
+ if ((OpCode32 & 0xff) != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", #%a0x%x", UAdd ? "" : "-", (OpCode32 & 0xff) << 2);
+ }
}
- }
- return;
-
- case LDRD_REG_IMM8:
- // LDRD <rt>, <rt2>, <label>
- Target = (OpCode32 & 0xff) << 2;
- if ((OpCode32 & BIT23) == 0) {
- // U == 0 means subtrack, U == 1 means add
- Target = -Target;
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
- return;
-
- case LDREXB:
- // LDREXB <Rt>, [Rn]
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a]", gReg[Rt], gReg[Rn]);
- return;
-
- case LDREXD:
- // LDREXD <Rt>, <Rt2>, [<Rn>]
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);
- return;
-
- case SRS_FORMAT:
- // SP{!}, #<mode>
- WriteBack = (OpCode32 & BIT21) == BIT21;
- AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack?"!":"", OpCode32 & 0x1f);
- return;
-
- case RFE_FORMAT:
- // <Rn>{!}
- WriteBack = (OpCode32 & BIT21) == BIT21;
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack?"!":"");
- return;
-
- case ADD_IMM12:
- // ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
- return;
-
- case ADD_IMM12_1REG:
- // MOV{S} <Rd>, #<const> i:imm3:imm8
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
- return;
-
- case THUMB2_IMM16:
- // MOVW <Rd>, #<const> i:imm3:imm8
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- Target |= ((OpCode32 >> 4) & 0xf0000);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
- return;
-
- case ADD_IMM5:
- // ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
- if (Target != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
- }
- return;
-
- case ADD_IMM5_2REG:
- // CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);
- if (Target != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
- }
-
-
- case ASR_IMM5:
- // ARS <Rd>, <Rm> #<const>} imm3:imm2
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);
- return;
-
- case ASR_3REG:
- // ARS <Rd>, <Rn>, <Rm>
- if ((OpCode32 & BIT20) == BIT20) {
- Buf[Offset - 3] = 'S'; // assume %-6a
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);
- return;
-
- case ADR_THUMB2:
- // ADDR <Rd>, <label>
- Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
- Target = PcAlign4 (Pc) - Target;
- } else {
- Target = PcAlign4 (Pc) + Target;
- }
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
- return;
-
- case CMN_THUMB2:
- // CMN <Rn>, #<const>}
- Target = (OpCode32 & 0xff) | ((OpCode >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);
- return;
-
- case BFC_THUMB2:
- // BFI <Rd>, <Rn>, #<lsb>, #<width>
- MsBit = OpCode32 & 0x1f;
- LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
- if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)){
- // BFC <Rd>, #<lsb>, #<width>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
- } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
- } else {
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
- }
- return;
-
- case CPD_THUMB2:
- // <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
- Coproc = (OpCode32 >> 8) & 0xf;
- Opc1 = (OpCode32 >> 20) & 0xf;
- Opc2 = (OpCode32 >> 5) & 0x7;
- CRd = (OpCode32 >> 12) & 0xf;
- CRn = (OpCode32 >> 16) & 0xf;
- CRm = OpCode32 & 0xf;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
- if (Opc2 != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
- }
- return;
-
- case MRC_THUMB2:
- // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
- Coproc = (OpCode32 >> 8) & 0xf;
- Opc1 = (OpCode32 >> 20) & 0xf;
- Opc2 = (OpCode32 >> 5) & 0x7;
- CRn = (OpCode32 >> 16) & 0xf;
- CRm = OpCode32 & 0xf;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
- if (Opc2 != 0) {
- AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
- }
- return;
-
- case MRRC_THUMB2:
- // MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
- Coproc = (OpCode32 >> 8) & 0xf;
- Opc1 = (OpCode32 >> 20) & 0xf;
- CRn = (OpCode32 >> 16) & 0xf;
- CRm = OpCode32 & 0xf;
- Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
- return;
-
- case THUMB2_2REGS:
- // <Rd>, <Rm>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);
- return;
-
- case THUMB2_4REGS:
- // <Rd>, <Rn>, <Rm>, <Ra>
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);
- return;
-
- case THUMB2_MRS:
- // MRS <Rd>, CPSR
- AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);
- return;
-
- case THUMB2_MSR:
- // MRS CPSR_<fields>, <Rd>
- Target = (OpCode32 >> 10) & 3;
- AsciiSPrint (&Buf[Offset], Size - Offset, " CPSR_%a%a, %a", (Target & 2) == 0 ? "":"f", (Target & 1) == 0 ? "":"s", gReg[Rd]);
- return;
-
- case THUMB2_NO_ARGS:
- default:
- break;
+
+ return;
+
+ case LDRD_REG_IMM8:
+ // LDRD <rt>, <rt2>, <label>
+ Target = (OpCode32 & 0xff) << 2;
+ if ((OpCode32 & BIT23) == 0) {
+ // U == 0 means subtrack, U == 1 means add
+ Target = -Target;
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rt], gReg[Rt2], Pc + 4 + Target);
+ return;
+
+ case LDREXB:
+ // LDREXB <Rt>, [Rn]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, [%a]", gReg[Rt], gReg[Rn]);
+ return;
+
+ case LDREXD:
+ // LDREXD <Rt>, <Rt2>, [<Rn>]
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, ,%a, [%a]", gReg[Rt], gReg[Rt2], gReg[Rn]);
+ return;
+
+ case SRS_FORMAT:
+ // SP{!}, #<mode>
+ WriteBack = (OpCode32 & BIT21) == BIT21;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " SP%a, #0x%x", WriteBack ? "!" : "", OpCode32 & 0x1f);
+ return;
+
+ case RFE_FORMAT:
+ // <Rn>{!}
+ WriteBack = (OpCode32 & BIT21) == BIT21;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a%a, #0x%x", gReg[Rn], WriteBack ? "!" : "");
+ return;
+
+ case ADD_IMM12:
+ // ADD{S} <Rd>, <Rn>, #<const> i:imm3:imm8
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #0x%x", gReg[Rd], gReg[Rn], Target);
+ return;
+
+ case ADD_IMM12_1REG:
+ // MOV{S} <Rd>, #<const> i:imm3:imm8
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
+ return;
+
+ case THUMB2_IMM16:
+ // MOVW <Rd>, #<const> i:imm3:imm8
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ Target |= ((OpCode32 >> 4) & 0xf0000);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rd], Target);
+ return;
+
+ case ADD_IMM5:
+ // ADC{S} <Rd>, <Rn>, <Rm> {,LSL #<const>} imm3:imm2
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm]);
+ if (Target != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
+ }
+
+ return;
+
+ case ADD_IMM5_2REG:
+ // CMP <Rn>, <Rm> {,LSL #<const>} imm3:imm2
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rn], gReg[Rm]);
+ if (Target != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ", LSL %d", gShiftType[(OpCode >> 5) & 3], Target);
+ }
+
+ case ASR_IMM5:
+ // ARS <Rd>, <Rm> #<const>} imm3:imm2
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ Target = ((OpCode32 >> 6) & 3) | ((OpCode32 >> 10) & 0x1c0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a #%d", gReg[Rd], gReg[Rm], Target);
+ return;
+
+ case ASR_3REG:
+ // ARS <Rd>, <Rn>, <Rm>
+ if ((OpCode32 & BIT20) == BIT20) {
+ Buf[Offset - 3] = 'S'; // assume %-6a
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a %a", gReg[Rd], gReg[Rn], gReg[Rm]);
+ return;
+
+ case ADR_THUMB2:
+ // ADDR <Rd>, <label>
+ Target = (OpCode32 & 0xff) | ((OpCode32 >> 8) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ if ((OpCode & (BIT23 | BIT21)) == (BIT23 | BIT21)) {
+ Target = PcAlign4 (Pc) - Target;
+ } else {
+ Target = PcAlign4 (Pc) + Target;
+ }
+
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, 0x%08x", gReg[Rd], Target);
+ return;
+
+ case CMN_THUMB2:
+ // CMN <Rn>, #<const>}
+ Target = (OpCode32 & 0xff) | ((OpCode >> 4) & 0x700) | ((OpCode & BIT26) == BIT26 ? BIT11 : 0);
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #0x%x", gReg[Rn], Target);
+ return;
+
+ case BFC_THUMB2:
+ // BFI <Rd>, <Rn>, #<lsb>, #<width>
+ MsBit = OpCode32 & 0x1f;
+ LsBit = ((OpCode32 >> 6) & 3) | ((OpCode >> 10) & 0x1c);
+ if ((Rn == 0xf) & (AsciiStrCmp (gOpThumb2[Index].Start, "BFC") == 0)) {
+ // BFC <Rd>, #<lsb>, #<width>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, #%d, #%d", gReg[Rd], LsBit, MsBit - LsBit + 1);
+ } else if (AsciiStrCmp (gOpThumb2[Index].Start, "BFI") == 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit - LsBit + 1);
+ } else {
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, #%d, #%d", gReg[Rd], gReg[Rn], LsBit, MsBit + 1);
+ }
+
+ return;
+
+ case CPD_THUMB2:
+ // <coproc>,<opc1>,<CRd>,<CRn>,<CRm>,<opc2>
+ Coproc = (OpCode32 >> 8) & 0xf;
+ Opc1 = (OpCode32 >> 20) & 0xf;
+ Opc2 = (OpCode32 >> 5) & 0x7;
+ CRd = (OpCode32 >> 12) & 0xf;
+ CRn = (OpCode32 >> 16) & 0xf;
+ CRm = OpCode32 & 0xf;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,c%d,c%d,c%d", Coproc, Opc1, CRd, CRn, CRm);
+ if (Opc2 != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
+ }
+
+ return;
+
+ case MRC_THUMB2:
+ // MRC <coproc>,<opc1>,<Rt>,<CRn>,<CRm>,<opc2>
+ Coproc = (OpCode32 >> 8) & 0xf;
+ Opc1 = (OpCode32 >> 20) & 0xf;
+ Opc2 = (OpCode32 >> 5) & 0x7;
+ CRn = (OpCode32 >> 16) & 0xf;
+ CRm = OpCode32 & 0xf;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,c%d,c%d", Coproc, Opc1, gReg[Rt], CRn, CRm);
+ if (Opc2 != 0) {
+ AsciiSPrint (&Buf[Offset], Size - Offset, ",#%d,", Opc2);
+ }
+
+ return;
+
+ case MRRC_THUMB2:
+ // MRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>,<opc2>
+ Coproc = (OpCode32 >> 8) & 0xf;
+ Opc1 = (OpCode32 >> 20) & 0xf;
+ CRn = (OpCode32 >> 16) & 0xf;
+ CRm = OpCode32 & 0xf;
+ Offset += AsciiSPrint (&Buf[Offset], Size - Offset, " p%d,#%d,%a,%a,c%d", Coproc, Opc1, gReg[Rt], gReg[Rt2], CRm);
+ return;
+
+ case THUMB2_2REGS:
+ // <Rd>, <Rm>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a", gReg[Rd], gReg[Rm]);
+ return;
+
+ case THUMB2_4REGS:
+ // <Rd>, <Rn>, <Rm>, <Ra>
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, %a, %a, %a", gReg[Rd], gReg[Rn], gReg[Rm], gReg[Rt]);
+ return;
+
+ case THUMB2_MRS:
+ // MRS <Rd>, CPSR
+ AsciiSPrint (&Buf[Offset], Size - Offset, " %a, CPSR", gReg[Rd]);
+ return;
+
+ case THUMB2_MSR:
+ // MRS CPSR_<fields>, <Rd>
+ Target = (OpCode32 >> 10) & 3;
+ AsciiSPrint (&Buf[Offset], Size - Offset, " CPSR_%a%a, %a", (Target & 2) == 0 ? "" : "f", (Target & 1) == 0 ? "" : "s", gReg[Rd]);
+ return;
+
+ case THUMB2_NO_ARGS:
+ default:
+ break;
}
}
}
@@ -1019,17 +1032,14 @@ DisassembleThumbInstruction ( AsciiSPrint (Buf, Size, "0x%08x", OpCode32);
}
-
-
VOID
DisassembleArmInstruction (
- IN UINT32 **OpCodePtr,
- OUT CHAR8 *Buf,
- OUT UINTN Size,
- IN BOOLEAN Extended
+ IN UINT32 **OpCodePtr,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size,
+ IN BOOLEAN Extended
);
-
/**
Place a disassembly of **OpCodePtr into buffer, and update OpCodePtr to
point to next instruction.
@@ -1047,12 +1057,12 @@ DisassembleArmInstruction ( **/
VOID
DisassembleInstruction (
- IN UINT8 **OpCodePtr,
- IN BOOLEAN Thumb,
- IN BOOLEAN Extended,
- IN OUT UINT32 *ItBlock,
- OUT CHAR8 *Buf,
- OUT UINTN Size
+ IN UINT8 **OpCodePtr,
+ IN BOOLEAN Thumb,
+ IN BOOLEAN Extended,
+ IN OUT UINT32 *ItBlock,
+ OUT CHAR8 *Buf,
+ OUT UINTN Size
)
{
if (Thumb) {
@@ -1061,4 +1071,3 @@ DisassembleInstruction ( DisassembleArmInstruction ((UINT32 **)OpCodePtr, Buf, Size, Extended);
}
}
-
diff --git a/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c b/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c index fcf3dd1644..ef6a132b8d 100644 --- a/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c +++ b/ArmPkg/Library/ArmExceptionLib/AArch64/AArch64Exception.c @@ -14,39 +14,39 @@ #include <Library/MemoryAllocationLib.h>
#include <Protocol/DebugSupport.h> // for MAX_AARCH64_EXCEPTION
-UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;
-EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
+UINTN gMaxExceptionNumber = MAX_AARCH64_EXCEPTION;
+EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_AARCH64_EXCEPTION + 1] = { 0 };
-PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
-UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
+PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
+UINTN gDebuggerNoHandlerValue = 0; // todo: define for AArch64
#define EL0_STACK_SIZE EFI_PAGES_TO_SIZE(2)
-STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
+STATIC UINTN mNewStackBase[EL0_STACK_SIZE / sizeof (UINTN)];
VOID
RegisterEl0Stack (
- IN VOID *Stack
+ IN VOID *Stack
);
RETURN_STATUS
ArchVectorConfig (
- IN UINTN VectorBaseAddress
+ IN UINTN VectorBaseAddress
)
{
- UINTN HcrReg;
+ UINTN HcrReg;
// Round down sp by 16 bytes alignment
RegisterEl0Stack (
(VOID *)(((UINTN)mNewStackBase + EL0_STACK_SIZE) & ~0xFUL)
);
- if (ArmReadCurrentEL() == AARCH64_EL2) {
- HcrReg = ArmReadHcr();
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ HcrReg = ArmReadHcr ();
// Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2
HcrReg |= ARM_HCR_TGE;
- ArmWriteHcr(HcrReg);
+ ArmWriteHcr (HcrReg);
}
return RETURN_SUCCESS;
diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c b/ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c index 40857c7f1f..fc411b845d 100644 --- a/ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c +++ b/ArmPkg/Library/ArmExceptionLib/Arm/ArmException.c @@ -17,28 +17,27 @@ #include <Protocol/DebugSupport.h> // for MAX_ARM_EXCEPTION
-UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;
-EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
+UINTN gMaxExceptionNumber = MAX_ARM_EXCEPTION;
+EFI_EXCEPTION_CALLBACK gExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1] = { 0 };
-PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
+PHYSICAL_ADDRESS gExceptionVectorAlignmentMask = ARM_VECTOR_TABLE_ALIGNMENT;
// Exception handler contains branch to vector location (jmp $) so no handler
// NOTE: This code assumes vectors are ARM and not Thumb code
-UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
+UINTN gDebuggerNoHandlerValue = 0xEAFFFFFE;
RETURN_STATUS
ArchVectorConfig (
- IN UINTN VectorBaseAddress
+ IN UINTN VectorBaseAddress
)
{
// if the vector address corresponds to high vectors
if (VectorBaseAddress == 0xFFFF0000) {
// set SCTLR.V to enable high vectors
- ArmSetHighVectors();
- }
- else {
+ ArmSetHighVectors ();
+ } else {
// Set SCTLR.V to 0 to enable VBAR to be used
- ArmSetLowVectors();
+ ArmSetLowVectors ();
}
return RETURN_SUCCESS;
diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c index 245e848e3f..1904816c16 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c +++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.c @@ -22,37 +22,38 @@ STATIC
RETURN_STATUS
-CopyExceptionHandlers(
- IN PHYSICAL_ADDRESS BaseAddress
+CopyExceptionHandlers (
+ IN PHYSICAL_ADDRESS BaseAddress
);
EFI_STATUS
EFIAPI
-RegisterExceptionHandler(
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+RegisterExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
);
VOID
-ExceptionHandlersStart(
+ExceptionHandlersStart (
VOID
);
VOID
-ExceptionHandlersEnd(
+ExceptionHandlersEnd (
VOID
);
-RETURN_STATUS ArchVectorConfig(
- IN UINTN VectorBaseAddress
+RETURN_STATUS
+ArchVectorConfig (
+ IN UINTN VectorBaseAddress
);
// these globals are provided by the architecture specific source (Arm or AArch64)
-extern UINTN gMaxExceptionNumber;
-extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];
-extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];
-extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;
-extern UINTN gDebuggerNoHandlerValue;
+extern UINTN gMaxExceptionNumber;
+extern EFI_EXCEPTION_CALLBACK gExceptionHandlers[];
+extern EFI_EXCEPTION_CALLBACK gDebuggerExceptionHandlers[];
+extern PHYSICAL_ADDRESS gExceptionVectorAlignmentMask;
+extern UINTN gDebuggerNoHandlerValue;
// A compiler flag adjusts the compilation of this library to a variant where
// the vectors are relocated (copied) to another location versus using the
@@ -60,13 +61,12 @@ extern UINTN gDebuggerNoHandlerValue; // address this at library build time. Since this affects the build of the
// library we cannot represent this in a PCD since PCDs are evaluated on
// a per-module basis.
-#if defined(ARM_RELOCATE_VECTORS)
-STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;
+#if defined (ARM_RELOCATE_VECTORS)
+STATIC CONST BOOLEAN gArmRelocateVectorTable = TRUE;
#else
-STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;
+STATIC CONST BOOLEAN gArmRelocateVectorTable = FALSE;
#endif
-
/**
Initializes all CPU exceptions entries and provides the default exception handlers.
@@ -85,23 +85,21 @@ with default exception handlers. **/
EFI_STATUS
EFIAPI
-InitializeCpuExceptionHandlers(
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+InitializeCpuExceptionHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
)
{
- RETURN_STATUS Status;
- UINTN VectorBase;
+ RETURN_STATUS Status;
+ UINTN VectorBase;
Status = EFI_SUCCESS;
// if we are requested to copy exception handlers to another location
if (gArmRelocateVectorTable) {
-
- VectorBase = PcdGet64(PcdCpuVectorBaseAddress);
- Status = CopyExceptionHandlers(VectorBase);
-
- }
- else { // use VBAR to point to where our exception handlers are
+ VectorBase = PcdGet64 (PcdCpuVectorBaseAddress);
+ Status = CopyExceptionHandlers (VectorBase);
+ } else {
+ // use VBAR to point to where our exception handlers are
// The vector table must be aligned for the architecture. If this
// assertion fails ensure the appropriate FFS alignment is in effect,
@@ -110,7 +108,7 @@ InitializeCpuExceptionHandlers( // for AArch64 Align=4K is required. Align=Auto can be used but this
// is known to cause an issue with populating the reset vector area
// for encapsulated FVs.
- ASSERT(((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);
+ ASSERT (((UINTN)ExceptionHandlersStart & gExceptionVectorAlignmentMask) == 0);
// We do not copy the Exception Table at PcdGet64(PcdCpuVectorBaseAddress). We just set Vector
// Base Address to point into CpuDxe code.
@@ -119,12 +117,12 @@ InitializeCpuExceptionHandlers( Status = RETURN_SUCCESS;
}
- if (!RETURN_ERROR(Status)) {
+ if (!RETURN_ERROR (Status)) {
// call the architecture-specific routine to prepare for the new vector
// configuration to take effect
- ArchVectorConfig(VectorBase);
+ ArchVectorConfig (VectorBase);
- ArmWriteVBar(VectorBase);
+ ArmWriteVBar (VectorBase);
}
return RETURN_SUCCESS;
@@ -148,14 +146,14 @@ with default exception handlers. **/
STATIC
RETURN_STATUS
-CopyExceptionHandlers(
- IN PHYSICAL_ADDRESS BaseAddress
+CopyExceptionHandlers (
+ IN PHYSICAL_ADDRESS BaseAddress
)
{
- RETURN_STATUS Status;
- UINTN Length;
- UINTN Index;
- UINT32 *VectorBase;
+ RETURN_STATUS Status;
+ UINTN Length;
+ UINTN Index;
+ UINT32 *VectorBase;
// ensure that the destination value specifies an address meeting the vector alignment requirements
ASSERT ((BaseAddress & gExceptionVectorAlignmentMask) == 0);
@@ -167,37 +165,35 @@ CopyExceptionHandlers( VectorBase = (UINT32 *)(UINTN)BaseAddress;
- if (FeaturePcdGet(PcdDebuggerExceptionSupport) == TRUE) {
+ if (FeaturePcdGet (PcdDebuggerExceptionSupport) == TRUE) {
// Save existing vector table, in case debugger is already hooked in
- CopyMem((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));
+ CopyMem ((VOID *)gDebuggerExceptionHandlers, (VOID *)VectorBase, sizeof (EFI_EXCEPTION_CALLBACK)* (gMaxExceptionNumber+1));
}
// Copy our assembly code into the page that contains the exception vectors.
- CopyMem((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
+ CopyMem ((VOID *)VectorBase, (VOID *)ExceptionHandlersStart, Length);
//
// Initialize the C entry points for interrupts
//
for (Index = 0; Index <= gMaxExceptionNumber; Index++) {
- if (!FeaturePcdGet(PcdDebuggerExceptionSupport) ||
- (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue)) {
-
- Status = RegisterExceptionHandler(Index, NULL);
- ASSERT_EFI_ERROR(Status);
- }
- else {
+ if (!FeaturePcdGet (PcdDebuggerExceptionSupport) ||
+ (gDebuggerExceptionHandlers[Index] == 0) || (gDebuggerExceptionHandlers[Index] == (VOID *)gDebuggerNoHandlerValue))
+ {
+ Status = RegisterExceptionHandler (Index, NULL);
+ ASSERT_EFI_ERROR (Status);
+ } else {
// If the debugger has already hooked put its vector back
VectorBase[Index] = (UINT32)(UINTN)gDebuggerExceptionHandlers[Index];
}
}
// Flush Caches since we updated executable stuff
- InvalidateInstructionCacheRange((VOID *)(UINTN)BaseAddress, Length);
+ InvalidateInstructionCacheRange ((VOID *)(UINTN)BaseAddress, Length);
return RETURN_SUCCESS;
}
-
/**
Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.
@@ -216,9 +212,9 @@ with default interrupt/exception handlers. **/
EFI_STATUS
EFIAPI
-InitializeCpuInterruptHandlers(
-IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
-)
+InitializeCpuInterruptHandlers (
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL
+ )
{
// not needed, this is what the CPU driver is for
return EFI_UNSUPPORTED;
@@ -250,9 +246,9 @@ previously installed. or this function is not supported.
**/
RETURN_STATUS
-RegisterCpuInterruptHandler(
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
+RegisterCpuInterruptHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_CPU_INTERRUPT_HANDLER ExceptionHandler
)
{
if (ExceptionType > gMaxExceptionNumber) {
@@ -287,19 +283,19 @@ If this parameter is NULL, then the handler will be uninstalled. **/
EFI_STATUS
EFIAPI
-RegisterExceptionHandler(
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
+RegisterExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler
)
{
- return RegisterCpuInterruptHandler(ExceptionType, InterruptHandler);
+ return RegisterCpuInterruptHandler (ExceptionType, InterruptHandler);
}
VOID
EFIAPI
-CommonCExceptionHandler(
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+CommonCExceptionHandler (
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
if (ExceptionType <= gMaxExceptionNumber) {
@@ -307,13 +303,12 @@ CommonCExceptionHandler( gExceptionHandlers[ExceptionType](ExceptionType, SystemContext);
return;
}
- }
- else {
- DEBUG((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType));
- ASSERT(FALSE);
+ } else {
+ DEBUG ((DEBUG_ERROR, "Unknown exception type %d\n", ExceptionType));
+ ASSERT (FALSE);
}
- DefaultExceptionHandler(ExceptionType, SystemContext);
+ DefaultExceptionHandler (ExceptionType, SystemContext);
}
/**
@@ -341,8 +336,8 @@ CommonCExceptionHandler( EFI_STATUS
EFIAPI
InitializeCpuExceptionHandlersEx (
- IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
- IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
+ IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL,
+ IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL
)
{
return InitializeCpuExceptionHandlers (VectorInfo);
diff --git a/ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c b/ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c index a65113fada..fbbecdc528 100644 --- a/ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c +++ b/ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.c @@ -16,9 +16,9 @@ ArmGenericTimerEnableTimer ( VOID
)
{
- UINTN TimerCtrlReg;
+ UINTN TimerCtrlReg;
- TimerCtrlReg = ArmReadCntpCtl ();
+ TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmWriteCntpCtl (TimerCtrlReg);
}
@@ -37,9 +37,9 @@ ArmGenericTimerDisableTimer ( VOID
)
{
- UINTN TimerCtrlReg;
+ UINTN TimerCtrlReg;
- TimerCtrlReg = ArmReadCntpCtl ();
+ TimerCtrlReg = ArmReadCntpCtl ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmWriteCntpCtl (TimerCtrlReg);
}
@@ -71,11 +71,10 @@ ArmGenericTimerGetTimerVal ( return ArmReadCntpTval ();
}
-
VOID
EFIAPI
ArmGenericTimerSetTimerVal (
- IN UINTN Value
+ IN UINTN Value
)
{
ArmWriteCntpTval (Value);
@@ -102,7 +101,7 @@ ArmGenericTimerGetTimerCtrlReg ( VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
- UINTN Value
+ UINTN Value
)
{
ArmWriteCntpCtl (Value);
@@ -120,7 +119,7 @@ ArmGenericTimerGetCompareVal ( VOID
EFIAPI
ArmGenericTimerSetCompareVal (
- IN UINT64 Value
+ IN UINT64 Value
)
{
ArmWriteCntpCval (Value);
diff --git a/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c b/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c index 74c85dd756..893125a111 100644 --- a/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c +++ b/ArmPkg/Library/ArmGenericTimerVirtCounterLib/ArmGenericTimerVirtCounterLib.c @@ -16,9 +16,9 @@ ArmGenericTimerEnableTimer ( VOID
)
{
- UINTN TimerCtrlReg;
+ UINTN TimerCtrlReg;
- TimerCtrlReg = ArmReadCntvCtl ();
+ TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg |= ARM_ARCH_TIMER_ENABLE;
ArmWriteCntvCtl (TimerCtrlReg);
}
@@ -37,9 +37,9 @@ ArmGenericTimerDisableTimer ( VOID
)
{
- UINTN TimerCtrlReg;
+ UINTN TimerCtrlReg;
- TimerCtrlReg = ArmReadCntvCtl ();
+ TimerCtrlReg = ArmReadCntvCtl ();
TimerCtrlReg &= ~ARM_ARCH_TIMER_ENABLE;
ArmWriteCntvCtl (TimerCtrlReg);
}
@@ -71,11 +71,10 @@ ArmGenericTimerGetTimerVal ( return ArmReadCntvTval ();
}
-
VOID
EFIAPI
ArmGenericTimerSetTimerVal (
- IN UINTN Value
+ IN UINTN Value
)
{
ArmWriteCntvTval (Value);
@@ -102,7 +101,7 @@ ArmGenericTimerGetTimerCtrlReg ( VOID
EFIAPI
ArmGenericTimerSetTimerCtrlReg (
- UINTN Value
+ UINTN Value
)
{
ArmWriteCntvCtl (Value);
@@ -120,7 +119,7 @@ ArmGenericTimerGetCompareVal ( VOID
EFIAPI
ArmGenericTimerSetCompareVal (
- IN UINT64 Value
+ IN UINT64 Value
)
{
ArmWriteCntvCval (Value);
diff --git a/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c b/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c index 6fd69658e0..f017eb5c47 100644 --- a/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.c @@ -9,7 +9,7 @@ #include <Library/ArmLib.h>
#include <Library/ArmGicLib.h>
-STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
+STATIC ARM_GIC_ARCH_REVISION mGicArchRevision;
RETURN_STATUS
EFIAPI
@@ -17,7 +17,7 @@ ArmGicArchLibInitialize ( VOID
)
{
- UINT32 IccSre;
+ UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
@@ -38,6 +38,7 @@ ArmGicArchLibInitialize ( ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
+
if (IccSre & ICC_SRE_EL2_SRE) {
mGicArchRevision = ARM_GIC_ARCH_REVISION_3;
goto Done;
diff --git a/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c b/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c index ca81951b2b..3c791a245c 100644 --- a/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c +++ b/ArmPkg/Library/ArmGicArchSecLib/ArmGicArchLib.c @@ -15,7 +15,7 @@ ArmGicGetSupportedArchRevision ( VOID
)
{
- UINT32 IccSre;
+ UINT32 IccSre;
// Ideally we would like to use the GICC IIDR Architecture version here, but
// this does not seem to be very reliable as the implementation could easily
@@ -36,6 +36,7 @@ ArmGicGetSupportedArchRevision ( ArmGicV3SetControlSystemRegisterEnable (IccSre | ICC_SRE_EL2_SRE);
IccSre = ArmGicV3GetControlSystemRegisterEnable ();
}
+
if (IccSre & ICC_SRE_EL2_SRE) {
return ARM_GIC_ARCH_REVISION_3;
}
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c index 191a5fea31..7ab28e3e05 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c @@ -23,10 +23,10 @@ AArch64DataCacheOperation ( IN AARCH64_CACHE_OPERATION DataCacheOperation
)
{
- UINTN SavedInterruptState;
+ UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
- ArmDisableInterrupts();
+ ArmDisableInterrupts ();
AArch64AllDataCachesOperation (DataCacheOperation);
@@ -99,7 +99,7 @@ ArmHasCcidx ( VOID
)
{
- UINTN Mmfr2;
+ UINTN Mmfr2;
Mmfr2 = ArmReadIdAA64Mmfr2 ();
return (((Mmfr2 >> 20) & 0xF) == 1) ? TRUE : FALSE;
diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h index 318020277b..330481fc50 100644 --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h @@ -11,7 +11,9 @@ #ifndef AARCH64_LIB_H_
#define AARCH64_LIB_H_
-typedef VOID (*AARCH64_CACHE_OPERATION)(UINTN);
+typedef VOID (*AARCH64_CACHE_OPERATION)(
+ UINTN
+ );
VOID
AArch64AllDataCachesOperation (
@@ -33,7 +35,7 @@ ArmCleanDataCacheEntryBySetWay ( VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryBySetWay (
- IN UINTN SetWayFormat
+ IN UINTN SetWayFormat
);
UINTN
@@ -53,4 +55,3 @@ ArmReadIdAA64Mmfr2 ( );
#endif // AARCH64_LIB_H_
-
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c index c5dd3f8b2f..521d5be0de 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c @@ -23,7 +23,7 @@ ArmV7DataCacheOperation ( IN ARM_V7_CACHE_OPERATION DataCacheOperation
)
{
- UINTN SavedInterruptState;
+ UINTN SavedInterruptState;
SavedInterruptState = ArmGetInterruptState ();
ArmDisableInterrupts ();
@@ -114,7 +114,7 @@ ArmHasCcidx ( VOID
)
{
- UINTN Mmfr4;
+ UINTN Mmfr4;
Mmfr4 = ArmReadIdMmfr4 ();
return (((Mmfr4 >> 24) & 0xF) == 1) ? TRUE : FALSE;
diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h index 5a92ade2b3..404ff92c4e 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h @@ -9,21 +9,23 @@ #ifndef ARM_V7_LIB_H_
#define ARM_V7_LIB_H_
-#define ID_MMFR0_SHARELVL_SHIFT 12
-#define ID_MMFR0_SHARELVL_MASK 0xf
-#define ID_MMFR0_SHARELVL_ONE 0
-#define ID_MMFR0_SHARELVL_TWO 1
-
-#define ID_MMFR0_INNERSHR_SHIFT 28
-#define ID_MMFR0_INNERSHR_MASK 0xf
-#define ID_MMFR0_OUTERSHR_SHIFT 8
-#define ID_MMFR0_OUTERSHR_MASK 0xf
-
-#define ID_MMFR0_SHR_IMP_UNCACHED 0
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
-#define ID_MMFR0_SHR_IGNORED 0xf
-
-typedef VOID (*ARM_V7_CACHE_OPERATION)(UINT32);
+#define ID_MMFR0_SHARELVL_SHIFT 12
+#define ID_MMFR0_SHARELVL_MASK 0xf
+#define ID_MMFR0_SHARELVL_ONE 0
+#define ID_MMFR0_SHARELVL_TWO 1
+
+#define ID_MMFR0_INNERSHR_SHIFT 28
+#define ID_MMFR0_INNERSHR_MASK 0xf
+#define ID_MMFR0_OUTERSHR_SHIFT 8
+#define ID_MMFR0_OUTERSHR_MASK 0xf
+
+#define ID_MMFR0_SHR_IMP_UNCACHED 0
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
+#define ID_MMFR0_SHR_IGNORED 0xf
+
+typedef VOID (*ARM_V7_CACHE_OPERATION)(
+ UINT32
+ );
VOID
ArmV7AllDataCachesOperation (
@@ -45,7 +47,7 @@ ArmCleanDataCacheEntryBySetWay ( VOID
EFIAPI
ArmCleanInvalidateDataCacheEntryBySetWay (
- IN UINTN SetWayFormat
+ IN UINTN SetWayFormat
);
/** Reads the ID_MMFR4 register.
@@ -65,4 +67,3 @@ ArmReadIdPfr1 ( );
#endif // ARM_V7_LIB_H_
-
diff --git a/ArmPkg/Library/ArmLib/ArmLib.c b/ArmPkg/Library/ArmLib/ArmLib.c index c8622f1794..30849564fc 100644 --- a/ArmPkg/Library/ArmLib/ArmLib.c +++ b/ArmPkg/Library/ArmLib/ArmLib.c @@ -16,19 +16,19 @@ VOID
EFIAPI
ArmSetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
)
{
- ArmWriteAuxCr(ArmReadAuxCr() | Bits);
+ ArmWriteAuxCr (ArmReadAuxCr () | Bits);
}
VOID
EFIAPI
ArmUnsetAuxCrBit (
- IN UINT32 Bits
+ IN UINT32 Bits
)
{
- ArmWriteAuxCr(ArmReadAuxCr() & ~Bits);
+ ArmWriteAuxCr (ArmReadAuxCr () & ~Bits);
}
//
@@ -38,7 +38,7 @@ ArmUnsetAuxCrBit ( VOID
EFIAPI
ArmSetCpuActlrBit (
- IN UINTN Bits
+ IN UINTN Bits
)
{
ArmWriteCpuActlr (ArmReadCpuActlr () | Bits);
@@ -47,7 +47,7 @@ ArmSetCpuActlrBit ( VOID
EFIAPI
ArmUnsetCpuActlrBit (
- IN UINTN Bits
+ IN UINTN Bits
)
{
ArmWriteCpuActlr (ArmReadCpuActlr () & ~Bits);
@@ -77,7 +77,7 @@ ArmCacheWritebackGranule ( VOID
)
{
- UINTN CWG;
+ UINTN CWG;
CWG = (ArmCacheInfo () >> 24) & 0xf; // CTR_EL0.CWG
diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h index 668aefd6a0..7fb27068ce 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -11,19 +11,19 @@ #ifndef ARM_LIB_PRIVATE_H_
#define ARM_LIB_PRIVATE_H_
-#define CACHE_SIZE_4_KB (3UL)
-#define CACHE_SIZE_8_KB (4UL)
-#define CACHE_SIZE_16_KB (5UL)
-#define CACHE_SIZE_32_KB (6UL)
-#define CACHE_SIZE_64_KB (7UL)
-#define CACHE_SIZE_128_KB (8UL)
+#define CACHE_SIZE_4_KB (3UL)
+#define CACHE_SIZE_8_KB (4UL)
+#define CACHE_SIZE_16_KB (5UL)
+#define CACHE_SIZE_32_KB (6UL)
+#define CACHE_SIZE_64_KB (7UL)
+#define CACHE_SIZE_128_KB (8UL)
#define CACHE_ASSOCIATIVITY_DIRECT (0UL)
#define CACHE_ASSOCIATIVITY_4_WAY (2UL)
#define CACHE_ASSOCIATIVITY_8_WAY (3UL)
-#define CACHE_PRESENT (0UL)
-#define CACHE_NOT_PRESENT (1UL)
+#define CACHE_PRESENT (0UL)
+#define CACHE_NOT_PRESENT (1UL)
#define CACHE_LINE_LENGTH_32_BYTES (2UL)
@@ -32,25 +32,25 @@ #define SIZE_FIELD_TO_CACHE_PRESENCE(x) (((x) >> 2) & 0x01)
#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x) (((x) >> 0) & 0x03)
-#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
-#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
+#define DATA_CACHE_SIZE_FIELD(x) (((x) >> 12) & 0x0FFF)
+#define INSTRUCTION_CACHE_SIZE_FIELD(x) (((x) >> 0) & 0x0FFF)
-#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
-#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))
+#define DATA_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_SIZE(x) (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_ASSOCIATIVITY(x) (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_PRESENT(x) (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))
+#define INSTRUCTION_CACHE_LINE_LENGTH(x) (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))
-#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
-#define CACHE_TYPE_WRITE_BACK (0x0EUL)
+#define CACHE_TYPE(x) (((x) >> 25) & 0x0F)
+#define CACHE_TYPE_WRITE_BACK (0x0EUL)
-#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
-#define CACHE_ARCHITECTURE_UNIFIED (0UL)
-#define CACHE_ARCHITECTURE_SEPARATE (1UL)
+#define CACHE_ARCHITECTURE(x) (((x) >> 24) & 0x01)
+#define CACHE_ARCHITECTURE_UNIFIED (0UL)
+#define CACHE_ARCHITECTURE_SEPARATE (1UL)
VOID
CPSRMaskInsert (
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 8c736d25bb..89da40fd8e 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -26,31 +26,32 @@ ArmMemoryAttributeToPageAttribute ( )
{
switch (Attributes) {
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
- return TT_ATTR_INDX_MEMORY_WRITE_BACK;
-
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
- return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
-
- case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
- return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
-
- // Uncached and device mappings are treated as outer shareable by default,
- case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
- return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
-
- default:
- ASSERT (0);
- case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
- case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
- if (ArmReadCurrentEL () == AARCH64_EL2)
- return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
- else
- return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK;
+
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
+ return TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+
+ case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
+ return TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+
+ // Uncached and device mappings are treated as outer shareable by default,
+ case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
+ return TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+
+ default:
+ ASSERT (0);
+ case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
+ case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
+ if (ArmReadCurrentEL () == AARCH64_EL2) {
+ return TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK;
+ } else {
+ return TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK;
+ }
}
}
@@ -61,7 +62,7 @@ ArmMemoryAttributeToPageAttribute ( STATIC
UINTN
GetRootTableEntryCount (
- IN UINTN T0SZ
+ IN UINTN T0SZ
)
{
return TT_ENTRY_COUNT >> (T0SZ - MIN_T0SZ) % BITS_PER_LEVEL;
@@ -70,7 +71,7 @@ GetRootTableEntryCount ( STATIC
UINTN
GetRootTableLevel (
- IN UINTN T0SZ
+ IN UINTN T0SZ
)
{
return (T0SZ - MIN_T0SZ) / BITS_PER_LEVEL;
@@ -79,10 +80,10 @@ GetRootTableLevel ( STATIC
VOID
ReplaceTableEntry (
- IN UINT64 *Entry,
- IN UINT64 Value,
- IN UINT64 RegionStart,
- IN BOOLEAN IsLiveBlockMapping
+ IN UINT64 *Entry,
+ IN UINT64 Value,
+ IN UINT64 RegionStart,
+ IN BOOLEAN IsLiveBlockMapping
)
{
if (!ArmMmuEnabled () || !IsLiveBlockMapping) {
@@ -100,19 +101,22 @@ FreePageTablesRecursive ( IN UINTN Level
)
{
- UINTN Index;
+ UINTN Index;
ASSERT (Level <= 3);
if (Level < 3) {
for (Index = 0; Index < TT_ENTRY_COUNT; Index++) {
if ((TranslationTable[Index] & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY) {
- FreePageTablesRecursive ((VOID *)(UINTN)(TranslationTable[Index] &
- TT_ADDRESS_MASK_BLOCK_ENTRY),
- Level + 1);
+ FreePageTablesRecursive (
+ (VOID *)(UINTN)(TranslationTable[Index] &
+ TT_ADDRESS_MASK_BLOCK_ENTRY),
+ Level + 1
+ );
}
}
}
+
FreePages (TranslationTable, 1);
}
@@ -126,6 +130,7 @@ IsBlockEntry ( if (Level == 3) {
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY_LEVEL3;
}
+
return (Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY;
}
@@ -143,39 +148,48 @@ IsTableEntry ( //
return FALSE;
}
+
return (Entry & TT_TYPE_MASK) == TT_TYPE_TABLE_ENTRY;
}
STATIC
EFI_STATUS
UpdateRegionMappingRecursive (
- IN UINT64 RegionStart,
- IN UINT64 RegionEnd,
- IN UINT64 AttributeSetMask,
- IN UINT64 AttributeClearMask,
- IN UINT64 *PageTable,
- IN UINTN Level
+ IN UINT64 RegionStart,
+ IN UINT64 RegionEnd,
+ IN UINT64 AttributeSetMask,
+ IN UINT64 AttributeClearMask,
+ IN UINT64 *PageTable,
+ IN UINTN Level
)
{
- UINTN BlockShift;
- UINT64 BlockMask;
- UINT64 BlockEnd;
- UINT64 *Entry;
- UINT64 EntryValue;
- VOID *TranslationTable;
- EFI_STATUS Status;
+ UINTN BlockShift;
+ UINT64 BlockMask;
+ UINT64 BlockEnd;
+ UINT64 *Entry;
+ UINT64 EntryValue;
+ VOID *TranslationTable;
+ EFI_STATUS Status;
ASSERT (((RegionStart | RegionEnd) & EFI_PAGE_MASK) == 0);
BlockShift = (Level + 1) * BITS_PER_LEVEL + MIN_T0SZ;
- BlockMask = MAX_UINT64 >> BlockShift;
-
- DEBUG ((DEBUG_VERBOSE, "%a(%d): %llx - %llx set %lx clr %lx\n", __FUNCTION__,
- Level, RegionStart, RegionEnd, AttributeSetMask, AttributeClearMask));
-
- for (; RegionStart < RegionEnd; RegionStart = BlockEnd) {
+ BlockMask = MAX_UINT64 >> BlockShift;
+
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a(%d): %llx - %llx set %lx clr %lx\n",
+ __FUNCTION__,
+ Level,
+ RegionStart,
+ RegionEnd,
+ AttributeSetMask,
+ AttributeClearMask
+ ));
+
+ for ( ; RegionStart < RegionEnd; RegionStart = BlockEnd) {
BlockEnd = MIN (RegionEnd, (RegionStart | BlockMask) + 1);
- Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];
+ Entry = &PageTable[(RegionStart >> (64 - BlockShift)) & (TT_ENTRY_COUNT - 1)];
//
// If RegionStart or BlockEnd is not aligned to the block size at this
@@ -187,8 +201,9 @@ UpdateRegionMappingRecursive ( // we cannot replace it with a block entry without potentially losing
// attribute information, so keep the table entry in that case.
//
- if (Level == 0 || ((RegionStart | BlockEnd) & BlockMask) != 0 ||
- (IsTableEntry (*Entry, Level) && AttributeClearMask != 0)) {
+ if ((Level == 0) || (((RegionStart | BlockEnd) & BlockMask) != 0) ||
+ (IsTableEntry (*Entry, Level) && (AttributeClearMask != 0)))
+ {
ASSERT (Level < 3);
if (!IsTableEntry (*Entry, Level)) {
@@ -216,9 +231,14 @@ UpdateRegionMappingRecursive ( // We are splitting an existing block entry, so we have to populate
// the new table with the attributes of the block entry it replaces.
//
- Status = UpdateRegionMappingRecursive (RegionStart & ~BlockMask,
- (RegionStart | BlockMask) + 1, *Entry & TT_ATTRIBUTES_MASK,
- 0, TranslationTable, Level + 1);
+ Status = UpdateRegionMappingRecursive (
+ RegionStart & ~BlockMask,
+ (RegionStart | BlockMask) + 1,
+ *Entry & TT_ATTRIBUTES_MASK,
+ 0,
+ TranslationTable,
+ Level + 1
+ );
if (EFI_ERROR (Status)) {
//
// The range we passed to UpdateRegionMappingRecursive () is block
@@ -236,9 +256,14 @@ UpdateRegionMappingRecursive ( //
// Recurse to the next level
//
- Status = UpdateRegionMappingRecursive (RegionStart, BlockEnd,
- AttributeSetMask, AttributeClearMask, TranslationTable,
- Level + 1);
+ Status = UpdateRegionMappingRecursive (
+ RegionStart,
+ BlockEnd,
+ AttributeSetMask,
+ AttributeClearMask,
+ TranslationTable,
+ Level + 1
+ );
if (EFI_ERROR (Status)) {
if (!IsTableEntry (*Entry, Level)) {
//
@@ -250,16 +275,21 @@ UpdateRegionMappingRecursive ( //
FreePageTablesRecursive (TranslationTable, Level + 1);
}
+
return Status;
}
if (!IsTableEntry (*Entry, Level)) {
EntryValue = (UINTN)TranslationTable | TT_TYPE_TABLE_ENTRY;
- ReplaceTableEntry (Entry, EntryValue, RegionStart,
- IsBlockEntry (*Entry, Level));
+ ReplaceTableEntry (
+ Entry,
+ EntryValue,
+ RegionStart,
+ IsBlockEntry (*Entry, Level)
+ );
}
} else {
- EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
+ EntryValue = (*Entry & AttributeClearMask) | AttributeSetMask;
EntryValue |= RegionStart;
EntryValue |= (Level == 3) ? TT_TYPE_BLOCK_ENTRY_LEVEL3
: TT_TYPE_BLOCK_ENTRY;
@@ -280,6 +310,7 @@ UpdateRegionMappingRecursive ( }
}
}
+
return EFI_SUCCESS;
}
@@ -292,7 +323,7 @@ UpdateRegionMapping ( IN UINT64 AttributeClearMask
)
{
- UINTN T0SZ;
+ UINTN T0SZ;
if (((RegionStart | RegionLength) & EFI_PAGE_MASK) != 0) {
return EFI_INVALID_PARAMETER;
@@ -300,9 +331,14 @@ UpdateRegionMapping ( T0SZ = ArmGetTCR () & TCR_T0SZ_MASK;
- return UpdateRegionMappingRecursive (RegionStart, RegionStart + RegionLength,
- AttributeSetMask, AttributeClearMask, ArmGetTTBR0BaseAddress (),
- GetRootTableLevel (T0SZ));
+ return UpdateRegionMappingRecursive (
+ RegionStart,
+ RegionStart + RegionLength,
+ AttributeSetMask,
+ AttributeClearMask,
+ ArmGetTTBR0BaseAddress (),
+ GetRootTableLevel (T0SZ)
+ );
}
STATIC
@@ -323,31 +359,32 @@ FillTranslationTable ( STATIC
UINT64
GcdAttributeToPageAttribute (
- IN UINT64 GcdAttributes
+ IN UINT64 GcdAttributes
)
{
- UINT64 PageAttributes;
+ UINT64 PageAttributes;
switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) {
- case EFI_MEMORY_UC:
- PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
- break;
- case EFI_MEMORY_WC:
- PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
- break;
- case EFI_MEMORY_WT:
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
- break;
- case EFI_MEMORY_WB:
- PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
- break;
- default:
- PageAttributes = TT_ATTR_INDX_MASK;
- break;
+ case EFI_MEMORY_UC:
+ PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY;
+ break;
+ case EFI_MEMORY_WC:
+ PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE;
+ break;
+ case EFI_MEMORY_WT:
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE;
+ break;
+ case EFI_MEMORY_WB:
+ PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE;
+ break;
+ default:
+ PageAttributes = TT_ATTR_INDX_MASK;
+ break;
}
- if ((GcdAttributes & EFI_MEMORY_XP) != 0 ||
- (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) {
+ if (((GcdAttributes & EFI_MEMORY_XP) != 0) ||
+ ((GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC))
+ {
if (ArmReadCurrentEL () == AARCH64_EL2) {
PageAttributes |= TT_XN_MASK;
} else {
@@ -364,15 +401,15 @@ GcdAttributeToPageAttribute ( EFI_STATUS
ArmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
- UINT64 PageAttributes;
- UINT64 PageAttributeMask;
+ UINT64 PageAttributes;
+ UINT64 PageAttributeMask;
- PageAttributes = GcdAttributeToPageAttribute (Attributes);
+ PageAttributes = GcdAttributeToPageAttribute (Attributes);
PageAttributeMask = 0;
if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) {
@@ -380,22 +417,26 @@ ArmSetMemoryAttributes ( // No memory type was set in Attributes, so we are going to update the
// permissions only.
//
- PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
+ PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK;
PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK |
TT_PXN_MASK | TT_XN_MASK);
}
- return UpdateRegionMapping (BaseAddress, Length, PageAttributes,
- PageAttributeMask);
+ return UpdateRegionMapping (
+ BaseAddress,
+ Length,
+ PageAttributes,
+ PageAttributeMask
+ );
}
STATIC
EFI_STATUS
SetMemoryRegionAttribute (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- IN UINT64 BlockEntryMask
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ IN UINT64 BlockEntryMask
)
{
return UpdateRegionMapping (BaseAddress, Length, Attributes, BlockEntryMask);
@@ -403,11 +444,11 @@ SetMemoryRegionAttribute ( EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- UINT64 Val;
+ UINT64 Val;
if (ArmReadCurrentEL () == AARCH64_EL1) {
Val = TT_PXN_MASK | TT_UXN_MASK;
@@ -419,16 +460,17 @@ ArmSetMemoryRegionNoExec ( BaseAddress,
Length,
Val,
- ~TT_ADDRESS_MASK_BLOCK_ENTRY);
+ ~TT_ADDRESS_MASK_BLOCK_ENTRY
+ );
}
EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- UINT64 Mask;
+ UINT64 Mask;
// XN maps to UXN in the EL1&0 translation regime
Mask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_PXN_MASK | TT_XN_MASK);
@@ -437,50 +479,53 @@ ArmClearMemoryRegionNoExec ( BaseAddress,
Length,
0,
- Mask);
+ Mask
+ );
}
EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return SetMemoryRegionAttribute (
BaseAddress,
Length,
TT_AP_RO_RO,
- ~TT_ADDRESS_MASK_BLOCK_ENTRY);
+ ~TT_ADDRESS_MASK_BLOCK_ENTRY
+ );
}
EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return SetMemoryRegionAttribute (
BaseAddress,
Length,
TT_AP_RW_RW,
- ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK));
+ ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK)
+ );
}
EFI_STATUS
EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
+ OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
- VOID* TranslationTable;
- UINTN MaxAddressBits;
- UINT64 MaxAddress;
- UINTN T0SZ;
- UINTN RootTableEntryCount;
- UINT64 TCR;
- EFI_STATUS Status;
+ VOID *TranslationTable;
+ UINTN MaxAddressBits;
+ UINT64 MaxAddress;
+ UINTN T0SZ;
+ UINTN RootTableEntryCount;
+ UINT64 TCR;
+ EFI_STATUS Status;
if (MemoryTable == NULL) {
ASSERT (MemoryTable != NULL);
@@ -495,9 +540,9 @@ ArmConfigureMmu ( // use of 4 KB pages.
//
MaxAddressBits = MIN (ArmGetPhysicalAddressBits (), MAX_VA_BITS);
- MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;
+ MaxAddress = LShiftU64 (1ULL, MaxAddressBits) - 1;
- T0SZ = 64 - MaxAddressBits;
+ T0SZ = 64 - MaxAddressBits;
RootTableEntryCount = GetRootTableEntryCount (T0SZ);
//
@@ -506,7 +551,7 @@ ArmConfigureMmu ( // Ideally we will be running at EL2, but should support EL1 as well.
// UEFI should not run at EL3.
if (ArmReadCurrentEL () == AARCH64_EL2) {
- //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
+ // Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
TCR = T0SZ | (1UL << 31) | (1UL << 23) | TCR_TG0_4KB;
// Set the Physical Address Size using MaxAddress
@@ -523,9 +568,11 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_PS_256TB;
} else {
- DEBUG ((DEBUG_ERROR,
+ DEBUG ((
+ DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
- MaxAddress));
+ MaxAddress
+ ));
ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED;
}
@@ -547,9 +594,11 @@ ArmConfigureMmu ( } else if (MaxAddress < SIZE_256TB) {
TCR |= TCR_IPS_256TB;
} else {
- DEBUG ((DEBUG_ERROR,
+ DEBUG ((
+ DEBUG_ERROR,
"ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n",
- MaxAddress));
+ MaxAddress
+ ));
ASSERT (0); // Bigger than 48-bit memory space are not supported
return EFI_UNSUPPORTED;
}
@@ -579,6 +628,7 @@ ArmConfigureMmu ( if (TranslationTable == NULL) {
return EFI_OUT_OF_RESOURCES;
}
+
//
// We set TTBR0 just after allocating the table to retrieve its location from
// the subsequent functions without needing to pass this value across the
@@ -599,8 +649,10 @@ ArmConfigureMmu ( // Make sure we are not inadvertently hitting in the caches
// when populating the page tables.
//
- InvalidateDataCacheRange (TranslationTable,
- RootTableEntryCount * sizeof (UINT64));
+ InvalidateDataCacheRange (
+ TranslationTable,
+ RootTableEntryCount * sizeof (UINT64)
+ );
ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));
while (MemoryTable->Length != 0) {
@@ -608,6 +660,7 @@ ArmConfigureMmu ( if (EFI_ERROR (Status)) {
goto FreeTranslationTable;
}
+
MemoryTable++;
}
@@ -618,10 +671,10 @@ ArmConfigureMmu ( // EFI_MEMORY_WB ==> MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
//
ArmSetMAIR (
- MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |
+ MAIR_ATTR (TT_ATTR_INDX_DEVICE_MEMORY, MAIR_ATTR_DEVICE_MEMORY) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_NON_CACHEABLE, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE) |
MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_THROUGH, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH) |
- MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
+ MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK)
);
ArmDisableAlignmentCheck ();
@@ -643,14 +696,16 @@ ArmMmuBaseLibConstructor ( VOID
)
{
- extern UINT32 ArmReplaceLiveTranslationEntrySize;
+ extern UINT32 ArmReplaceLiveTranslationEntrySize;
//
// The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC
//
- WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
- ArmReplaceLiveTranslationEntrySize);
+ WriteBackDataCacheRange (
+ (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
+ ArmReplaceLiveTranslationEntrySize
+ );
return RETURN_SUCCESS;
}
diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c index 843b5d2781..caace2c17c 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuPeiLibConstructor.c @@ -16,14 +16,14 @@ EFI_STATUS
EFIAPI
ArmMmuPeiLibConstructor (
- IN EFI_PEI_FILE_HANDLE FileHandle,
- IN CONST EFI_PEI_SERVICES **PeiServices
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- extern UINT32 ArmReplaceLiveTranslationEntrySize;
+ extern UINT32 ArmReplaceLiveTranslationEntrySize;
- EFI_FV_FILE_INFO FileInfo;
- EFI_STATUS Status;
+ EFI_FV_FILE_INFO FileInfo;
+ EFI_STATUS Status;
ASSERT (FileHandle != NULL);
@@ -37,9 +37,10 @@ ArmMmuPeiLibConstructor ( // is executing from DRAM, we only need to perform the cache maintenance
// when not executing in place.
//
- if ((UINTN)FileInfo.Buffer <= (UINTN)ArmReplaceLiveTranslationEntry &&
+ if (((UINTN)FileInfo.Buffer <= (UINTN)ArmReplaceLiveTranslationEntry) &&
((UINTN)FileInfo.Buffer + FileInfo.BufferSize >=
- (UINTN)ArmReplaceLiveTranslationEntry + ArmReplaceLiveTranslationEntrySize)) {
+ (UINTN)ArmReplaceLiveTranslationEntry + ArmReplaceLiveTranslationEntrySize))
+ {
DEBUG ((DEBUG_INFO, "ArmMmuLib: skipping cache maintenance on XIP PEIM\n"));
} else {
DEBUG ((DEBUG_INFO, "ArmMmuLib: performing cache maintenance on shadowed PEIM\n"));
@@ -47,8 +48,10 @@ ArmMmuPeiLibConstructor ( // The ArmReplaceLiveTranslationEntry () helper function may be invoked
// with the MMU off so we have to ensure that it gets cleaned to the PoC
//
- WriteBackDataCacheRange ((VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
- ArmReplaceLiveTranslationEntrySize);
+ WriteBackDataCacheRange (
+ (VOID *)(UINTN)ArmReplaceLiveTranslationEntry,
+ ArmReplaceLiveTranslationEntrySize
+ );
}
return RETURN_SUCCESS;
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c index e3b02a9fba..bee8ad7028 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibConvert.c @@ -19,9 +19,9 @@ ConvertSectionAttributesToPageAttributes ( IN BOOLEAN IsLargePage
)
{
- UINT32 PageAttributes;
+ UINT32 PageAttributes;
- PageAttributes = 0;
+ PageAttributes = 0;
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index b4fffed9ae..9e304ea05e 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -17,19 +17,19 @@ #include <Library/DebugLib.h>
#include <Library/PcdLib.h>
-#define ID_MMFR0_SHARELVL_SHIFT 12
-#define ID_MMFR0_SHARELVL_MASK 0xf
-#define ID_MMFR0_SHARELVL_ONE 0
-#define ID_MMFR0_SHARELVL_TWO 1
+#define ID_MMFR0_SHARELVL_SHIFT 12
+#define ID_MMFR0_SHARELVL_MASK 0xf
+#define ID_MMFR0_SHARELVL_ONE 0
+#define ID_MMFR0_SHARELVL_TWO 1
-#define ID_MMFR0_INNERSHR_SHIFT 28
-#define ID_MMFR0_INNERSHR_MASK 0xf
-#define ID_MMFR0_OUTERSHR_SHIFT 8
-#define ID_MMFR0_OUTERSHR_MASK 0xf
+#define ID_MMFR0_INNERSHR_SHIFT 28
+#define ID_MMFR0_INNERSHR_MASK 0xf
+#define ID_MMFR0_OUTERSHR_SHIFT 8
+#define ID_MMFR0_OUTERSHR_MASK 0xf
-#define ID_MMFR0_SHR_IMP_UNCACHED 0
-#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
-#define ID_MMFR0_SHR_IGNORED 0xf
+#define ID_MMFR0_SHR_IMP_UNCACHED 0
+#define ID_MMFR0_SHR_IMP_HW_COHERENT 1
+#define ID_MMFR0_SHR_IGNORED 0xf
UINTN
EFIAPI
@@ -49,8 +49,8 @@ PreferNonshareableMemory ( VOID
)
{
- UINTN Mmfr;
- UINTN Val;
+ UINTN Mmfr;
+ UINTN Val;
if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {
return TRUE;
@@ -63,32 +63,33 @@ PreferNonshareableMemory ( //
Mmfr = ArmReadIdMmfr0 ();
switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {
- case ID_MMFR0_SHARELVL_ONE:
- // one level of shareability
- Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;
- break;
- case ID_MMFR0_SHARELVL_TWO:
- // two levels of shareability
- Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;
- break;
- default:
- // unexpected value -> shareable is the safe option
- ASSERT (FALSE);
- return FALSE;
+ case ID_MMFR0_SHARELVL_ONE:
+ // one level of shareability
+ Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;
+ break;
+ case ID_MMFR0_SHARELVL_TWO:
+ // two levels of shareability
+ Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;
+ break;
+ default:
+ // unexpected value -> shareable is the safe option
+ ASSERT (FALSE);
+ return FALSE;
}
+
return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;
}
STATIC
VOID
PopulateLevel2PageTable (
- IN UINT32 *SectionEntry,
- IN UINT32 PhysicalBase,
- IN UINT32 RemainLength,
- IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
+ IN UINT32 *SectionEntry,
+ IN UINT32 PhysicalBase,
+ IN UINT32 RemainLength,
+ IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
)
{
- UINT32* PageEntry;
+ UINT32 *PageEntry;
UINT32 Pages;
UINT32 Index;
UINT32 PageAttributes;
@@ -104,7 +105,7 @@ PopulateLevel2PageTable ( break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
- PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
+ PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
@@ -132,7 +133,7 @@ PopulateLevel2PageTable ( // Level 2 Translation Table to it
if (*SectionEntry != 0) {
// The entry must be a page table. Otherwise it exists an overlapping in the memory map
- if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (*SectionEntry)) {
TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;
} else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
// Case where a virtual memory map descriptor overlapped a section entry
@@ -140,60 +141,66 @@ PopulateLevel2PageTable ( // Allocate a Level2 Page Table for this Section
TranslationTable = (UINTN)AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),
- TRANSLATION_TABLE_PAGE_ALIGNMENT);
+ TRANSLATION_TABLE_PAGE_ALIGNMENT
+ );
// Translate the Section Descriptor into Page Descriptor
SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);
- BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);
+ BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (*SectionEntry);
//
// Make sure we are not inadvertently hitting in the caches
// when populating the page tables
//
- InvalidateDataCacheRange ((VOID *)TranslationTable,
- TRANSLATION_TABLE_PAGE_SIZE);
+ InvalidateDataCacheRange (
+ (VOID *)TranslationTable,
+ TRANSLATION_TABLE_PAGE_SIZE
+ );
// Populate the new Level2 Page Table for the section
- PageEntry = (UINT32*)TranslationTable;
+ PageEntry = (UINT32 *)TranslationTable;
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
- PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;
+ PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseSectionAddress + (Index << 12)) | SectionDescriptor;
}
// Overwrite the section entry to point to the new Level2 Translation Table
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
- (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
- TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
+ (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |
+ TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
} else {
// We do not support the other section type (16MB Section)
- ASSERT(0);
+ ASSERT (0);
return;
}
} else {
TranslationTable = (UINTN)AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_PAGE_SIZE),
- TRANSLATION_TABLE_PAGE_ALIGNMENT);
+ TRANSLATION_TABLE_PAGE_ALIGNMENT
+ );
//
// Make sure we are not inadvertently hitting in the caches
// when populating the page tables
//
- InvalidateDataCacheRange ((VOID *)TranslationTable,
- TRANSLATION_TABLE_PAGE_SIZE);
+ InvalidateDataCacheRange (
+ (VOID *)TranslationTable,
+ TRANSLATION_TABLE_PAGE_SIZE
+ );
ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);
*SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
- (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
- TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
+ (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE (Attributes) ? (1 << 3) : 0) |
+ TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
}
FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
- PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;
- Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
+ PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;
+ Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);
for (Index = 0; Index < Pages; Index++) {
- *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;
+ *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (PhysicalBase) | PageAttributes;
PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
}
@@ -202,8 +209,10 @@ PopulateLevel2PageTable ( // [speculatively] since the previous invalidate are evicted again.
//
ArmDataMemoryBarrier ();
- InvalidateDataCacheRange ((UINT32 *)TranslationTable + FirstPageOffset,
- RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry));
+ InvalidateDataCacheRange (
+ (UINT32 *)TranslationTable + FirstPageOffset,
+ RemainLength / TT_DESCRIPTOR_PAGE_SIZE * sizeof (*PageEntry)
+ );
}
STATIC
@@ -219,50 +228,50 @@ FillTranslationTable ( UINT64 RemainLength;
UINT32 PageMapLength;
- ASSERT(MemoryRegion->Length > 0);
+ ASSERT (MemoryRegion->Length > 0);
if (MemoryRegion->PhysicalBase >= SIZE_4GB) {
return;
}
PhysicalBase = (UINT32)MemoryRegion->PhysicalBase;
- RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);
+ RemainLength = MIN (MemoryRegion->Length, SIZE_4GB - PhysicalBase);
switch (MemoryRegion->Attributes) {
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (0);
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE (0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK (1);
Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
- Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
+ Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH (1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
- Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
+ Attributes = TT_DESCRIPTOR_SECTION_DEVICE (1);
break;
case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (1);
break;
default:
- Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
+ Attributes = TT_DESCRIPTOR_SECTION_UNCACHED (0);
break;
}
@@ -271,14 +280,15 @@ FillTranslationTable ( }
// Get the first section entry for this mapping
- SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+ SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS (TranslationTable, MemoryRegion->VirtualBase);
while (RemainLength != 0) {
- if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&
- RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
+ if ((PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
+ (RemainLength >= TT_DESCRIPTOR_SECTION_SIZE))
+ {
// Case: Physical address aligned on the Section Size (1MB) && the length
// is greater than the Section Size
- *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+ *SectionEntry = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (PhysicalBase) | Attributes;
//
// Issue a DMB to ensure that the page table entry update made it to
@@ -291,14 +301,21 @@ FillTranslationTable ( PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
} else {
- PageMapLength = MIN ((UINT32)RemainLength, TT_DESCRIPTOR_SECTION_SIZE -
- (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));
+ PageMapLength = MIN (
+ (UINT32)RemainLength,
+ TT_DESCRIPTOR_SECTION_SIZE -
+ (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE)
+ );
// Case: Physical address aligned on the Section Size (1MB) && the length
// does not fill a section
// Case: Physical address NOT aligned on the Section Size (1MB)
- PopulateLevel2PageTable (SectionEntry, PhysicalBase, PageMapLength,
- MemoryRegion->Attributes);
+ PopulateLevel2PageTable (
+ SectionEntry,
+ PhysicalBase,
+ PageMapLength,
+ MemoryRegion->Attributes
+ );
//
// Issue a DMB to ensure that the page table entry update made it to
@@ -323,16 +340,17 @@ RETURN_STATUS EFIAPI
ArmConfigureMmu (
IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
- OUT VOID **TranslationTableBase OPTIONAL,
+ OUT VOID **TranslationTableBase OPTIONAL,
OUT UINTN *TranslationTableSize OPTIONAL
)
{
- VOID *TranslationTable;
- UINT32 TTBRAttributes;
+ VOID *TranslationTable;
+ UINT32 TTBRAttributes;
TranslationTable = AllocateAlignedPages (
EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE),
- TRANSLATION_TABLE_SECTION_ALIGNMENT);
+ TRANSLATION_TABLE_SECTION_ALIGNMENT
+ );
if (TranslationTable == NULL) {
return RETURN_OUT_OF_RESOURCES;
}
@@ -389,25 +407,27 @@ ArmConfigureMmu ( //
ArmSetTTBCR (0);
- ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
- DOMAIN_ACCESS_CONTROL_NONE(14) |
- DOMAIN_ACCESS_CONTROL_NONE(13) |
- DOMAIN_ACCESS_CONTROL_NONE(12) |
- DOMAIN_ACCESS_CONTROL_NONE(11) |
- DOMAIN_ACCESS_CONTROL_NONE(10) |
- DOMAIN_ACCESS_CONTROL_NONE( 9) |
- DOMAIN_ACCESS_CONTROL_NONE( 8) |
- DOMAIN_ACCESS_CONTROL_NONE( 7) |
- DOMAIN_ACCESS_CONTROL_NONE( 6) |
- DOMAIN_ACCESS_CONTROL_NONE( 5) |
- DOMAIN_ACCESS_CONTROL_NONE( 4) |
- DOMAIN_ACCESS_CONTROL_NONE( 3) |
- DOMAIN_ACCESS_CONTROL_NONE( 2) |
- DOMAIN_ACCESS_CONTROL_NONE( 1) |
- DOMAIN_ACCESS_CONTROL_CLIENT(0));
-
- ArmEnableInstructionCache();
- ArmEnableDataCache();
- ArmEnableMmu();
+ ArmSetDomainAccessControl (
+ DOMAIN_ACCESS_CONTROL_NONE (15) |
+ DOMAIN_ACCESS_CONTROL_NONE (14) |
+ DOMAIN_ACCESS_CONTROL_NONE (13) |
+ DOMAIN_ACCESS_CONTROL_NONE (12) |
+ DOMAIN_ACCESS_CONTROL_NONE (11) |
+ DOMAIN_ACCESS_CONTROL_NONE (10) |
+ DOMAIN_ACCESS_CONTROL_NONE (9) |
+ DOMAIN_ACCESS_CONTROL_NONE (8) |
+ DOMAIN_ACCESS_CONTROL_NONE (7) |
+ DOMAIN_ACCESS_CONTROL_NONE (6) |
+ DOMAIN_ACCESS_CONTROL_NONE (5) |
+ DOMAIN_ACCESS_CONTROL_NONE (4) |
+ DOMAIN_ACCESS_CONTROL_NONE (3) |
+ DOMAIN_ACCESS_CONTROL_NONE (2) |
+ DOMAIN_ACCESS_CONTROL_NONE (1) |
+ DOMAIN_ACCESS_CONTROL_CLIENT (0)
+ );
+
+ ArmEnableInstructionCache ();
+ ArmEnableDataCache ();
+ ArmEnableMmu ();
return RETURN_SUCCESS;
}
diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c index 6b9d7eba90..b402197ade 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibUpdate.c @@ -18,9 +18,9 @@ #include <Chipset/ArmV7.h>
-#define __EFI_MEMORY_RWX 0 // no restrictions
+#define __EFI_MEMORY_RWX 0 // no restrictions
-#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \
+#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \
EFI_MEMORY_WC | \
EFI_MEMORY_WT | \
EFI_MEMORY_WB | \
@@ -33,14 +33,14 @@ ConvertSectionToPages ( IN EFI_PHYSICAL_ADDRESS BaseAddress
)
{
- UINT32 FirstLevelIdx;
- UINT32 SectionDescriptor;
- UINT32 PageTableDescriptor;
- UINT32 PageDescriptor;
- UINT32 Index;
+ UINT32 FirstLevelIdx;
+ UINT32 SectionDescriptor;
+ UINT32 PageTableDescriptor;
+ UINT32 PageDescriptor;
+ UINT32 Index;
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
- volatile ARM_PAGE_TABLE_ENTRY *PageTable;
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ volatile ARM_PAGE_TABLE_ENTRY *PageTable;
DEBUG ((DEBUG_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
@@ -48,12 +48,12 @@ ConvertSectionToPages ( FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
// Calculate index into first level translation table for start of modification
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// Get section attributes and convert to page attributes
SectionDescriptor = FirstLevelTable[FirstLevelIdx];
- PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);
+ PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);
// Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);
@@ -63,7 +63,7 @@ ConvertSectionToPages ( // Write the page table entries out
for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
- PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;
+ PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS (BaseAddress + (Index << 12)) | PageDescriptor;
}
// Formulate page table entry, Domain=0, NS=0
@@ -78,27 +78,27 @@ ConvertSectionToPages ( STATIC
EFI_STATUS
UpdatePageEntries (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes,
- OUT BOOLEAN *FlushTlbs OPTIONAL
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes,
+ OUT BOOLEAN *FlushTlbs OPTIONAL
)
{
- EFI_STATUS Status;
- UINT32 EntryValue;
- UINT32 EntryMask;
- UINT32 FirstLevelIdx;
- UINT32 Offset;
- UINT32 NumPageEntries;
- UINT32 Descriptor;
- UINT32 p;
- UINT32 PageTableIndex;
- UINT32 PageTableEntry;
- UINT32 CurrentPageTableEntry;
- VOID *Mva;
-
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
- volatile ARM_PAGE_TABLE_ENTRY *PageTable;
+ EFI_STATUS Status;
+ UINT32 EntryValue;
+ UINT32 EntryMask;
+ UINT32 FirstLevelIdx;
+ UINT32 Offset;
+ UINT32 NumPageEntries;
+ UINT32 Descriptor;
+ UINT32 p;
+ UINT32 PageTableIndex;
+ UINT32 PageTableEntry;
+ UINT32 CurrentPageTableEntry;
+ VOID *Mva;
+
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ volatile ARM_PAGE_TABLE_ENTRY *PageTable;
Status = EFI_SUCCESS;
@@ -156,19 +156,19 @@ UpdatePageEntries ( // Iterate for the number of 4KB pages to change
Offset = 0;
- for(p = 0; p < NumPageEntries; p++) {
+ for (p = 0; p < NumPageEntries; p++) {
// Calculate index into first level translation table for page table value
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// Read the descriptor from the first level page table
Descriptor = FirstLevelTable[FirstLevelIdx];
// Does this descriptor need to be converted from section entry to 4K pages?
- if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {
+ if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (Descriptor)) {
Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
- if (EFI_ERROR(Status)) {
+ if (EFI_ERROR (Status)) {
// Exit for loop
break;
}
@@ -181,7 +181,7 @@ UpdatePageEntries ( }
// Obtain page table base address
- PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);
+ PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS (Descriptor);
// Calculate index into the page table
PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
@@ -204,9 +204,8 @@ UpdatePageEntries ( ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
}
- Status = EFI_SUCCESS;
+ Status = EFI_SUCCESS;
Offset += TT_DESCRIPTOR_PAGE_SIZE;
-
} // End first level translation table loop
return Status;
@@ -215,21 +214,21 @@ UpdatePageEntries ( STATIC
EFI_STATUS
UpdateSectionEntries (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
- EFI_STATUS Status;
- UINT32 EntryMask;
- UINT32 EntryValue;
- UINT32 FirstLevelIdx;
- UINT32 NumSections;
- UINT32 i;
- UINT32 CurrentDescriptor;
- UINT32 Descriptor;
- VOID *Mva;
- volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
+ EFI_STATUS Status;
+ UINT32 EntryMask;
+ UINT32 EntryValue;
+ UINT32 FirstLevelIdx;
+ UINT32 NumSections;
+ UINT32 i;
+ UINT32 CurrentDescriptor;
+ UINT32 Descriptor;
+ VOID *Mva;
+ volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
Status = EFI_SUCCESS;
@@ -286,24 +285,25 @@ UpdateSectionEntries ( FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
// calculate index into first level translation table for start of modification
- FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
+ FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS (BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
// calculate number of 1MB first level entries this applies to
NumSections = (UINT32)(Length / TT_DESCRIPTOR_SECTION_SIZE);
// iterate through each descriptor
- for(i=0; i<NumSections; i++) {
+ for (i = 0; i < NumSections; i++) {
CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
// has this descriptor already been converted to pages?
- if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {
+ if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE (CurrentDescriptor)) {
// forward this 1MB range to page table function instead
Status = UpdatePageEntries (
(FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,
TT_DESCRIPTOR_SECTION_SIZE,
Attributes,
- NULL);
+ NULL
+ );
} else {
// still a section entry
@@ -334,14 +334,14 @@ UpdateSectionEntries ( EFI_STATUS
ArmSetMemoryAttributes (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT64 Attributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT64 Attributes
)
{
- EFI_STATUS Status;
- UINT64 ChunkLength;
- BOOLEAN FlushTlbs;
+ EFI_STATUS Status;
+ UINT64 ChunkLength;
+ BOOLEAN FlushTlbs;
if (BaseAddress > (UINT64)MAX_ADDRESS) {
return EFI_UNSUPPORTED;
@@ -355,19 +355,22 @@ ArmSetMemoryAttributes ( FlushTlbs = FALSE;
while (Length > 0) {
if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
- Length >= TT_DESCRIPTOR_SECTION_SIZE) {
-
+ (Length >= TT_DESCRIPTOR_SECTION_SIZE))
+ {
ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;
- DEBUG ((DEBUG_PAGE,
+ DEBUG ((
+ DEBUG_PAGE,
"SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",
- BaseAddress, ChunkLength, Attributes));
+ BaseAddress,
+ ChunkLength,
+ Attributes
+ ));
Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);
FlushTlbs = TRUE;
} else {
-
//
// Process page by page until the next section boundary, but only if
// we have more than a section's worth of area to deal with after that.
@@ -378,12 +381,20 @@ ArmSetMemoryAttributes ( ChunkLength = Length;
}
- DEBUG ((DEBUG_PAGE,
+ DEBUG ((
+ DEBUG_PAGE,
"SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",
- BaseAddress, ChunkLength, Attributes));
+ BaseAddress,
+ ChunkLength,
+ Attributes
+ ));
- Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes,
- &FlushTlbs);
+ Status = UpdatePageEntries (
+ BaseAddress,
+ ChunkLength,
+ Attributes,
+ &FlushTlbs
+ );
}
if (EFI_ERROR (Status)) {
@@ -391,19 +402,20 @@ ArmSetMemoryAttributes ( }
BaseAddress += ChunkLength;
- Length -= ChunkLength;
+ Length -= ChunkLength;
}
if (FlushTlbs) {
ArmInvalidateTlb ();
}
+
return Status;
}
EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);
@@ -411,8 +423,8 @@ ArmSetMemoryRegionNoExec ( EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
@@ -420,8 +432,8 @@ ArmClearMemoryRegionNoExec ( EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
@@ -429,8 +441,8 @@ ArmSetMemoryRegionReadOnly ( EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
diff --git a/ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c b/ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c index 8dc2d07e39..8d5d37e7ae 100644 --- a/ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c +++ b/ArmPkg/Library/ArmMtlNullLib/ArmMtlNullLib.c @@ -34,7 +34,7 @@ MtlWaitUntilChannelFree ( @retval UINT32* Pointer to the payload.
**/
-UINT32*
+UINT32 *
MtlGetChannelPayload (
IN MTL_CHANNEL *Channel
)
diff --git a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c index 97d49816aa..7bcd348495 100644 --- a/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.c @@ -36,30 +36,30 @@ EFI_STATUS
EFIAPI
LibResetSystem (
- IN EFI_RESET_TYPE ResetType,
- IN EFI_STATUS ResetStatus,
- IN UINTN DataSize,
- IN CHAR16 *ResetData OPTIONAL
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN CHAR16 *ResetData OPTIONAL
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
switch (ResetType) {
- case EfiResetPlatformSpecific:
+ case EfiResetPlatformSpecific:
// Map the platform specific reset as reboot
- case EfiResetWarm:
+ case EfiResetWarm:
// Map a warm reset into a cold reset
- case EfiResetCold:
- // Send a PSCI 0.2 SYSTEM_RESET command
- ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
- break;
- case EfiResetShutdown:
- // Send a PSCI 0.2 SYSTEM_OFF command
- ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
- break;
- default:
- ASSERT (FALSE);
- return EFI_UNSUPPORTED;
+ case EfiResetCold:
+ // Send a PSCI 0.2 SYSTEM_RESET command
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
+ break;
+ case EfiResetShutdown:
+ // Send a PSCI 0.2 SYSTEM_OFF command
+ ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
+ break;
+ default:
+ ASSERT (FALSE);
+ return EFI_UNSUPPORTED;
}
ArmCallSmc (&ArmSmcArgs);
diff --git a/ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c b/ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c index 2d79aadaf1..3c1adef8eb 100644 --- a/ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c +++ b/ArmPkg/Library/ArmSmcLibNull/ArmSmcLibNull.c @@ -10,7 +10,7 @@ VOID
ArmCallSmc (
- IN OUT ARM_SMC_ARGS *Args
+ IN OUT ARM_SMC_ARGS *Args
)
{
}
diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c index 8b5ff5c27e..6688fca37a 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c @@ -31,7 +31,7 @@ ResetCold ( VOID
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
// Send a PSCI 0.2 SYSTEM_RESET command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_RESET;
@@ -66,7 +66,7 @@ ResetShutdown ( VOID
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
// Send a PSCI 0.2 SYSTEM_OFF command
ArmSmcArgs.Arg0 = ARM_SMC_ID_PSCI_SYSTEM_OFF;
@@ -87,8 +87,8 @@ ResetShutdown ( VOID
EFIAPI
ResetPlatformSpecific (
- IN UINTN DataSize,
- IN VOID *ResetData
+ IN UINTN DataSize,
+ IN VOID *ResetData
)
{
// Map the platform specific reset as reboot
@@ -110,30 +110,30 @@ ResetPlatformSpecific ( VOID
EFIAPI
ResetSystem (
- IN EFI_RESET_TYPE ResetType,
- IN EFI_STATUS ResetStatus,
- IN UINTN DataSize,
- IN VOID *ResetData OPTIONAL
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN VOID *ResetData OPTIONAL
)
{
switch (ResetType) {
- case EfiResetWarm:
- ResetWarm ();
- break;
+ case EfiResetWarm:
+ ResetWarm ();
+ break;
- case EfiResetCold:
- ResetCold ();
- break;
+ case EfiResetCold:
+ ResetCold ();
+ break;
- case EfiResetShutdown:
- ResetShutdown ();
- return;
+ case EfiResetShutdown:
+ ResetShutdown ();
+ return;
- case EfiResetPlatformSpecific:
- ResetPlatformSpecific (DataSize, ResetData);
- return;
+ case EfiResetPlatformSpecific:
+ ResetPlatformSpecific (DataSize, ResetData);
+ return;
- default:
- return;
+ default:
+ return;
}
}
diff --git a/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c b/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c index 77e2473678..55ec564309 100644 --- a/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c +++ b/ArmPkg/Library/ArmSoftFloatLib/ArmSoftFloatLib.c @@ -18,35 +18,47 @@ * have been expected we use aeabi_float_t and aeabi_double_t respectively
* instead.
*/
-typedef uint32_t aeabi_float_t;
-typedef uint64_t aeabi_double_t;
+typedef uint32_t aeabi_float_t;
+typedef uint64_t aeabi_double_t;
/*
* Helpers to convert between float32 and aeabi_float_t, and float64 and
* aeabi_double_t used by the AEABI functions below.
*/
-static aeabi_float_t f32_to_f(float32_t val)
+static aeabi_float_t
+f32_to_f (
+ float32_t val
+ )
{
return val.v;
}
-static float32_t f32_from_f(aeabi_float_t val)
+static float32_t
+f32_from_f (
+ aeabi_float_t val
+ )
{
- float32_t res;
+ float32_t res;
res.v = val;
return res;
}
-static aeabi_double_t f64_to_d(float64_t val)
+static aeabi_double_t
+f64_to_d (
+ float64_t val
+ )
{
return val.v;
}
-static float64_t f64_from_d(aeabi_double_t val)
+static float64_t
+f64_from_d (
+ aeabi_double_t val
+ )
{
- float64_t res;
+ float64_t res;
res.v = val;
@@ -64,220 +76,346 @@ static float64_t f64_from_d(aeabi_double_t val) * Table 2, Standard aeabi_double_t precision floating-point arithmetic helper
* functions
*/
-
-aeabi_double_t __aeabi_dadd(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_dadd (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_add(f64_from_d(a), f64_from_d(b)));
+ return f64_to_d (f64_add (f64_from_d (a), f64_from_d (b)));
}
-aeabi_double_t __aeabi_ddiv(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_ddiv (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_div(f64_from_d(a), f64_from_d(b)));
+ return f64_to_d (f64_div (f64_from_d (a), f64_from_d (b)));
}
-aeabi_double_t __aeabi_dmul(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_dmul (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_mul(f64_from_d(a), f64_from_d(b)));
+ return f64_to_d (f64_mul (f64_from_d (a), f64_from_d (b)));
}
-
-aeabi_double_t __aeabi_drsub(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_drsub (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_sub(f64_from_d(b), f64_from_d(a)));
+ return f64_to_d (f64_sub (f64_from_d (b), f64_from_d (a)));
}
-aeabi_double_t __aeabi_dsub(aeabi_double_t a, aeabi_double_t b)
+aeabi_double_t
+__aeabi_dsub (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_to_d(f64_sub(f64_from_d(a), f64_from_d(b)));
+ return f64_to_d (f64_sub (f64_from_d (a), f64_from_d (b)));
}
/*
* Table 3, double precision floating-point comparison helper functions
*/
-
-int __aeabi_dcmpeq(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmpeq (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_eq(f64_from_d(a), f64_from_d(b));
+ return f64_eq (f64_from_d (a), f64_from_d (b));
}
-int __aeabi_dcmplt(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmplt (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_lt(f64_from_d(a), f64_from_d(b));
+ return f64_lt (f64_from_d (a), f64_from_d (b));
}
-int __aeabi_dcmple(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmple (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_le(f64_from_d(a), f64_from_d(b));
+ return f64_le (f64_from_d (a), f64_from_d (b));
}
-int __aeabi_dcmpge(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmpge (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_le(f64_from_d(b), f64_from_d(a));
+ return f64_le (f64_from_d (b), f64_from_d (a));
}
-int __aeabi_dcmpgt(aeabi_double_t a, aeabi_double_t b)
+int
+__aeabi_dcmpgt (
+ aeabi_double_t a,
+ aeabi_double_t b
+ )
{
- return f64_lt(f64_from_d(b), f64_from_d(a));
+ return f64_lt (f64_from_d (b), f64_from_d (a));
}
/*
* Table 4, Standard single precision floating-point arithmetic helper
* functions
*/
-
-aeabi_float_t __aeabi_fadd(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_fadd (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_add(f32_from_f(a), f32_from_f(b)));
+ return f32_to_f (f32_add (f32_from_f (a), f32_from_f (b)));
}
-aeabi_float_t __aeabi_fdiv(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_fdiv (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_div(f32_from_f(a), f32_from_f(b)));
+ return f32_to_f (f32_div (f32_from_f (a), f32_from_f (b)));
}
-aeabi_float_t __aeabi_fmul(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_fmul (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_mul(f32_from_f(a), f32_from_f(b)));
+ return f32_to_f (f32_mul (f32_from_f (a), f32_from_f (b)));
}
-aeabi_float_t __aeabi_frsub(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_frsub (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_sub(f32_from_f(b), f32_from_f(a)));
+ return f32_to_f (f32_sub (f32_from_f (b), f32_from_f (a)));
}
-aeabi_float_t __aeabi_fsub(aeabi_float_t a, aeabi_float_t b)
+aeabi_float_t
+__aeabi_fsub (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_to_f(f32_sub(f32_from_f(a), f32_from_f(b)));
+ return f32_to_f (f32_sub (f32_from_f (a), f32_from_f (b)));
}
/*
* Table 5, Standard single precision floating-point comparison helper
* functions
*/
-
-int __aeabi_fcmpeq(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmpeq (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_eq(f32_from_f(a), f32_from_f(b));
+ return f32_eq (f32_from_f (a), f32_from_f (b));
}
-int __aeabi_fcmplt(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmplt (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_lt(f32_from_f(a), f32_from_f(b));
+ return f32_lt (f32_from_f (a), f32_from_f (b));
}
-int __aeabi_fcmple(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmple (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_le(f32_from_f(a), f32_from_f(b));
+ return f32_le (f32_from_f (a), f32_from_f (b));
}
-int __aeabi_fcmpge(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmpge (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_le(f32_from_f(b), f32_from_f(a));
+ return f32_le (f32_from_f (b), f32_from_f (a));
}
-int __aeabi_fcmpgt(aeabi_float_t a, aeabi_float_t b)
+int
+__aeabi_fcmpgt (
+ aeabi_float_t a,
+ aeabi_float_t b
+ )
{
- return f32_lt(f32_from_f(b), f32_from_f(a));
+ return f32_lt (f32_from_f (b), f32_from_f (a));
}
/*
* Table 6, Standard floating-point to integer conversions
*/
-
-int __aeabi_d2iz(aeabi_double_t a)
+int
+__aeabi_d2iz (
+ aeabi_double_t a
+ )
{
- return f64_to_i32_r_minMag(f64_from_d(a), false);
+ return f64_to_i32_r_minMag (f64_from_d (a), false);
}
-unsigned __aeabi_d2uiz(aeabi_double_t a)
+unsigned
+__aeabi_d2uiz (
+ aeabi_double_t a
+ )
{
- return f64_to_ui32_r_minMag(f64_from_d(a), false);
+ return f64_to_ui32_r_minMag (f64_from_d (a), false);
}
-long long __aeabi_d2lz(aeabi_double_t a)
+long long
+__aeabi_d2lz (
+ aeabi_double_t a
+ )
{
- return f64_to_i64_r_minMag(f64_from_d(a), false);
+ return f64_to_i64_r_minMag (f64_from_d (a), false);
}
-unsigned long long __aeabi_d2ulz(aeabi_double_t a)
+unsigned long long
+__aeabi_d2ulz (
+ aeabi_double_t a
+ )
{
- return f64_to_ui64_r_minMag(f64_from_d(a), false);
+ return f64_to_ui64_r_minMag (f64_from_d (a), false);
}
-int __aeabi_f2iz(aeabi_float_t a)
+int
+__aeabi_f2iz (
+ aeabi_float_t a
+ )
{
- return f32_to_i32_r_minMag(f32_from_f(a), false);
+ return f32_to_i32_r_minMag (f32_from_f (a), false);
}
-unsigned __aeabi_f2uiz(aeabi_float_t a)
+unsigned
+__aeabi_f2uiz (
+ aeabi_float_t a
+ )
{
- return f32_to_ui32_r_minMag(f32_from_f(a), false);
+ return f32_to_ui32_r_minMag (f32_from_f (a), false);
}
-long long __aeabi_f2lz(aeabi_float_t a)
+long long
+__aeabi_f2lz (
+ aeabi_float_t a
+ )
{
- return f32_to_i64_r_minMag(f32_from_f(a), false);
+ return f32_to_i64_r_minMag (f32_from_f (a), false);
}
-unsigned long long __aeabi_f2ulz(aeabi_float_t a)
+unsigned long long
+__aeabi_f2ulz (
+ aeabi_float_t a
+ )
{
- return f32_to_ui64_r_minMag(f32_from_f(a), false);
+ return f32_to_ui64_r_minMag (f32_from_f (a), false);
}
/*
* Table 7, Standard conversions between floating types
*/
-
-aeabi_float_t __aeabi_d2f(aeabi_double_t a)
+aeabi_float_t
+__aeabi_d2f (
+ aeabi_double_t a
+ )
{
- return f32_to_f(f64_to_f32(f64_from_d(a)));
+ return f32_to_f (f64_to_f32 (f64_from_d (a)));
}
-aeabi_double_t __aeabi_f2d(aeabi_float_t a)
+aeabi_double_t
+__aeabi_f2d (
+ aeabi_float_t a
+ )
{
- return f64_to_d(f32_to_f64(f32_from_f(a)));
+ return f64_to_d (f32_to_f64 (f32_from_f (a)));
}
/*
* Table 8, Standard integer to floating-point conversions
*/
-
-aeabi_double_t __aeabi_i2d(int a)
+aeabi_double_t
+__aeabi_i2d (
+ int a
+ )
{
- return f64_to_d(i32_to_f64(a));
+ return f64_to_d (i32_to_f64 (a));
}
-aeabi_double_t __aeabi_ui2d(unsigned a)
+aeabi_double_t
+__aeabi_ui2d (
+ unsigned a
+ )
{
- return f64_to_d(ui32_to_f64(a));
+ return f64_to_d (ui32_to_f64 (a));
}
-aeabi_double_t __aeabi_l2d(long long a)
+aeabi_double_t
+__aeabi_l2d (
+ long long a
+ )
{
- return f64_to_d(i64_to_f64(a));
+ return f64_to_d (i64_to_f64 (a));
}
-aeabi_double_t __aeabi_ul2d(unsigned long long a)
+aeabi_double_t
+__aeabi_ul2d (
+ unsigned long long a
+ )
{
- return f64_to_d(ui64_to_f64(a));
+ return f64_to_d (ui64_to_f64 (a));
}
-aeabi_float_t __aeabi_i2f(int a)
+aeabi_float_t
+__aeabi_i2f (
+ int a
+ )
{
- return f32_to_f(i32_to_f32(a));
+ return f32_to_f (i32_to_f32 (a));
}
-aeabi_float_t __aeabi_ui2f(unsigned a)
+aeabi_float_t
+__aeabi_ui2f (
+ unsigned a
+ )
{
- return f32_to_f(ui32_to_f32(a));
+ return f32_to_f (ui32_to_f32 (a));
}
-aeabi_float_t __aeabi_l2f(long long a)
+aeabi_float_t
+__aeabi_l2f (
+ long long a
+ )
{
- return f32_to_f(i64_to_f32(a));
+ return f32_to_f (i64_to_f32 (a));
}
-aeabi_float_t __aeabi_ul2f(unsigned long long a)
+aeabi_float_t
+__aeabi_ul2f (
+ unsigned long long a
+ )
{
- return f32_to_f(ui64_to_f32(a));
+ return f32_to_f (ui64_to_f32 (a));
}
diff --git a/ArmPkg/Library/ArmSoftFloatLib/platform.h b/ArmPkg/Library/ArmSoftFloatLib/platform.h index fddf9de04d..3b70360568 100644 --- a/ArmPkg/Library/ArmSoftFloatLib/platform.h +++ b/ArmPkg/Library/ArmSoftFloatLib/platform.h @@ -8,9 +8,9 @@ #ifndef ARM_SOFT_FLOAT_LIB_H_
#define ARM_SOFT_FLOAT_LIB_H_
-#define LITTLEENDIAN 1
-#define INLINE static inline
-#define SOFTFLOAT_BUILTIN_CLZ 1
+#define LITTLEENDIAN 1
+#define INLINE static inline
+#define SOFTFLOAT_BUILTIN_CLZ 1
#define SOFTFLOAT_FAST_INT64
#include "opts-GCC.h"
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c b/ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c index b0e0322951..cedbfca471 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memcmp_ms.c @@ -1,32 +1,45 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2019, Pete Batard. All rights reserved.
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
-#if defined(_M_ARM64)
-typedef unsigned __int64 size_t;
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
#else
-typedef unsigned __int32 size_t;
+typedef unsigned __int32 size_t;
#endif
-int memcmp(void *, void *, size_t);
+int
+memcmp (
+ void *,
+ void *,
+ size_t
+ );
+
#pragma intrinsic(memcmp)
#pragma function(memcmp)
-int memcmp(const void *s1, const void *s2, size_t n)
+int
+memcmp (
+ const void *s1,
+ const void *s2,
+ size_t n
+ )
{
- unsigned char const *t1;
- unsigned char const *t2;
+ unsigned char const *t1;
+ unsigned char const *t2;
t1 = s1;
t2 = s2;
while (n-- != 0) {
- if (*t1 != *t2)
+ if (*t1 != *t2) {
return (int)*t1 - (int)*t2;
+ }
+
t1++;
t2++;
}
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c index e1d0b72782..415146f7f2 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy.c @@ -1,18 +1,23 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
typedef __SIZE_TYPE__ size_t;
-static void __memcpy(void *dest, const void *src, size_t n)
+static void
+__memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
{
- unsigned char *d;
- unsigned char const *s;
+ unsigned char *d;
+ unsigned char const *s;
d = dest;
s = src;
@@ -22,21 +27,41 @@ static void __memcpy(void *dest, const void *src, size_t n) }
}
-void *memcpy(void *dest, const void *src, size_t n)
+void *
+memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
{
- __memcpy(dest, src, n);
+ __memcpy (dest, src, n);
return dest;
}
#ifdef __arm__
-__attribute__((__alias__("__memcpy")))
-void __aeabi_memcpy(void *dest, const void *src, size_t n);
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ );
-__attribute__((__alias__("__memcpy")))
-void __aeabi_memcpy4(void *dest, const void *src, size_t n);
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy4 (
+ void *dest,
+ const void *src,
+ size_t n
+ );
-__attribute__((__alias__("__memcpy")))
-void __aeabi_memcpy8(void *dest, const void *src, size_t n);
+__attribute__ ((__alias__ ("__memcpy")))
+void
+__aeabi_memcpy8 (
+ void *dest,
+ const void *src,
+ size_t n
+ );
#endif
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c index a52fd8deef..0eafa83ed4 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memcpy_ms.c @@ -1,25 +1,36 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
-#if defined(_M_ARM64)
-typedef unsigned __int64 size_t;
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
#else
-typedef unsigned __int32 size_t;
+typedef unsigned __int32 size_t;
#endif
-void* memcpy(void *, const void *, size_t);
+void *
+memcpy (
+ void *,
+ const void *,
+ size_t
+ );
+
#pragma intrinsic(memcpy)
#pragma function(memcpy)
-void* memcpy(void *dest, const void *src, size_t n)
+void *
+memcpy (
+ void *dest,
+ const void *src,
+ size_t n
+ )
{
- unsigned char *d;
- unsigned char const *s;
+ unsigned char *d;
+ unsigned char const *s;
d = dest;
s = src;
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c b/ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c index ebc9e385aa..f68eb52a6c 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memmove_ms.c @@ -1,25 +1,36 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2019, Pete Batard. All rights reserved.
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
-#if defined(_M_ARM64)
-typedef unsigned __int64 size_t;
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
#else
-typedef unsigned __int32 size_t;
+typedef unsigned __int32 size_t;
#endif
-void* memmove(void *, const void *, size_t);
+void *
+memmove (
+ void *,
+ const void *,
+ size_t
+ );
+
#pragma intrinsic(memmove)
#pragma function(memmove)
-void* memmove(void *dest, const void *src, size_t n)
+void *
+memmove (
+ void *dest,
+ const void *src,
+ size_t n
+ )
{
- unsigned char *d;
- unsigned char const *s;
+ unsigned char *d;
+ unsigned char const *s;
d = dest;
s = src;
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memset.c b/ArmPkg/Library/CompilerIntrinsicsLib/memset.c index 63f6cf68a6..3e45302fe6 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memset.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memset.c @@ -1,18 +1,23 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2016, Linaro Ltd. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
typedef __SIZE_TYPE__ size_t;
-static __attribute__((__used__))
-void *__memset(void *s, int c, size_t n)
+static __attribute__ ((__used__))
+void *
+__memset (
+ void *s,
+ int c,
+ size_t n
+ )
{
- unsigned char *d;
+ unsigned char *d;
d = s;
@@ -29,31 +34,63 @@ void *__memset(void *s, int c, size_t n) // object was pulled into the link due to the definitions below. So make
// our memset() 'weak' to let the other implementation take precedence.
//
-__attribute__((__weak__, __alias__("__memset")))
-void *memset(void *dest, int c, size_t n);
+__attribute__ ((__weak__, __alias__ ("__memset")))
+void *
+memset (
+ void *dest,
+ int c,
+ size_t n
+ );
#ifdef __arm__
-void __aeabi_memset(void *dest, size_t n, int c)
+void
+__aeabi_memset (
+ void *dest,
+ size_t n,
+ int c
+ )
{
- __memset(dest, c, n);
+ __memset (dest, c, n);
}
-__attribute__((__alias__("__aeabi_memset")))
-void __aeabi_memset4(void *dest, size_t n, int c);
+__attribute__ ((__alias__ ("__aeabi_memset")))
+void
+__aeabi_memset4 (
+ void *dest,
+ size_t n,
+ int c
+ );
-__attribute__((__alias__("__aeabi_memset")))
-void __aeabi_memset8(void *dest, size_t n, int c);
+__attribute__ ((__alias__ ("__aeabi_memset")))
+void
+__aeabi_memset8 (
+ void *dest,
+ size_t n,
+ int c
+ );
-void __aeabi_memclr(void *dest, size_t n)
+void
+__aeabi_memclr (
+ void *dest,
+ size_t n
+ )
{
- __memset(dest, 0, n);
+ __memset (dest, 0, n);
}
-__attribute__((__alias__("__aeabi_memclr")))
-void __aeabi_memclr4(void *dest, size_t n);
+__attribute__ ((__alias__ ("__aeabi_memclr")))
+void
+__aeabi_memclr4 (
+ void *dest,
+ size_t n
+ );
-__attribute__((__alias__("__aeabi_memclr")))
-void __aeabi_memclr8(void *dest, size_t n);
+__attribute__ ((__alias__ ("__aeabi_memclr")))
+void
+__aeabi_memclr8 (
+ void *dest,
+ size_t n
+ );
#endif
diff --git a/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c b/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c index b88a5f2c5f..5882cd28b0 100644 --- a/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c +++ b/ArmPkg/Library/CompilerIntrinsicsLib/memset_ms.c @@ -1,24 +1,35 @@ -//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
//
// Copyright (c) 2017, Pete Batard. All rights reserved.<BR>
// Copyright (c) 2021, Arm Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
-//------------------------------------------------------------------------------
+// ------------------------------------------------------------------------------
-#if defined(_M_ARM64)
-typedef unsigned __int64 size_t;
+#if defined (_M_ARM64)
+typedef unsigned __int64 size_t;
#else
-typedef unsigned __int32 size_t;
+typedef unsigned __int32 size_t;
#endif
-void* memset(void *, int, size_t);
+void *
+memset (
+ void *,
+ int,
+ size_t
+ );
+
#pragma intrinsic(memset)
#pragma function(memset)
-void *memset(void *s, int c, size_t n)
+void *
+memset (
+ void *s,
+ int c,
+ size_t n
+ )
{
- unsigned char *d;
+ unsigned char *d;
d = s;
diff --git a/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c b/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c index c8edc4f5cf..77c92f9ecc 100644 --- a/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c +++ b/ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.c @@ -22,7 +22,6 @@ #define GET_OCCUPIED_SIZE(ActualSize, Alignment) \
(ActualSize) + (((Alignment) - ((ActualSize) & ((Alignment) - 1))) & ((Alignment) - 1))
-
// Vector Table for Sec Phase
VOID
DebugAgentVectorTable (
@@ -53,7 +52,7 @@ GetFileState ( FileState = FfsHeader->State;
if (ErasePolarity != 0) {
- FileState = (EFI_FFS_FILE_STATE)~FileState;
+ FileState = (EFI_FFS_FILE_STATE) ~FileState;
}
HighestBit = 0x80;
@@ -79,10 +78,10 @@ CalculateHeaderChecksum ( IN EFI_FFS_FILE_HEADER *FileHeader
)
{
- UINT8 Sum;
+ UINT8 Sum;
// Calculate the sum of the header
- Sum = CalculateSum8 ((CONST VOID*)FileHeader,sizeof(EFI_FFS_FILE_HEADER));
+ Sum = CalculateSum8 ((CONST VOID *)FileHeader, sizeof (EFI_FFS_FILE_HEADER));
// State field (since this indicates the different state of file).
Sum = (UINT8)(Sum - FileHeader->State);
@@ -95,24 +94,24 @@ CalculateHeaderChecksum ( EFI_STATUS
GetFfsFile (
- IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader,
- IN EFI_FV_FILETYPE FileType,
- OUT EFI_FFS_FILE_HEADER **FileHeader
+ IN EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader,
+ IN EFI_FV_FILETYPE FileType,
+ OUT EFI_FFS_FILE_HEADER **FileHeader
)
{
- UINT64 FvLength;
- UINTN FileOffset;
- EFI_FFS_FILE_HEADER *FfsFileHeader;
- UINT8 ErasePolarity;
- UINT8 FileState;
- UINT32 FileLength;
- UINT32 FileOccupiedSize;
+ UINT64 FvLength;
+ UINTN FileOffset;
+ EFI_FFS_FILE_HEADER *FfsFileHeader;
+ UINT8 ErasePolarity;
+ UINT8 FileState;
+ UINT32 FileLength;
+ UINT32 FileOccupiedSize;
ASSERT (FwVolHeader->Signature == EFI_FVH_SIGNATURE);
- FvLength = FwVolHeader->FvLength;
+ FvLength = FwVolHeader->FvLength;
FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FwVolHeader + FwVolHeader->HeaderLength);
- FileOffset = FwVolHeader->HeaderLength;
+ FileOffset = FwVolHeader->HeaderLength;
if (FwVolHeader->Attributes & EFI_FVB2_ERASE_POLARITY) {
ErasePolarity = 1;
@@ -125,42 +124,42 @@ GetFfsFile ( FileState = GetFileState (ErasePolarity, FfsFileHeader);
switch (FileState) {
+ case EFI_FILE_HEADER_INVALID:
+ FileOffset += sizeof (EFI_FFS_FILE_HEADER);
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + sizeof (EFI_FFS_FILE_HEADER));
+ break;
- case EFI_FILE_HEADER_INVALID:
- FileOffset += sizeof(EFI_FFS_FILE_HEADER);
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + sizeof(EFI_FFS_FILE_HEADER));
- break;
-
- case EFI_FILE_DATA_VALID:
- case EFI_FILE_MARKED_FOR_UPDATE:
- if (CalculateHeaderChecksum (FfsFileHeader) != 0) {
- ASSERT (FALSE);
- return EFI_NOT_FOUND;
- }
+ case EFI_FILE_DATA_VALID:
+ case EFI_FILE_MARKED_FOR_UPDATE:
+ if (CalculateHeaderChecksum (FfsFileHeader) != 0) {
+ ASSERT (FALSE);
+ return EFI_NOT_FOUND;
+ }
- if (FfsFileHeader->Type == FileType) {
- *FileHeader = FfsFileHeader;
- return EFI_SUCCESS;
- }
+ if (FfsFileHeader->Type == FileType) {
+ *FileHeader = FfsFileHeader;
+ return EFI_SUCCESS;
+ }
- FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;
- FileOccupiedSize = GET_OCCUPIED_SIZE(FileLength, 8);
+ FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;
+ FileOccupiedSize = GET_OCCUPIED_SIZE (FileLength, 8);
- FileOffset += FileOccupiedSize;
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);
- break;
+ FileOffset += FileOccupiedSize;
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);
+ break;
- case EFI_FILE_DELETED:
- FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;
- FileOccupiedSize = GET_OCCUPIED_SIZE(FileLength, 8);
- FileOffset += FileOccupiedSize;
- FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);
- break;
+ case EFI_FILE_DELETED:
+ FileLength = *(UINT32 *)(FfsFileHeader->Size) & 0x00FFFFFF;
+ FileOccupiedSize = GET_OCCUPIED_SIZE (FileLength, 8);
+ FileOffset += FileOccupiedSize;
+ FfsFileHeader = (EFI_FFS_FILE_HEADER *)((UINT8 *)FfsFileHeader + FileOccupiedSize);
+ break;
- default:
- return EFI_NOT_FOUND;
+ default:
+ return EFI_NOT_FOUND;
}
}
+
return EFI_NOT_FOUND;
}
@@ -170,25 +169,25 @@ GetImageContext ( OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
- EFI_STATUS Status;
- UINTN ParsedLength;
- UINTN SectionSize;
- UINTN SectionLength;
- EFI_COMMON_SECTION_HEADER *Section;
- VOID *EfiImage;
- UINTN ImageAddress;
- EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;
- VOID *CodeViewEntryPointer;
-
- Section = (EFI_COMMON_SECTION_HEADER *)(FfsHeader + 1);
- SectionSize = *(UINT32 *)(FfsHeader->Size) & 0x00FFFFFF;
+ EFI_STATUS Status;
+ UINTN ParsedLength;
+ UINTN SectionSize;
+ UINTN SectionLength;
+ EFI_COMMON_SECTION_HEADER *Section;
+ VOID *EfiImage;
+ UINTN ImageAddress;
+ EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *DebugEntry;
+ VOID *CodeViewEntryPointer;
+
+ Section = (EFI_COMMON_SECTION_HEADER *)(FfsHeader + 1);
+ SectionSize = *(UINT32 *)(FfsHeader->Size) & 0x00FFFFFF;
SectionSize -= sizeof (EFI_FFS_FILE_HEADER);
ParsedLength = 0;
- EfiImage = NULL;
+ EfiImage = NULL;
while (ParsedLength < SectionSize) {
if ((Section->Type == EFI_SECTION_PE32) || (Section->Type == EFI_SECTION_TE)) {
- EfiImage = (EFI_IMAGE_OPTIONAL_HEADER_UNION*)(Section + 1);
+ EfiImage = (EFI_IMAGE_OPTIONAL_HEADER_UNION *)(Section + 1);
break;
}
@@ -201,7 +200,7 @@ GetImageContext ( SectionLength = GET_OCCUPIED_SIZE (SectionLength, 4);
ASSERT (SectionLength != 0);
ParsedLength += SectionLength;
- Section = (EFI_COMMON_SECTION_HEADER *)((UINT8 *)Section + SectionLength);
+ Section = (EFI_COMMON_SECTION_HEADER *)((UINT8 *)Section + SectionLength);
}
if (EfiImage == NULL) {
@@ -214,27 +213,27 @@ GetImageContext ( ImageContext->ImageRead = PeCoffLoaderImageReadFromMemory;
Status = PeCoffLoaderGetImageInfo (ImageContext);
- if (!EFI_ERROR(Status) && ((VOID*)(UINTN)ImageContext->DebugDirectoryEntryRva != NULL)) {
+ if (!EFI_ERROR (Status) && ((VOID *)(UINTN)ImageContext->DebugDirectoryEntryRva != NULL)) {
ImageAddress = ImageContext->ImageAddress;
if (ImageContext->IsTeImage) {
- ImageAddress += sizeof (EFI_TE_IMAGE_HEADER) - ((EFI_TE_IMAGE_HEADER*)EfiImage)->StrippedSize;
+ ImageAddress += sizeof (EFI_TE_IMAGE_HEADER) - ((EFI_TE_IMAGE_HEADER *)EfiImage)->StrippedSize;
}
- DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY*)(ImageAddress + ImageContext->DebugDirectoryEntryRva);
+ DebugEntry = (EFI_IMAGE_DEBUG_DIRECTORY_ENTRY *)(ImageAddress + ImageContext->DebugDirectoryEntryRva);
if (DebugEntry->Type == EFI_IMAGE_DEBUG_TYPE_CODEVIEW) {
- CodeViewEntryPointer = (VOID *) (ImageAddress + (UINTN) DebugEntry->RVA);
- switch (* (UINT32 *) CodeViewEntryPointer) {
- case CODEVIEW_SIGNATURE_NB10:
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY);
- break;
- case CODEVIEW_SIGNATURE_RSDS:
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);
- break;
- case CODEVIEW_SIGNATURE_MTOC:
- ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);
- break;
- default:
- break;
+ CodeViewEntryPointer = (VOID *)(ImageAddress + (UINTN)DebugEntry->RVA);
+ switch (*(UINT32 *)CodeViewEntryPointer) {
+ case CODEVIEW_SIGNATURE_NB10:
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_NB10_ENTRY);
+ break;
+ case CODEVIEW_SIGNATURE_RSDS:
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_RSDS_ENTRY);
+ break;
+ case CODEVIEW_SIGNATURE_MTOC:
+ ImageContext->PdbPointer = (CHAR8 *)CodeViewEntryPointer + sizeof (EFI_IMAGE_DEBUG_CODEVIEW_MTOC_ENTRY);
+ break;
+ default:
+ break;
}
}
}
@@ -272,8 +271,8 @@ InitializeDebugAgent ( IN DEBUG_AGENT_CONTINUE Function OPTIONAL
)
{
- EFI_STATUS Status;
- EFI_FFS_FILE_HEADER *FfsHeader;
+ EFI_STATUS Status;
+ EFI_FFS_FILE_HEADER *FfsHeader;
PE_COFF_LOADER_IMAGE_CONTEXT ImageContext;
// We use InitFlag to know if DebugAgent has been initialized from
@@ -283,10 +282,10 @@ InitializeDebugAgent ( //
// Get the Sec or PrePeiCore module (defined as SEC type module)
//
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
- if (!EFI_ERROR(Status)) {
- Status = GetImageContext (FfsHeader,&ImageContext);
- if (!EFI_ERROR(Status)) {
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdSecureFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
+ if (!EFI_ERROR (Status)) {
+ Status = GetImageContext (FfsHeader, &ImageContext);
+ if (!EFI_ERROR (Status)) {
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
}
}
@@ -294,10 +293,10 @@ InitializeDebugAgent ( //
// Get the PrePi or PrePeiCore module (defined as SEC type module)
//
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
- if (!EFI_ERROR(Status)) {
- Status = GetImageContext (FfsHeader,&ImageContext);
- if (!EFI_ERROR(Status)) {
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_SECURITY_CORE, &FfsHeader);
+ if (!EFI_ERROR (Status)) {
+ Status = GetImageContext (FfsHeader, &ImageContext);
+ if (!EFI_ERROR (Status)) {
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
}
}
@@ -305,10 +304,10 @@ InitializeDebugAgent ( //
// Get the PeiCore module (defined as PEI_CORE type module)
//
- Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER*)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);
- if (!EFI_ERROR(Status)) {
- Status = GetImageContext (FfsHeader,&ImageContext);
- if (!EFI_ERROR(Status)) {
+ Status = GetFfsFile ((EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)PcdGet64 (PcdFvBaseAddress), EFI_FV_FILETYPE_PEI_CORE, &FfsHeader);
+ if (!EFI_ERROR (Status)) {
+ Status = GetImageContext (FfsHeader, &ImageContext);
+ if (!EFI_ERROR (Status)) {
PeCoffLoaderRelocateImageExtraAction (&ImageContext);
}
}
@@ -330,7 +329,7 @@ InitializeDebugAgent ( BOOLEAN
EFIAPI
SaveAndSetDebugTimerInterrupt (
- IN BOOLEAN EnableStatus
+ IN BOOLEAN EnableStatus
)
{
return FALSE;
diff --git a/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c b/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c index 2e8afc051e..3827122a96 100644 --- a/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c +++ b/ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.c @@ -17,7 +17,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/PeCoffExtraActionLib.h>
#include <Library/PrintLib.h>
-
/**
If the build is done on cygwin the paths are cygpaths.
/cygdrive/c/tmp.txt vs c:\tmp.txt so we need to convert
@@ -28,14 +27,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/
CHAR8 *
DeCygwinPathIfNeeded (
- IN CHAR8 *Name,
- IN CHAR8 *Temp,
- IN UINTN Size
+ IN CHAR8 *Name,
+ IN CHAR8 *Temp,
+ IN UINTN Size
)
{
- CHAR8 *Ptr;
- UINTN Index;
- UINTN Index2;
+ CHAR8 *Ptr;
+ UINTN Index;
+ UINTN Index2;
Ptr = AsciiStrStr (Name, "/cygdrive/");
if (Ptr == NULL) {
@@ -45,19 +44,18 @@ DeCygwinPathIfNeeded ( for (Index = 9, Index2 = 0; (Index < (Size + 9)) && (Ptr[Index] != '\0'); Index++, Index2++) {
Temp[Index2] = Ptr[Index];
if (Temp[Index2] == '/') {
- Temp[Index2] = '\\' ;
- }
+ Temp[Index2] = '\\';
+ }
if (Index2 == 1) {
Temp[Index2 - 1] = Ptr[Index];
- Temp[Index2] = ':';
+ Temp[Index2] = ':';
}
}
return Temp;
}
-
/**
Performs additional actions after a PE/COFF image has been loaded and relocated.
@@ -73,32 +71,30 @@ PeCoffLoaderRelocateImageExtraAction ( IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
-#if !defined(MDEPKG_NDEBUG)
- CHAR8 Temp[512];
-#endif
+ #if !defined (MDEPKG_NDEBUG)
+ CHAR8 Temp[512];
+ #endif
if (ImageContext->PdbPointer) {
-#ifdef __CC_ARM
-#if (__ARMCC_VERSION < 500000)
+ #ifdef __CC_ARM
+ #if (__ARMCC_VERSION < 500000)
// Print out the command for the RVD debugger to load symbols for this image
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "load /a /ni /np %a &0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
-#else
+ #else
// Print out the command for the DS-5 to load symbols for this image
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "add-symbol-file %a 0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
-#endif
-#elif __GNUC__
+ #endif
+ #elif __GNUC__
// This may not work correctly if you generate PE/COFF directly as then the Offset would not be required
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "add-symbol-file %a 0x%p\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
-#else
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
-#endif
+ #else
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
+ #endif
} else {
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Loading driver at 0x%11p EntryPoint=0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress, FUNCTION_ENTRY_POINT (ImageContext->EntryPoint)));
}
}
-
-
/**
Performs additional actions just before a PE/COFF image is unloaded. Any resources
that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.
@@ -115,21 +111,21 @@ PeCoffLoaderUnloadImageExtraAction ( IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
-#if !defined(MDEPKG_NDEBUG)
- CHAR8 Temp[512];
-#endif
+ #if !defined (MDEPKG_NDEBUG)
+ CHAR8 Temp[512];
+ #endif
if (ImageContext->PdbPointer) {
-#ifdef __CC_ARM
+ #ifdef __CC_ARM
// Print out the command for the RVD debugger to load symbols for this image
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "unload symbols_only %a\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp))));
-#elif __GNUC__
+ #elif __GNUC__
// This may not work correctly if you generate PE/COFF directly as then the Offset would not be required
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "remove-symbol-file %a 0x%08x\n", DeCygwinPathIfNeeded (ImageContext->PdbPointer, Temp, sizeof (Temp)), (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders)));
-#else
+ #else
DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading %a\n", ImageContext->PdbPointer));
-#endif
+ #endif
} else {
- DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading driver at 0x%11p\n", (VOID *)(UINTN) ImageContext->ImageAddress));
+ DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Unloading driver at 0x%11p\n", (VOID *)(UINTN)ImageContext->ImageAddress));
}
}
diff --git a/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c b/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c index 2bb0888b43..f2bca5d740 100644 --- a/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c +++ b/ArmPkg/Library/DefaultExceptionHandlerLib/AArch64/DefaultExceptionHandler.c @@ -22,14 +22,14 @@ #include <Protocol/DebugSupport.h>
#include <Protocol/LoadedImage.h>
-STATIC CHAR8 *gExceptionTypeString[] = {
+STATIC CHAR8 *gExceptionTypeString[] = {
"Synchronous",
"IRQ",
"FIQ",
"SError"
};
-STATIC BOOLEAN mRecursiveException;
+STATIC BOOLEAN mRecursiveException;
CHAR8 *
GetImageName (
@@ -41,47 +41,79 @@ GetImageName ( STATIC
VOID
DescribeInstructionOrDataAbort (
- IN CHAR8 *AbortType,
- IN UINTN Iss
+ IN CHAR8 *AbortType,
+ IN UINTN Iss
)
{
- CHAR8 *AbortCause;
+ CHAR8 *AbortCause;
switch (Iss & 0x3f) {
- case 0x0: AbortCause = "Address size fault, zeroth level of translation or translation table base register"; break;
- case 0x1: AbortCause = "Address size fault, first level"; break;
- case 0x2: AbortCause = "Address size fault, second level"; break;
- case 0x3: AbortCause = "Address size fault, third level"; break;
- case 0x4: AbortCause = "Translation fault, zeroth level"; break;
- case 0x5: AbortCause = "Translation fault, first level"; break;
- case 0x6: AbortCause = "Translation fault, second level"; break;
- case 0x7: AbortCause = "Translation fault, third level"; break;
- case 0x9: AbortCause = "Access flag fault, first level"; break;
- case 0xa: AbortCause = "Access flag fault, second level"; break;
- case 0xb: AbortCause = "Access flag fault, third level"; break;
- case 0xd: AbortCause = "Permission fault, first level"; break;
- case 0xe: AbortCause = "Permission fault, second level"; break;
- case 0xf: AbortCause = "Permission fault, third level"; break;
- case 0x10: AbortCause = "Synchronous external abort"; break;
- case 0x18: AbortCause = "Synchronous parity error on memory access"; break;
- case 0x11: AbortCause = "Asynchronous external abort"; break;
- case 0x19: AbortCause = "Asynchronous parity error on memory access"; break;
- case 0x14: AbortCause = "Synchronous external abort on translation table walk, zeroth level"; break;
- case 0x15: AbortCause = "Synchronous external abort on translation table walk, first level"; break;
- case 0x16: AbortCause = "Synchronous external abort on translation table walk, second level"; break;
- case 0x17: AbortCause = "Synchronous external abort on translation table walk, third level"; break;
- case 0x1c: AbortCause = "Synchronous parity error on memory access on translation table walk, zeroth level"; break;
- case 0x1d: AbortCause = "Synchronous parity error on memory access on translation table walk, first level"; break;
- case 0x1e: AbortCause = "Synchronous parity error on memory access on translation table walk, second level"; break;
- case 0x1f: AbortCause = "Synchronous parity error on memory access on translation table walk, third level"; break;
- case 0x21: AbortCause = "Alignment fault"; break;
- case 0x22: AbortCause = "Debug event"; break;
- case 0x30: AbortCause = "TLB conflict abort"; break;
+ case 0x0: AbortCause = "Address size fault, zeroth level of translation or translation table base register";
+ break;
+ case 0x1: AbortCause = "Address size fault, first level";
+ break;
+ case 0x2: AbortCause = "Address size fault, second level";
+ break;
+ case 0x3: AbortCause = "Address size fault, third level";
+ break;
+ case 0x4: AbortCause = "Translation fault, zeroth level";
+ break;
+ case 0x5: AbortCause = "Translation fault, first level";
+ break;
+ case 0x6: AbortCause = "Translation fault, second level";
+ break;
+ case 0x7: AbortCause = "Translation fault, third level";
+ break;
+ case 0x9: AbortCause = "Access flag fault, first level";
+ break;
+ case 0xa: AbortCause = "Access flag fault, second level";
+ break;
+ case 0xb: AbortCause = "Access flag fault, third level";
+ break;
+ case 0xd: AbortCause = "Permission fault, first level";
+ break;
+ case 0xe: AbortCause = "Permission fault, second level";
+ break;
+ case 0xf: AbortCause = "Permission fault, third level";
+ break;
+ case 0x10: AbortCause = "Synchronous external abort";
+ break;
+ case 0x18: AbortCause = "Synchronous parity error on memory access";
+ break;
+ case 0x11: AbortCause = "Asynchronous external abort";
+ break;
+ case 0x19: AbortCause = "Asynchronous parity error on memory access";
+ break;
+ case 0x14: AbortCause = "Synchronous external abort on translation table walk, zeroth level";
+ break;
+ case 0x15: AbortCause = "Synchronous external abort on translation table walk, first level";
+ break;
+ case 0x16: AbortCause = "Synchronous external abort on translation table walk, second level";
+ break;
+ case 0x17: AbortCause = "Synchronous external abort on translation table walk, third level";
+ break;
+ case 0x1c: AbortCause = "Synchronous parity error on memory access on translation table walk, zeroth level";
+ break;
+ case 0x1d: AbortCause = "Synchronous parity error on memory access on translation table walk, first level";
+ break;
+ case 0x1e: AbortCause = "Synchronous parity error on memory access on translation table walk, second level";
+ break;
+ case 0x1f: AbortCause = "Synchronous parity error on memory access on translation table walk, third level";
+ break;
+ case 0x21: AbortCause = "Alignment fault";
+ break;
+ case 0x22: AbortCause = "Debug event";
+ break;
+ case 0x30: AbortCause = "TLB conflict abort";
+ break;
case 0x33:
- case 0x34: AbortCause = "IMPLEMENTATION DEFINED"; break;
+ case 0x34: AbortCause = "IMPLEMENTATION DEFINED";
+ break;
case 0x35:
- case 0x36: AbortCause = "Domain fault"; break;
- default: AbortCause = ""; break;
+ case 0x36: AbortCause = "Domain fault";
+ break;
+ default: AbortCause = "";
+ break;
}
DEBUG ((DEBUG_ERROR, "\n%a: %a\n", AbortType, AbortCause));
@@ -90,24 +122,29 @@ DescribeInstructionOrDataAbort ( STATIC
VOID
DescribeExceptionSyndrome (
- IN UINT32 Esr
+ IN UINT32 Esr
)
{
- CHAR8 *Message;
- UINTN Ec;
- UINTN Iss;
+ CHAR8 *Message;
+ UINTN Ec;
+ UINTN Iss;
- Ec = Esr >> 26;
+ Ec = Esr >> 26;
Iss = Esr & 0x00ffffff;
switch (Ec) {
- case 0x15: Message = "SVC executed in AArch64"; break;
+ case 0x15: Message = "SVC executed in AArch64";
+ break;
case 0x20:
- case 0x21: DescribeInstructionOrDataAbort ("Instruction abort", Iss); return;
- case 0x22: Message = "PC alignment fault"; break;
- case 0x23: Message = "SP alignment fault"; break;
+ case 0x21: DescribeInstructionOrDataAbort ("Instruction abort", Iss);
+ return;
+ case 0x22: Message = "PC alignment fault";
+ break;
+ case 0x23: Message = "SP alignment fault";
+ break;
case 0x24:
- case 0x25: DescribeInstructionOrDataAbort ("Data abort", Iss); return;
+ case 0x25: DescribeInstructionOrDataAbort ("Data abort", Iss);
+ return;
default: return;
}
@@ -118,20 +155,22 @@ DescribeExceptionSyndrome ( STATIC
CONST CHAR8 *
BaseName (
- IN CONST CHAR8 *FullName
+ IN CONST CHAR8 *FullName
)
{
- CONST CHAR8 *Str;
+ CONST CHAR8 *Str;
Str = FullName + AsciiStrLen (FullName);
while (--Str > FullName) {
- if (*Str == '/' || *Str == '\\') {
+ if ((*Str == '/') || (*Str == '\\')) {
return Str + 1;
}
}
+
return Str;
}
+
#endif
/**
@@ -145,8 +184,8 @@ BaseName ( **/
VOID
DefaultExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
CHAR8 Buffer[100];
@@ -154,75 +193,93 @@ DefaultExceptionHandler ( INT32 Offset;
if (mRecursiveException) {
- STATIC CHAR8 CONST Message[] = "\nRecursive exception occurred while dumping the CPU state\n";
+ STATIC CHAR8 CONST Message[] = "\nRecursive exception occurred while dumping the CPU state\n";
SerialPortWrite ((UINT8 *)Message, sizeof Message - 1);
if (gST->ConOut != NULL) {
AsciiPrint (Message);
}
+
CpuDeadLoop ();
}
+
mRecursiveException = TRUE;
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"\n\n%a Exception at 0x%016lx\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextAArch64->ELR);
- SerialPortWrite ((UINT8 *) Buffer, CharCount);
+ CharCount = AsciiSPrint (Buffer, sizeof (Buffer), "\n\n%a Exception at 0x%016lx\n", gExceptionTypeString[ExceptionType], SystemContext.SystemContextAArch64->ELR);
+ SerialPortWrite ((UINT8 *)Buffer, CharCount);
if (gST->ConOut != NULL) {
AsciiPrint (Buffer);
}
DEBUG_CODE_BEGIN ();
- CHAR8 *Pdb, *PrevPdb;
- UINTN ImageBase;
- UINTN PeCoffSizeOfHeader;
- UINT64 *Fp;
- UINT64 RootFp[2];
- UINTN Idx;
+ CHAR8 *Pdb, *PrevPdb;
+ UINTN ImageBase;
+ UINTN PeCoffSizeOfHeader;
+ UINT64 *Fp;
+ UINT64 RootFp[2];
+ UINTN Idx;
+
+ PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);
+ if (Pdb != NULL) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "PC 0x%012lx (0x%012lx+0x%08x) [ 0] %a\n",
+ SystemContext.SystemContextAArch64->ELR,
+ ImageBase,
+ SystemContext.SystemContextAArch64->ELR - ImageBase,
+ BaseName (Pdb)
+ ));
+ } else {
+ DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", SystemContext.SystemContextAArch64->ELR));
+ }
- PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);
- if (Pdb != NULL) {
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx (0x%012lx+0x%08x) [ 0] %a\n",
- SystemContext.SystemContextAArch64->ELR, ImageBase,
- SystemContext.SystemContextAArch64->ELR - ImageBase, BaseName (Pdb)));
- } else {
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", SystemContext.SystemContextAArch64->ELR));
- }
+ if ((UINT64 *)SystemContext.SystemContextAArch64->FP != 0) {
+ Idx = 0;
- if ((UINT64 *)SystemContext.SystemContextAArch64->FP != 0) {
- Idx = 0;
+ RootFp[0] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[0];
+ RootFp[1] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[1];
+ if (RootFp[1] != SystemContext.SystemContextAArch64->LR) {
+ RootFp[0] = SystemContext.SystemContextAArch64->FP;
+ RootFp[1] = SystemContext.SystemContextAArch64->LR;
+ }
- RootFp[0] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[0];
- RootFp[1] = ((UINT64 *)SystemContext.SystemContextAArch64->FP)[1];
- if (RootFp[1] != SystemContext.SystemContextAArch64->LR) {
- RootFp[0] = SystemContext.SystemContextAArch64->FP;
- RootFp[1] = SystemContext.SystemContextAArch64->LR;
- }
- for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {
- Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);
- if (Pdb != NULL) {
- if (Pdb != PrevPdb) {
- Idx++;
- PrevPdb = Pdb;
- }
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx (0x%012lx+0x%08x) [% 2d] %a\n",
- Fp[1], ImageBase, Fp[1] - ImageBase, Idx, BaseName (Pdb)));
- } else {
- DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", Fp[1]));
- }
- }
- PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);
+ for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {
+ Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);
if (Pdb != NULL) {
- DEBUG ((DEBUG_ERROR, "\n[ 0] %a\n", Pdb));
- }
-
- Idx = 0;
- for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {
- Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);
- if (Pdb != NULL && Pdb != PrevPdb) {
- DEBUG ((DEBUG_ERROR, "[% 2d] %a\n", ++Idx, Pdb));
+ if (Pdb != PrevPdb) {
+ Idx++;
PrevPdb = Pdb;
}
+
+ DEBUG ((
+ DEBUG_ERROR,
+ "PC 0x%012lx (0x%012lx+0x%08x) [% 2d] %a\n",
+ Fp[1],
+ ImageBase,
+ Fp[1] - ImageBase,
+ Idx,
+ BaseName (Pdb)
+ ));
+ } else {
+ DEBUG ((DEBUG_ERROR, "PC 0x%012lx\n", Fp[1]));
+ }
+ }
+
+ PrevPdb = Pdb = GetImageName (SystemContext.SystemContextAArch64->ELR, &ImageBase, &PeCoffSizeOfHeader);
+ if (Pdb != NULL) {
+ DEBUG ((DEBUG_ERROR, "\n[ 0] %a\n", Pdb));
+ }
+
+ Idx = 0;
+ for (Fp = RootFp; Fp[0] != 0; Fp = (UINT64 *)Fp[0]) {
+ Pdb = GetImageName (Fp[1], &ImageBase, &PeCoffSizeOfHeader);
+ if ((Pdb != NULL) && (Pdb != PrevPdb)) {
+ DEBUG ((DEBUG_ERROR, "[% 2d] %a\n", ++Idx, Pdb));
+ PrevPdb = Pdb;
}
}
+ }
+
DEBUG_CODE_END ();
DEBUG ((DEBUG_ERROR, "\n X0 0x%016lx X1 0x%016lx X2 0x%016lx X3 0x%016lx\n", SystemContext.SystemContextAArch64->X0, SystemContext.SystemContextAArch64->X1, SystemContext.SystemContextAArch64->X2, SystemContext.SystemContextAArch64->X3));
@@ -255,19 +312,22 @@ DefaultExceptionHandler ( DEBUG ((DEBUG_ERROR, "\n SP 0x%016lx ELR 0x%016lx SPSR 0x%08lx FPSR 0x%08lx\n ESR 0x%08lx FAR 0x%016lx\n", SystemContext.SystemContextAArch64->SP, SystemContext.SystemContextAArch64->ELR, SystemContext.SystemContextAArch64->SPSR, SystemContext.SystemContextAArch64->FPSR, SystemContext.SystemContextAArch64->ESR, SystemContext.SystemContextAArch64->FAR));
- DEBUG ((DEBUG_ERROR, "\n ESR : EC 0x%02x IL 0x%x ISS 0x%08x\n", (SystemContext.SystemContextAArch64->ESR & 0xFC000000) >> 26, (SystemContext.SystemContextAArch64->ESR >> 25) & 0x1, SystemContext.SystemContextAArch64->ESR & 0x1FFFFFF ));
+ DEBUG ((DEBUG_ERROR, "\n ESR : EC 0x%02x IL 0x%x ISS 0x%08x\n", (SystemContext.SystemContextAArch64->ESR & 0xFC000000) >> 26, (SystemContext.SystemContextAArch64->ESR >> 25) & 0x1, SystemContext.SystemContextAArch64->ESR & 0x1FFFFFF));
DescribeExceptionSyndrome (SystemContext.SystemContextAArch64->ESR);
DEBUG ((DEBUG_ERROR, "\nStack dump:\n"));
for (Offset = -256; Offset < 256; Offset += 32) {
- DEBUG ((DEBUG_ERROR, "%c %013lx: %016lx %016lx %016lx %016lx\n",
+ DEBUG ((
+ DEBUG_ERROR,
+ "%c %013lx: %016lx %016lx %016lx %016lx\n",
Offset == 0 ? '>' : ' ',
SystemContext.SystemContextAArch64->SP + Offset,
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset),
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 8),
*(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 16),
- *(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 24)));
+ *(UINT64 *)(SystemContext.SystemContextAArch64->SP + Offset + 24)
+ ));
}
ASSERT (FALSE);
diff --git a/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c b/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c index 26f552622d..13b321e456 100644 --- a/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c +++ b/ArmPkg/Library/DefaultExceptionHandlerLib/Arm/DefaultExceptionHandler.c @@ -27,14 +27,14 @@ // The number of elements in a CHAR8 array, including the terminating NUL, that
// is meant to hold the string rendering of the CPSR.
//
-#define CPSR_STRING_SIZE 32
+#define CPSR_STRING_SIZE 32
typedef struct {
- UINT32 BIT;
- CHAR8 Char;
+ UINT32 BIT;
+ CHAR8 Char;
} CPSR_CHAR;
-STATIC CONST CPSR_CHAR mCpsrChar[] = {
+STATIC CONST CPSR_CHAR mCpsrChar[] = {
{ 31, 'n' },
{ 30, 'z' },
{ 29, 'c' },
@@ -72,9 +72,9 @@ CpsrString ( OUT CHAR8 *ReturnStr
)
{
- UINTN Index;
- CHAR8* Str;
- CHAR8* ModeStr;
+ UINTN Index;
+ CHAR8 *Str;
+ CHAR8 *ModeStr;
Str = ReturnStr;
@@ -87,37 +87,37 @@ CpsrString ( }
*Str++ = '_';
- *Str = '\0';
+ *Str = '\0';
switch (Cpsr & 0x1f) {
- case 0x10:
- ModeStr = "usr";
- break;
- case 0x011:
- ModeStr = "fiq";
- break;
- case 0x12:
- ModeStr = "irq";
- break;
- case 0x13:
- ModeStr = "svc";
- break;
- case 0x16:
- ModeStr = "mon";
- break;
- case 0x17:
- ModeStr = "abt";
- break;
- case 0x1b:
- ModeStr = "und";
- break;
- case 0x1f:
- ModeStr = "sys";
- break;
-
- default:
- ModeStr = "???";
- break;
+ case 0x10:
+ ModeStr = "usr";
+ break;
+ case 0x011:
+ ModeStr = "fiq";
+ break;
+ case 0x12:
+ ModeStr = "irq";
+ break;
+ case 0x13:
+ ModeStr = "svc";
+ break;
+ case 0x16:
+ ModeStr = "mon";
+ break;
+ case 0x17:
+ ModeStr = "abt";
+ break;
+ case 0x1b:
+ ModeStr = "und";
+ break;
+ case 0x1f:
+ ModeStr = "sys";
+ break;
+
+ default:
+ ModeStr = "???";
+ break;
}
//
@@ -131,31 +131,47 @@ FaultStatusToString ( IN UINT32 Status
)
{
- CHAR8 *FaultSource;
+ CHAR8 *FaultSource;
switch (Status) {
- case 0x01: FaultSource = "Alignment fault"; break;
- case 0x02: FaultSource = "Debug event fault"; break;
- case 0x03: FaultSource = "Access Flag fault on Section"; break;
- case 0x04: FaultSource = "Cache maintenance operation fault[2]"; break;
- case 0x05: FaultSource = "Translation fault on Section"; break;
- case 0x06: FaultSource = "Access Flag fault on Page"; break;
- case 0x07: FaultSource = "Translation fault on Page"; break;
- case 0x08: FaultSource = "Precise External Abort"; break;
- case 0x09: FaultSource = "Domain fault on Section"; break;
- case 0x0b: FaultSource = "Domain fault on Page"; break;
- case 0x0c: FaultSource = "External abort on translation, first level"; break;
- case 0x0d: FaultSource = "Permission fault on Section"; break;
- case 0x0e: FaultSource = "External abort on translation, second level"; break;
- case 0x0f: FaultSource = "Permission fault on Page"; break;
- case 0x16: FaultSource = "Imprecise External Abort"; break;
- default: FaultSource = "No function"; break;
- }
+ case 0x01: FaultSource = "Alignment fault";
+ break;
+ case 0x02: FaultSource = "Debug event fault";
+ break;
+ case 0x03: FaultSource = "Access Flag fault on Section";
+ break;
+ case 0x04: FaultSource = "Cache maintenance operation fault[2]";
+ break;
+ case 0x05: FaultSource = "Translation fault on Section";
+ break;
+ case 0x06: FaultSource = "Access Flag fault on Page";
+ break;
+ case 0x07: FaultSource = "Translation fault on Page";
+ break;
+ case 0x08: FaultSource = "Precise External Abort";
+ break;
+ case 0x09: FaultSource = "Domain fault on Section";
+ break;
+ case 0x0b: FaultSource = "Domain fault on Page";
+ break;
+ case 0x0c: FaultSource = "External abort on translation, first level";
+ break;
+ case 0x0d: FaultSource = "Permission fault on Section";
+ break;
+ case 0x0e: FaultSource = "External abort on translation, second level";
+ break;
+ case 0x0f: FaultSource = "Permission fault on Page";
+ break;
+ case 0x16: FaultSource = "Imprecise External Abort";
+ break;
+ default: FaultSource = "No function";
+ break;
+ }
return FaultSource;
}
-STATIC CHAR8 *gExceptionTypeString[] = {
+STATIC CHAR8 *gExceptionTypeString[] = {
"Reset",
"Undefined OpCode",
"SVC",
@@ -178,62 +194,68 @@ STATIC CHAR8 *gExceptionTypeString[] = { **/
VOID
DefaultExceptionHandler (
- IN EFI_EXCEPTION_TYPE ExceptionType,
- IN OUT EFI_SYSTEM_CONTEXT SystemContext
+ IN EFI_EXCEPTION_TYPE ExceptionType,
+ IN OUT EFI_SYSTEM_CONTEXT SystemContext
)
{
- CHAR8 Buffer[100];
- UINTN CharCount;
- UINT32 DfsrStatus;
- UINT32 IfsrStatus;
- BOOLEAN DfsrWrite;
- UINT32 PcAdjust;
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+ UINT32 DfsrStatus;
+ UINT32 IfsrStatus;
+ BOOLEAN DfsrWrite;
+ UINT32 PcAdjust;
PcAdjust = 0;
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"\n%a Exception PC at 0x%08x CPSR 0x%08x ",
- gExceptionTypeString[ExceptionType], SystemContext.SystemContextArm->PC, SystemContext.SystemContextArm->CPSR);
+ CharCount = AsciiSPrint (
+ Buffer,
+ sizeof (Buffer),
+ "\n%a Exception PC at 0x%08x CPSR 0x%08x ",
+ gExceptionTypeString[ExceptionType],
+ SystemContext.SystemContextArm->PC,
+ SystemContext.SystemContextArm->CPSR
+ );
SerialPortWrite ((UINT8 *)Buffer, CharCount);
if (gST->ConOut != NULL) {
AsciiPrint (Buffer);
}
DEBUG_CODE_BEGIN ();
- CHAR8 *Pdb;
- UINT32 ImageBase;
- UINT32 PeCoffSizeOfHeader;
- UINT32 Offset;
- CHAR8 CpsrStr[CPSR_STRING_SIZE]; // char per bit. Lower 5-bits are mode
+ CHAR8 *Pdb;
+ UINT32 ImageBase;
+ UINT32 PeCoffSizeOfHeader;
+ UINT32 Offset;
+ CHAR8 CpsrStr[CPSR_STRING_SIZE]; // char per bit. Lower 5-bits are mode
// that is a 3 char string
- CHAR8 Buffer[80];
- UINT8 *DisAsm;
- UINT32 ItBlock;
-
- CpsrString (SystemContext.SystemContextArm->CPSR, CpsrStr);
- DEBUG ((DEBUG_ERROR, "%a\n", CpsrStr));
-
- Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);
- Offset = SystemContext.SystemContextArm->PC - ImageBase;
- if (Pdb != NULL) {
- DEBUG ((DEBUG_ERROR, "%a\n", Pdb));
-
- //
- // A PE/COFF image loads its headers into memory so the headers are
- // included in the linked addresses. ELF and Mach-O images do not
- // include the headers so the first byte of the image is usually
- // text (code). If you look at link maps from ELF or Mach-O images
- // you need to subtract out the size of the PE/COFF header to get
- // get the offset that matches the link map.
- //
- DEBUG ((DEBUG_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));
-
- // If we come from an image it is safe to show the instruction. We know it should not fault
- DisAsm = (UINT8 *)(UINTN)SystemContext.SystemContextArm->PC;
- ItBlock = 0;
- DisassembleInstruction (&DisAsm, (SystemContext.SystemContextArm->CPSR & BIT5) == BIT5, TRUE, &ItBlock, Buffer, sizeof (Buffer));
- DEBUG ((DEBUG_ERROR, "\n%a", Buffer));
-
- switch (ExceptionType) {
+ CHAR8 Buffer[80];
+ UINT8 *DisAsm;
+ UINT32 ItBlock;
+
+ CpsrString (SystemContext.SystemContextArm->CPSR, CpsrStr);
+ DEBUG ((DEBUG_ERROR, "%a\n", CpsrStr));
+
+ Pdb = GetImageName (SystemContext.SystemContextArm->PC, &ImageBase, &PeCoffSizeOfHeader);
+ Offset = SystemContext.SystemContextArm->PC - ImageBase;
+ if (Pdb != NULL) {
+ DEBUG ((DEBUG_ERROR, "%a\n", Pdb));
+
+ //
+ // A PE/COFF image loads its headers into memory so the headers are
+ // included in the linked addresses. ELF and Mach-O images do not
+ // include the headers so the first byte of the image is usually
+ // text (code). If you look at link maps from ELF or Mach-O images
+ // you need to subtract out the size of the PE/COFF header to get
+ // get the offset that matches the link map.
+ //
+ DEBUG ((DEBUG_ERROR, "loaded at 0x%08x (PE/COFF offset) 0x%x (ELF or Mach-O offset) 0x%x", ImageBase, Offset, Offset - PeCoffSizeOfHeader));
+
+ // If we come from an image it is safe to show the instruction. We know it should not fault
+ DisAsm = (UINT8 *)(UINTN)SystemContext.SystemContextArm->PC;
+ ItBlock = 0;
+ DisassembleInstruction (&DisAsm, (SystemContext.SystemContextArm->CPSR & BIT5) == BIT5, TRUE, &ItBlock, Buffer, sizeof (Buffer));
+ DEBUG ((DEBUG_ERROR, "\n%a", Buffer));
+
+ switch (ExceptionType) {
case EXCEPT_ARM_UNDEFINED_INSTRUCTION:
case EXCEPT_ARM_SOFTWARE_INTERRUPT:
case EXCEPT_ARM_PREFETCH_ABORT:
@@ -244,9 +266,9 @@ DefaultExceptionHandler ( default:
break;
- }
-
}
+ }
+
DEBUG_CODE_END ();
DEBUG ((DEBUG_ERROR, "\n R0 0x%08x R1 0x%08x R2 0x%08x R3 0x%08x\n", SystemContext.SystemContextArm->R0, SystemContext.SystemContextArm->R1, SystemContext.SystemContextArm->R2, SystemContext.SystemContextArm->R3));
DEBUG ((DEBUG_ERROR, " R4 0x%08x R5 0x%08x R6 0x%08x R7 0x%08x\n", SystemContext.SystemContextArm->R4, SystemContext.SystemContextArm->R5, SystemContext.SystemContextArm->R6, SystemContext.SystemContextArm->R7));
@@ -256,7 +278,7 @@ DefaultExceptionHandler ( // Bit10 is Status[4] Bit3:0 is Status[3:0]
DfsrStatus = (SystemContext.SystemContextArm->DFSR & 0xf) | ((SystemContext.SystemContextArm->DFSR >> 6) & 0x10);
- DfsrWrite = (SystemContext.SystemContextArm->DFSR & BIT11) != 0;
+ DfsrWrite = (SystemContext.SystemContextArm->DFSR & BIT11) != 0;
if (DfsrStatus != 0x00) {
DEBUG ((DEBUG_ERROR, " %a: %a 0x%08x\n", FaultStatusToString (DfsrStatus), DfsrWrite ? "write to" : "read from", SystemContext.SystemContextArm->DFAR));
}
diff --git a/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c b/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c index e9fea40382..752a763f04 100644 --- a/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c +++ b/ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerUefi.c @@ -33,11 +33,11 @@ GetImageName ( OUT UINTN *PeCoffSizeOfHeaders
)
{
- EFI_STATUS Status;
- EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugTableHeader;
- EFI_DEBUG_IMAGE_INFO *DebugTable;
- UINTN Entry;
- CHAR8 *Address;
+ EFI_STATUS Status;
+ EFI_DEBUG_IMAGE_INFO_TABLE_HEADER *DebugTableHeader;
+ EFI_DEBUG_IMAGE_INFO *DebugTable;
+ UINTN Entry;
+ CHAR8 *Address;
Status = EfiGetSystemConfigurationTable (&gEfiDebugImageInfoTableGuid, (VOID **)&DebugTableHeader);
if (EFI_ERROR (Status)) {
@@ -53,10 +53,12 @@ GetImageName ( for (Entry = 0; Entry < DebugTableHeader->TableSize; Entry++, DebugTable++) {
if (DebugTable->NormalImage != NULL) {
if ((DebugTable->NormalImage->ImageInfoType == EFI_DEBUG_IMAGE_INFO_TYPE_NORMAL) &&
- (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL)) {
+ (DebugTable->NormalImage->LoadedImageProtocolInstance != NULL))
+ {
if ((Address >= (CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase) &&
- (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize))) {
- *ImageBase = (UINTN)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
+ (Address <= ((CHAR8 *)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase + DebugTable->NormalImage->LoadedImageProtocolInstance->ImageSize)))
+ {
+ *ImageBase = (UINTN)DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase;
*PeCoffSizeOfHeaders = PeCoffGetSizeOfHeaders ((VOID *)(UINTN)*ImageBase);
return PeCoffLoaderGetPdbPointer (DebugTable->NormalImage->LoadedImageProtocolInstance->ImageBase);
}
@@ -66,4 +68,3 @@ GetImageName ( return NULL;
}
-
diff --git a/ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBm.c b/ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBm.c index 3295c5a070..5a44af5a75 100644 --- a/ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBm.c +++ b/ArmPkg/Library/LinuxBootBootManagerLib/LinuxBootBm.c @@ -38,19 +38,19 @@ STATIC
VOID
PlatformRegisterFvBootOption (
- CONST EFI_GUID *FileGuid,
- CHAR16 *Description,
- UINT32 Attributes
+ CONST EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes
)
{
- EFI_STATUS Status;
- INTN OptionIndex;
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN BootOptionCount;
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_STATUS Status;
+ INTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
Status = gBS->HandleProtocol (
gImageHandle,
@@ -96,6 +96,7 @@ PlatformRegisterFvBootOption ( Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
ASSERT_EFI_ERROR (Status);
}
+
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
}
@@ -136,7 +137,7 @@ PlatformBootManagerAfterConsole ( VOID
)
{
- EFI_GUID LinuxBootFileGuid;
+ EFI_GUID LinuxBootFileGuid;
CopyGuid (&LinuxBootFileGuid, PcdGetPtr (PcdLinuxBootFileGuid));
@@ -163,7 +164,7 @@ PlatformBootManagerAfterConsole ( VOID
EFIAPI
PlatformBootManagerWaitCallback (
- UINT16 TimeoutRemain
+ UINT16 TimeoutRemain
)
{
return;
diff --git a/ArmPkg/Library/OpteeLib/Optee.c b/ArmPkg/Library/OpteeLib/Optee.c index bedb2edbb3..48e33cb3d5 100644 --- a/ArmPkg/Library/OpteeLib/Optee.c +++ b/ArmPkg/Library/OpteeLib/Optee.c @@ -20,7 +20,7 @@ #include <OpteeSmc.h>
#include <Uefi.h>
-STATIC OPTEE_SHARED_MEMORY_INFORMATION OpteeSharedMemoryInformation = { 0 };
+STATIC OPTEE_SHARED_MEMORY_INFORMATION OpteeSharedMemoryInformation = { 0 };
/**
Check for OP-TEE presence.
@@ -31,7 +31,7 @@ IsOpteePresent ( VOID
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));
// Send a Trusted OS Calls UID command
@@ -41,7 +41,8 @@ IsOpteePresent ( if ((ArmSmcArgs.Arg0 == OPTEE_OS_UID0) &&
(ArmSmcArgs.Arg1 == OPTEE_OS_UID1) &&
(ArmSmcArgs.Arg2 == OPTEE_OS_UID2) &&
- (ArmSmcArgs.Arg3 == OPTEE_OS_UID3)) {
+ (ArmSmcArgs.Arg3 == OPTEE_OS_UID3))
+ {
return TRUE;
} else {
return FALSE;
@@ -54,12 +55,12 @@ OpteeSharedMemoryRemap ( VOID
)
{
- ARM_SMC_ARGS ArmSmcArgs;
- EFI_PHYSICAL_ADDRESS PhysicalAddress;
- EFI_PHYSICAL_ADDRESS Start;
- EFI_PHYSICAL_ADDRESS End;
- EFI_STATUS Status;
- UINTN Size;
+ ARM_SMC_ARGS ArmSmcArgs;
+ EFI_PHYSICAL_ADDRESS PhysicalAddress;
+ EFI_PHYSICAL_ADDRESS Start;
+ EFI_PHYSICAL_ADDRESS End;
+ EFI_STATUS Status;
+ UINTN Size;
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));
ArmSmcArgs.Arg0 = OPTEE_SMC_GET_SHARED_MEMORY_CONFIG;
@@ -75,10 +76,10 @@ OpteeSharedMemoryRemap ( return EFI_UNSUPPORTED;
}
- Start = (ArmSmcArgs.Arg1 + SIZE_4KB - 1) & ~(SIZE_4KB - 1);
- End = (ArmSmcArgs.Arg1 + ArmSmcArgs.Arg2) & ~(SIZE_4KB - 1);
+ Start = (ArmSmcArgs.Arg1 + SIZE_4KB - 1) & ~(SIZE_4KB - 1);
+ End = (ArmSmcArgs.Arg1 + ArmSmcArgs.Arg2) & ~(SIZE_4KB - 1);
PhysicalAddress = Start;
- Size = End - Start;
+ Size = End - Start;
if (Size < SIZE_4KB) {
DEBUG ((DEBUG_WARN, "OP-TEE shared memory too small\n"));
@@ -102,7 +103,7 @@ OpteeInit ( VOID
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
if (!IsOpteePresent ()) {
DEBUG ((DEBUG_WARN, "OP-TEE not present\n"));
@@ -121,7 +122,7 @@ OpteeInit ( STATIC
BOOLEAN
IsOpteeSmcReturnRpc (
- UINT32 Return
+ UINT32 Return
)
{
return (Return != OPTEE_SMC_RETURN_UNKNOWN_FUNCTION) &&
@@ -140,10 +141,10 @@ IsOpteeSmcReturnRpc ( STATIC
UINT32
OpteeCallWithArg (
- IN UINT64 PhysicalArg
+ IN UINT64 PhysicalArg
)
{
- ARM_SMC_ARGS ArmSmcArgs;
+ ARM_SMC_ARGS ArmSmcArgs;
ZeroMem (&ArmSmcArgs, sizeof (ARM_SMC_ARGS));
ArmSmcArgs.Arg0 = OPTEE_SMC_CALL_WITH_ARG;
@@ -155,18 +156,18 @@ OpteeCallWithArg ( if (IsOpteeSmcReturnRpc (ArmSmcArgs.Arg0)) {
switch (ArmSmcArgs.Arg0) {
- case OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT:
- //
- // A foreign interrupt was raised while secure world was
- // executing, since they are handled in UEFI a dummy RPC is
- // performed to let UEFI take the interrupt through the normal
- // vector.
- //
- break;
-
- default:
- // Do nothing in case RPC is not implemented.
- break;
+ case OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT:
+ //
+ // A foreign interrupt was raised while secure world was
+ // executing, since they are handled in UEFI a dummy RPC is
+ // performed to let UEFI take the interrupt through the normal
+ // vector.
+ //
+ break;
+
+ default:
+ // Do nothing in case RPC is not implemented.
+ break;
}
ArmSmcArgs.Arg0 = OPTEE_SMC_RETURN_FROM_RPC;
@@ -181,8 +182,8 @@ OpteeCallWithArg ( STATIC
VOID
EfiGuidToRfc4122Uuid (
- OUT RFC4122_UUID *Rfc4122Uuid,
- IN EFI_GUID *Guid
+ OUT RFC4122_UUID *Rfc4122Uuid,
+ IN EFI_GUID *Guid
)
{
Rfc4122Uuid->Data1 = SwapBytes32 (Guid->Data1);
@@ -194,10 +195,10 @@ EfiGuidToRfc4122Uuid ( EFI_STATUS
EFIAPI
OpteeOpenSession (
- IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
+ IN OUT OPTEE_OPEN_SESSION_ARG *OpenSessionArg
)
{
- OPTEE_MESSAGE_ARG *MessageArg;
+ OPTEE_MESSAGE_ARG *MessageArg;
MessageArg = NULL;
@@ -229,12 +230,12 @@ OpteeOpenSession ( MessageArg->NumParams = 2;
if (OpteeCallWithArg ((UINTN)MessageArg) != 0) {
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}
- OpenSessionArg->Session = MessageArg->Session;
- OpenSessionArg->Return = MessageArg->Return;
+ OpenSessionArg->Session = MessageArg->Session;
+ OpenSessionArg->Return = MessageArg->Return;
OpenSessionArg->ReturnOrigin = MessageArg->ReturnOrigin;
return EFI_SUCCESS;
@@ -243,10 +244,10 @@ OpteeOpenSession ( EFI_STATUS
EFIAPI
OpteeCloseSession (
- IN UINT32 Session
+ IN UINT32 Session
)
{
- OPTEE_MESSAGE_ARG *MessageArg;
+ OPTEE_MESSAGE_ARG *MessageArg;
MessageArg = NULL;
@@ -269,70 +270,70 @@ OpteeCloseSession ( STATIC
EFI_STATUS
OpteeToMessageParam (
- OUT OPTEE_MESSAGE_PARAM *MessageParams,
- IN UINT32 NumParams,
- IN OPTEE_MESSAGE_PARAM *InParams
+ OUT OPTEE_MESSAGE_PARAM *MessageParams,
+ IN UINT32 NumParams,
+ IN OPTEE_MESSAGE_PARAM *InParams
)
{
- UINT32 Idx;
- UINTN ParamSharedMemoryAddress;
- UINTN SharedMemorySize;
- UINTN Size;
+ UINT32 Idx;
+ UINTN ParamSharedMemoryAddress;
+ UINTN SharedMemorySize;
+ UINTN Size;
Size = (sizeof (OPTEE_MESSAGE_ARG) + sizeof (UINT64) - 1) &
- ~(sizeof (UINT64) - 1);
+ ~(sizeof (UINT64) - 1);
ParamSharedMemoryAddress = OpteeSharedMemoryInformation.Base + Size;
- SharedMemorySize = OpteeSharedMemoryInformation.Size - Size;
+ SharedMemorySize = OpteeSharedMemoryInformation.Size - Size;
for (Idx = 0; Idx < NumParams; Idx++) {
- CONST OPTEE_MESSAGE_PARAM *InParam;
- OPTEE_MESSAGE_PARAM *MessageParam;
- UINT32 Attribute;
+ CONST OPTEE_MESSAGE_PARAM *InParam;
+ OPTEE_MESSAGE_PARAM *MessageParam;
+ UINT32 Attribute;
- InParam = InParams + Idx;
+ InParam = InParams + Idx;
MessageParam = MessageParams + Idx;
- Attribute = InParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;
+ Attribute = InParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;
switch (Attribute) {
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:
- MessageParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;
- ZeroMem (&MessageParam->Union, sizeof (MessageParam->Union));
- break;
-
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:
- MessageParam->Attribute = Attribute;
- MessageParam->Union.Value.A = InParam->Union.Value.A;
- MessageParam->Union.Value.B = InParam->Union.Value.B;
- MessageParam->Union.Value.C = InParam->Union.Value.C;
- break;
-
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:
- MessageParam->Attribute = Attribute;
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:
+ MessageParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;
+ ZeroMem (&MessageParam->Union, sizeof (MessageParam->Union));
+ break;
- if (InParam->Union.Memory.Size > SharedMemorySize) {
- return EFI_OUT_OF_RESOURCES;
- }
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:
+ MessageParam->Attribute = Attribute;
+ MessageParam->Union.Value.A = InParam->Union.Value.A;
+ MessageParam->Union.Value.B = InParam->Union.Value.B;
+ MessageParam->Union.Value.C = InParam->Union.Value.C;
+ break;
- CopyMem (
- (VOID *)ParamSharedMemoryAddress,
- (VOID *)(UINTN)InParam->Union.Memory.BufferAddress,
- InParam->Union.Memory.Size
- );
- MessageParam->Union.Memory.BufferAddress = (UINT64)ParamSharedMemoryAddress;
- MessageParam->Union.Memory.Size = InParam->Union.Memory.Size;
-
- Size = (InParam->Union.Memory.Size + sizeof (UINT64) - 1) &
- ~(sizeof (UINT64) - 1);
- ParamSharedMemoryAddress += Size;
- SharedMemorySize -= Size;
- break;
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:
+ MessageParam->Attribute = Attribute;
+
+ if (InParam->Union.Memory.Size > SharedMemorySize) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ CopyMem (
+ (VOID *)ParamSharedMemoryAddress,
+ (VOID *)(UINTN)InParam->Union.Memory.BufferAddress,
+ InParam->Union.Memory.Size
+ );
+ MessageParam->Union.Memory.BufferAddress = (UINT64)ParamSharedMemoryAddress;
+ MessageParam->Union.Memory.Size = InParam->Union.Memory.Size;
+
+ Size = (InParam->Union.Memory.Size + sizeof (UINT64) - 1) &
+ ~(sizeof (UINT64) - 1);
+ ParamSharedMemoryAddress += Size;
+ SharedMemorySize -= Size;
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
}
@@ -342,56 +343,56 @@ OpteeToMessageParam ( STATIC
EFI_STATUS
OpteeFromMessageParam (
- OUT OPTEE_MESSAGE_PARAM *OutParams,
- IN UINT32 NumParams,
- IN OPTEE_MESSAGE_PARAM *MessageParams
+ OUT OPTEE_MESSAGE_PARAM *OutParams,
+ IN UINT32 NumParams,
+ IN OPTEE_MESSAGE_PARAM *MessageParams
)
{
- UINT32 Idx;
+ UINT32 Idx;
for (Idx = 0; Idx < NumParams; Idx++) {
- OPTEE_MESSAGE_PARAM *OutParam;
- CONST OPTEE_MESSAGE_PARAM *MessageParam;
- UINT32 Attribute;
+ OPTEE_MESSAGE_PARAM *OutParam;
+ CONST OPTEE_MESSAGE_PARAM *MessageParam;
+ UINT32 Attribute;
- OutParam = OutParams + Idx;
+ OutParam = OutParams + Idx;
MessageParam = MessageParams + Idx;
- Attribute = MessageParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;
+ Attribute = MessageParam->Attribute & OPTEE_MESSAGE_ATTRIBUTE_TYPE_MASK;
switch (Attribute) {
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:
- OutParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;
- ZeroMem (&OutParam->Union, sizeof (OutParam->Union));
- break;
-
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:
- OutParam->Attribute = Attribute;
- OutParam->Union.Value.A = MessageParam->Union.Value.A;
- OutParam->Union.Value.B = MessageParam->Union.Value.B;
- OutParam->Union.Value.C = MessageParam->Union.Value.C;
- break;
-
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:
- case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:
- OutParam->Attribute = Attribute;
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE:
+ OutParam->Attribute = OPTEE_MESSAGE_ATTRIBUTE_TYPE_NONE;
+ ZeroMem (&OutParam->Union, sizeof (OutParam->Union));
+ break;
- if (MessageParam->Union.Memory.Size > OutParam->Union.Memory.Size) {
- return EFI_BAD_BUFFER_SIZE;
- }
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_OUTPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_VALUE_INOUT:
+ OutParam->Attribute = Attribute;
+ OutParam->Union.Value.A = MessageParam->Union.Value.A;
+ OutParam->Union.Value.B = MessageParam->Union.Value.B;
+ OutParam->Union.Value.C = MessageParam->Union.Value.C;
+ break;
- CopyMem (
- (VOID *)(UINTN)OutParam->Union.Memory.BufferAddress,
- (VOID *)(UINTN)MessageParam->Union.Memory.BufferAddress,
- MessageParam->Union.Memory.Size
- );
- OutParam->Union.Memory.Size = MessageParam->Union.Memory.Size;
- break;
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_OUTPUT:
+ case OPTEE_MESSAGE_ATTRIBUTE_TYPE_MEMORY_INOUT:
+ OutParam->Attribute = Attribute;
+
+ if (MessageParam->Union.Memory.Size > OutParam->Union.Memory.Size) {
+ return EFI_BAD_BUFFER_SIZE;
+ }
+
+ CopyMem (
+ (VOID *)(UINTN)OutParam->Union.Memory.BufferAddress,
+ (VOID *)(UINTN)MessageParam->Union.Memory.BufferAddress,
+ MessageParam->Union.Memory.Size
+ );
+ OutParam->Union.Memory.Size = MessageParam->Union.Memory.Size;
+ break;
- default:
- return EFI_INVALID_PARAMETER;
+ default:
+ return EFI_INVALID_PARAMETER;
}
}
@@ -401,11 +402,11 @@ OpteeFromMessageParam ( EFI_STATUS
EFIAPI
OpteeInvokeFunction (
- IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
+ IN OUT OPTEE_INVOKE_FUNCTION_ARG *InvokeFunctionArg
)
{
- EFI_STATUS Status;
- OPTEE_MESSAGE_ARG *MessageArg;
+ EFI_STATUS Status;
+ OPTEE_MESSAGE_ARG *MessageArg;
MessageArg = NULL;
@@ -417,9 +418,9 @@ OpteeInvokeFunction ( MessageArg = (OPTEE_MESSAGE_ARG *)OpteeSharedMemoryInformation.Base;
ZeroMem (MessageArg, sizeof (OPTEE_MESSAGE_ARG));
- MessageArg->Command = OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION;
+ MessageArg->Command = OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION;
MessageArg->Function = InvokeFunctionArg->Function;
- MessageArg->Session = InvokeFunctionArg->Session;
+ MessageArg->Session = InvokeFunctionArg->Session;
Status = OpteeToMessageParam (
MessageArg->Params,
@@ -433,7 +434,7 @@ OpteeInvokeFunction ( MessageArg->NumParams = OPTEE_MAX_CALL_PARAMS;
if (OpteeCallWithArg ((UINTN)MessageArg) != 0) {
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}
@@ -441,12 +442,13 @@ OpteeInvokeFunction ( InvokeFunctionArg->Params,
OPTEE_MAX_CALL_PARAMS,
MessageArg->Params
- ) != 0) {
- MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
+ ) != 0)
+ {
+ MessageArg->Return = OPTEE_ERROR_COMMUNICATION;
MessageArg->ReturnOrigin = OPTEE_ORIGIN_COMMUNICATION;
}
- InvokeFunctionArg->Return = MessageArg->Return;
+ InvokeFunctionArg->Return = MessageArg->Return;
InvokeFunctionArg->ReturnOrigin = MessageArg->ReturnOrigin;
return EFI_SUCCESS;
diff --git a/ArmPkg/Library/OpteeLib/OpteeSmc.h b/ArmPkg/Library/OpteeLib/OpteeSmc.h index b760ec8f82..ff4b4b020f 100644 --- a/ArmPkg/Library/OpteeLib/OpteeSmc.h +++ b/ArmPkg/Library/OpteeLib/OpteeSmc.h @@ -11,26 +11,26 @@ #define OPTEE_SMC_H_
/* Returned in Arg0 only from Trusted OS functions */
-#define OPTEE_SMC_RETURN_OK 0x0
+#define OPTEE_SMC_RETURN_OK 0x0
-#define OPTEE_SMC_RETURN_FROM_RPC 0x32000003
-#define OPTEE_SMC_CALL_WITH_ARG 0x32000004
-#define OPTEE_SMC_GET_SHARED_MEMORY_CONFIG 0xb2000007
+#define OPTEE_SMC_RETURN_FROM_RPC 0x32000003
+#define OPTEE_SMC_CALL_WITH_ARG 0x32000004
+#define OPTEE_SMC_GET_SHARED_MEMORY_CONFIG 0xb2000007
-#define OPTEE_SMC_SHARED_MEMORY_CACHED 1
+#define OPTEE_SMC_SHARED_MEMORY_CACHED 1
#define OPTEE_SMC_RETURN_UNKNOWN_FUNCTION 0xffffffff
#define OPTEE_SMC_RETURN_RPC_PREFIX_MASK 0xffff0000
#define OPTEE_SMC_RETURN_RPC_PREFIX 0xffff0000
#define OPTEE_SMC_RETURN_RPC_FOREIGN_INTERRUPT 0xffff0004
-#define OPTEE_MESSAGE_COMMAND_OPEN_SESSION 0
-#define OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION 1
-#define OPTEE_MESSAGE_COMMAND_CLOSE_SESSION 2
+#define OPTEE_MESSAGE_COMMAND_OPEN_SESSION 0
+#define OPTEE_MESSAGE_COMMAND_INVOKE_FUNCTION 1
+#define OPTEE_MESSAGE_COMMAND_CLOSE_SESSION 2
-#define OPTEE_MESSAGE_ATTRIBUTE_META 0x100
+#define OPTEE_MESSAGE_ATTRIBUTE_META 0x100
-#define OPTEE_LOGIN_PUBLIC 0x0
+#define OPTEE_LOGIN_PUBLIC 0x0
typedef struct {
UINTN Base;
@@ -41,10 +41,10 @@ typedef struct { // UUID struct compliant with RFC4122 (network byte order).
//
typedef struct {
- UINT32 Data1;
- UINT16 Data2;
- UINT16 Data3;
- UINT8 Data4[8];
+ UINT32 Data1;
+ UINT16 Data2;
+ UINT16 Data3;
+ UINT8 Data4[8];
} RFC4122_UUID;
#endif // OPTEE_SMC_H_
diff --git a/ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c b/ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c index 67cbc46e5c..bc6841b892 100644 --- a/ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c +++ b/ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointer.c @@ -28,10 +28,10 @@ VOID
EFIAPI
SetPeiServicesTablePointer (
- IN CONST EFI_PEI_SERVICES ** PeiServicesTablePointer
+ IN CONST EFI_PEI_SERVICES **PeiServicesTablePointer
)
{
- ArmWriteTpidrurw((UINTN)PeiServicesTablePointer);
+ ArmWriteTpidrurw ((UINTN)PeiServicesTablePointer);
}
/**
@@ -52,7 +52,7 @@ GetPeiServicesTablePointer ( VOID
)
{
- return (CONST EFI_PEI_SERVICES **)ArmReadTpidrurw();
+ return (CONST EFI_PEI_SERVICES **)ArmReadTpidrurw ();
}
/**
@@ -71,9 +71,9 @@ migration actions are required for Itanium or ARM CPUs. **/
VOID
EFIAPI
-MigratePeiServicesTablePointer(
-VOID
-)
+MigratePeiServicesTablePointer (
+ VOID
+ )
{
return;
}
diff --git a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c index 097df3e9e4..2fb1a4aa4f 100644 --- a/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c +++ b/ArmPkg/Library/PlatformBootManagerLib/PlatformBm.c @@ -37,23 +37,23 @@ #include "PlatformBm.h"
-#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
+#define DP_NODE_LEN(Type) { (UINT8)sizeof (Type), (UINT8)(sizeof (Type) >> 8) }
#pragma pack (1)
typedef struct {
- VENDOR_DEVICE_PATH SerialDxe;
- UART_DEVICE_PATH Uart;
- VENDOR_DEFINED_DEVICE_PATH TermType;
- EFI_DEVICE_PATH_PROTOCOL End;
+ VENDOR_DEVICE_PATH SerialDxe;
+ UART_DEVICE_PATH Uart;
+ VENDOR_DEFINED_DEVICE_PATH TermType;
+ EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_SERIAL_CONSOLE;
#pragma pack ()
-STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
+STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = {
//
// VENDOR_DEVICE_PATH SerialDxe
//
{
- { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
+ { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, DP_NODE_LEN (VENDOR_DEVICE_PATH) },
EDKII_SERIAL_PORT_LIB_VENDOR_GUID
},
@@ -61,7 +61,7 @@ STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { // UART_DEVICE_PATH Uart
//
{
- { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
+ { MESSAGING_DEVICE_PATH, MSG_UART_DP, DP_NODE_LEN (UART_DEVICE_PATH) },
0, // Reserved
FixedPcdGet64 (PcdUartDefaultBaudRate), // BaudRate
FixedPcdGet8 (PcdUartDefaultDataBits), // DataBits
@@ -91,15 +91,14 @@ STATIC PLATFORM_SERIAL_CONSOLE mSerialConsole = { }
};
-
#pragma pack (1)
typedef struct {
- USB_CLASS_DEVICE_PATH Keyboard;
- EFI_DEVICE_PATH_PROTOCOL End;
+ USB_CLASS_DEVICE_PATH Keyboard;
+ EFI_DEVICE_PATH_PROTOCOL End;
} PLATFORM_USB_KEYBOARD;
#pragma pack ()
-STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
+STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = {
//
// USB_CLASS_DEVICE_PATH Keyboard
//
@@ -124,7 +123,6 @@ STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = { }
};
-
/**
Check if the handle satisfies a particular condition.
@@ -138,12 +136,11 @@ STATIC PLATFORM_USB_KEYBOARD mUsbKeyboard = { **/
typedef
BOOLEAN
-(EFIAPI *FILTER_FUNCTION) (
+(EFIAPI *FILTER_FUNCTION)(
IN EFI_HANDLE Handle,
IN CONST CHAR16 *ReportText
);
-
/**
Process a handle.
@@ -153,7 +150,7 @@ BOOLEAN **/
typedef
VOID
-(EFIAPI *CALLBACK_FUNCTION) (
+(EFIAPI *CALLBACK_FUNCTION)(
IN EFI_HANDLE Handle,
IN CONST CHAR16 *ReportText
);
@@ -174,31 +171,41 @@ VOID STATIC
VOID
FilterAndProcess (
- IN EFI_GUID *ProtocolGuid,
- IN FILTER_FUNCTION Filter OPTIONAL,
- IN CALLBACK_FUNCTION Process
+ IN EFI_GUID *ProtocolGuid,
+ IN FILTER_FUNCTION Filter OPTIONAL,
+ IN CALLBACK_FUNCTION Process
)
{
- EFI_STATUS Status;
- EFI_HANDLE *Handles;
- UINTN NoHandles;
- UINTN Idx;
-
- Status = gBS->LocateHandleBuffer (ByProtocol, ProtocolGuid,
- NULL /* SearchKey */, &NoHandles, &Handles);
+ EFI_STATUS Status;
+ EFI_HANDLE *Handles;
+ UINTN NoHandles;
+ UINTN Idx;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ ProtocolGuid,
+ NULL /* SearchKey */,
+ &NoHandles,
+ &Handles
+ );
if (EFI_ERROR (Status)) {
//
// This is not an error, just an informative condition.
//
- DEBUG ((DEBUG_VERBOSE, "%a: %g: %r\n", __FUNCTION__, ProtocolGuid,
- Status));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: %g: %r\n",
+ __FUNCTION__,
+ ProtocolGuid,
+ Status
+ ));
return;
}
ASSERT (NoHandles > 0);
for (Idx = 0; Idx < NoHandles; ++Idx) {
- CHAR16 *DevicePathText;
- STATIC CHAR16 Fallback[] = L"<device path unavailable>";
+ CHAR16 *DevicePathText;
+ STATIC CHAR16 Fallback[] = L"<device path unavailable>";
//
// The ConvertDevicePathToText() function handles NULL input transparently.
@@ -212,7 +219,7 @@ FilterAndProcess ( DevicePathText = Fallback;
}
- if (Filter == NULL || Filter (Handles[Idx], DevicePathText)) {
+ if ((Filter == NULL) || Filter (Handles[Idx], DevicePathText)) {
Process (Handles[Idx], DevicePathText);
}
@@ -220,10 +227,10 @@ FilterAndProcess ( FreePool (DevicePathText);
}
}
+
gBS->FreePool (Handles);
}
-
/**
This FILTER_FUNCTION checks if a handle corresponds to a PCI display device.
**/
@@ -231,16 +238,19 @@ STATIC BOOLEAN
EFIAPI
IsPciDisplay (
- IN EFI_HANDLE Handle,
- IN CONST CHAR16 *ReportText
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
)
{
- EFI_STATUS Status;
- EFI_PCI_IO_PROTOCOL *PciIo;
- PCI_TYPE00 Pci;
+ EFI_STATUS Status;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
- Status = gBS->HandleProtocol (Handle, &gEfiPciIoProtocolGuid,
- (VOID**)&PciIo);
+ Status = gBS->HandleProtocol (
+ Handle,
+ &gEfiPciIoProtocolGuid,
+ (VOID **)&PciIo
+ );
if (EFI_ERROR (Status)) {
//
// This is not an error worth reporting.
@@ -248,8 +258,13 @@ IsPciDisplay ( return FALSE;
}
- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint32, 0 /* Offset */,
- sizeof Pci / sizeof (UINT32), &Pci);
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0 /* Offset */,
+ sizeof Pci / sizeof (UINT32),
+ &Pci
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a: %s: %r\n", __FUNCTION__, ReportText, Status));
return FALSE;
@@ -258,7 +273,6 @@ IsPciDisplay ( return IS_PCI_DISPLAY (&Pci);
}
-
/**
This FILTER_FUNCTION checks if a handle corresponds to a non-discoverable
USB host controller.
@@ -267,29 +281,32 @@ STATIC BOOLEAN
EFIAPI
IsUsbHost (
- IN EFI_HANDLE Handle,
- IN CONST CHAR16 *ReportText
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
)
{
- NON_DISCOVERABLE_DEVICE *Device;
- EFI_STATUS Status;
+ NON_DISCOVERABLE_DEVICE *Device;
+ EFI_STATUS Status;
- Status = gBS->HandleProtocol (Handle,
+ Status = gBS->HandleProtocol (
+ Handle,
&gEdkiiNonDiscoverableDeviceProtocolGuid,
- (VOID **)&Device);
+ (VOID **)&Device
+ );
if (EFI_ERROR (Status)) {
return FALSE;
}
if (CompareGuid (Device->Type, &gEdkiiNonDiscoverableUhciDeviceGuid) ||
CompareGuid (Device->Type, &gEdkiiNonDiscoverableEhciDeviceGuid) ||
- CompareGuid (Device->Type, &gEdkiiNonDiscoverableXhciDeviceGuid)) {
+ CompareGuid (Device->Type, &gEdkiiNonDiscoverableXhciDeviceGuid))
+ {
return TRUE;
}
+
return FALSE;
}
-
/**
This CALLBACK_FUNCTION attempts to connect a handle non-recursively, asking
the matching driver to produce all first-level child handles.
@@ -298,11 +315,11 @@ STATIC VOID
EFIAPI
Connect (
- IN EFI_HANDLE Handle,
- IN CONST CHAR16 *ReportText
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
Status = gBS->ConnectController (
Handle, // ControllerHandle
@@ -310,11 +327,15 @@ Connect ( NULL, // RemainingDevicePath -- produce all children
FALSE // Recursive
);
- DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE, "%a: %s: %r\n",
- __FUNCTION__, ReportText, Status));
+ DEBUG ((
+ EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
+ "%a: %s: %r\n",
+ __FUNCTION__,
+ ReportText,
+ Status
+ ));
}
-
/**
This CALLBACK_FUNCTION retrieves the EFI_DEVICE_PATH_PROTOCOL from the
handle, and adds it to ConOut and ErrOut.
@@ -323,60 +344,79 @@ STATIC VOID
EFIAPI
AddOutput (
- IN EFI_HANDLE Handle,
- IN CONST CHAR16 *ReportText
+ IN EFI_HANDLE Handle,
+ IN CONST CHAR16 *ReportText
)
{
- EFI_STATUS Status;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
DevicePath = DevicePathFromHandle (Handle);
if (DevicePath == NULL) {
- DEBUG ((DEBUG_ERROR, "%a: %s: handle %p: device path not found\n",
- __FUNCTION__, ReportText, Handle));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %s: handle %p: device path not found\n",
+ __FUNCTION__,
+ ReportText,
+ Handle
+ ));
return;
}
Status = EfiBootManagerUpdateConsoleVariable (ConOut, DevicePath, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: %s: adding to ConOut: %r\n", __FUNCTION__,
- ReportText, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %s: adding to ConOut: %r\n",
+ __FUNCTION__,
+ ReportText,
+ Status
+ ));
return;
}
Status = EfiBootManagerUpdateConsoleVariable (ErrOut, DevicePath, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: %s: adding to ErrOut: %r\n", __FUNCTION__,
- ReportText, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: %s: adding to ErrOut: %r\n",
+ __FUNCTION__,
+ ReportText,
+ Status
+ ));
return;
}
- DEBUG ((DEBUG_VERBOSE, "%a: %s: added to ConOut and ErrOut\n", __FUNCTION__,
- ReportText));
+ DEBUG ((
+ DEBUG_VERBOSE,
+ "%a: %s: added to ConOut and ErrOut\n",
+ __FUNCTION__,
+ ReportText
+ ));
}
STATIC
VOID
PlatformRegisterFvBootOption (
- CONST EFI_GUID *FileGuid,
- CHAR16 *Description,
- UINT32 Attributes,
- EFI_INPUT_KEY *Key
+ CONST EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINT32 Attributes,
+ EFI_INPUT_KEY *Key
)
{
- EFI_STATUS Status;
- INTN OptionIndex;
- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN BootOptionCount;
- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
- EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_STATUS Status;
+ INTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
Status = gBS->HandleProtocol (
gImageHandle,
&gEfiLoadedImageProtocolGuid,
- (VOID **) &LoadedImage
+ (VOID **)&LoadedImage
);
ASSERT_EFI_ERROR (Status);
@@ -385,7 +425,7 @@ PlatformRegisterFvBootOption ( ASSERT (DevicePath != NULL);
DevicePath = AppendDevicePathNode (
DevicePath,
- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+ (EFI_DEVICE_PATH_PROTOCOL *)&FileNode
);
ASSERT (DevicePath != NULL);
@@ -403,25 +443,33 @@ PlatformRegisterFvBootOption ( FreePool (DevicePath);
BootOptions = EfiBootManagerGetLoadOptions (
- &BootOptionCount, LoadOptionTypeBoot
+ &BootOptionCount,
+ LoadOptionTypeBoot
);
OptionIndex = EfiBootManagerFindLoadOption (
- &NewOption, BootOptions, BootOptionCount
+ &NewOption,
+ BootOptions,
+ BootOptionCount
);
if (OptionIndex == -1) {
Status = EfiBootManagerAddLoadOptionVariable (&NewOption, MAX_UINTN);
ASSERT_EFI_ERROR (Status);
- Status = EfiBootManagerAddKeyOptionVariable (NULL,
- (UINT16)NewOption.OptionNumber, 0, Key, NULL);
+ Status = EfiBootManagerAddKeyOptionVariable (
+ NULL,
+ (UINT16)NewOption.OptionNumber,
+ 0,
+ Key,
+ NULL
+ );
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
}
+
EfiBootManagerFreeLoadOption (&NewOption);
EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
}
-
STATIC
VOID
GetPlatformOptions (
@@ -437,11 +485,15 @@ GetPlatformOptions ( UINTN Index;
UINTN BootCount;
- Status = gBS->LocateProtocol (&gPlatformBootManagerProtocolGuid, NULL,
- (VOID **)&PlatformBootManager);
+ Status = gBS->LocateProtocol (
+ &gPlatformBootManagerProtocolGuid,
+ NULL,
+ (VOID **)&PlatformBootManager
+ );
if (EFI_ERROR (Status)) {
return;
}
+
Status = PlatformBootManager->GetPlatformBootOptionsAndKeys (
&BootCount,
&BootOptions,
@@ -450,6 +502,7 @@ GetPlatformOptions ( if (EFI_ERROR (Status)) {
return;
}
+
//
// Fetch the existent boot options. If there are none, CurrentBootCount
// will be zeroed.
@@ -462,8 +515,8 @@ GetPlatformOptions ( // Process the platform boot options.
//
for (Index = 0; Index < BootCount; Index++) {
- INTN Match;
- UINTN BootOptionNumber;
+ INTN Match;
+ UINTN BootOptionNumber;
//
// If there are any preexistent boot options, and the subject platform boot
@@ -491,10 +544,16 @@ GetPlatformOptions ( MAX_UINTN
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: failed to register \"%s\": %r\n",
- __FUNCTION__, BootOptions[Index].Description, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: failed to register \"%s\": %r\n",
+ __FUNCTION__,
+ BootOptions[Index].Description,
+ Status
+ ));
continue;
}
+
BootOptionNumber = BootOptions[Index].OptionNumber;
}
@@ -513,10 +572,16 @@ GetPlatformOptions ( NULL
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: failed to register hotkey for \"%s\": %r\n",
- __FUNCTION__, BootOptions[Index].Description, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: failed to register hotkey for \"%s\": %r\n",
+ __FUNCTION__,
+ BootOptions[Index].Description,
+ Status
+ ));
}
}
+
EfiBootManagerFreeLoadOptions (CurrentBootOptions, CurrentBootOptionCount);
EfiBootManagerFreeLoadOptions (BootOptions, BootCount);
FreePool (BootKeys);
@@ -528,11 +593,11 @@ PlatformRegisterOptionsAndKeys ( VOID
)
{
- EFI_STATUS Status;
- EFI_INPUT_KEY Enter;
- EFI_INPUT_KEY F2;
- EFI_INPUT_KEY Esc;
- EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
+ EFI_STATUS Status;
+ EFI_INPUT_KEY Enter;
+ EFI_INPUT_KEY F2;
+ EFI_INPUT_KEY Esc;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootOption;
GetPlatformOptions ();
@@ -541,7 +606,7 @@ PlatformRegisterOptionsAndKeys ( //
Enter.ScanCode = SCAN_NULL;
Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
- Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
+ Status = EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
ASSERT_EFI_ERROR (Status);
//
@@ -551,22 +616,30 @@ PlatformRegisterOptionsAndKeys ( F2.UnicodeChar = CHAR_NULL;
Esc.ScanCode = SCAN_ESC;
Esc.UnicodeChar = CHAR_NULL;
- Status = EfiBootManagerGetBootManagerMenu (&BootOption);
+ Status = EfiBootManagerGetBootManagerMenu (&BootOption);
ASSERT_EFI_ERROR (Status);
Status = EfiBootManagerAddKeyOptionVariable (
- NULL, (UINT16) BootOption.OptionNumber, 0, &F2, NULL
+ NULL,
+ (UINT16)BootOption.OptionNumber,
+ 0,
+ &F2,
+ NULL
);
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
Status = EfiBootManagerAddKeyOptionVariable (
- NULL, (UINT16) BootOption.OptionNumber, 0, &Esc, NULL
+ NULL,
+ (UINT16)BootOption.OptionNumber,
+ 0,
+ &Esc,
+ NULL
);
ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
}
-
//
// BDS Platform Functions
//
+
/**
Do the platform init, can be customized by OEM/IBV
Possible things that can be done in PlatformBootManagerBeforeConsole:
@@ -626,27 +699,45 @@ PlatformBootManagerBeforeConsole ( //
// Add the hardcoded short-form USB keyboard device path to ConIn.
//
- EfiBootManagerUpdateConsoleVariable (ConIn,
- (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard, NULL);
+ EfiBootManagerUpdateConsoleVariable (
+ ConIn,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mUsbKeyboard,
+ NULL
+ );
//
// Add the hardcoded serial console device path to ConIn, ConOut, ErrOut.
//
- STATIC_ASSERT (FixedPcdGet8 (PcdDefaultTerminalType) == 4,
- "PcdDefaultTerminalType must be TTYTERM");
- STATIC_ASSERT (FixedPcdGet8 (PcdUartDefaultParity) != 0,
- "PcdUartDefaultParity must be set to an actual value, not 'default'");
- STATIC_ASSERT (FixedPcdGet8 (PcdUartDefaultStopBits) != 0,
- "PcdUartDefaultStopBits must be set to an actual value, not 'default'");
+ STATIC_ASSERT (
+ FixedPcdGet8 (PcdDefaultTerminalType) == 4,
+ "PcdDefaultTerminalType must be TTYTERM"
+ );
+ STATIC_ASSERT (
+ FixedPcdGet8 (PcdUartDefaultParity) != 0,
+ "PcdUartDefaultParity must be set to an actual value, not 'default'"
+ );
+ STATIC_ASSERT (
+ FixedPcdGet8 (PcdUartDefaultStopBits) != 0,
+ "PcdUartDefaultStopBits must be set to an actual value, not 'default'"
+ );
CopyGuid (&mSerialConsole.TermType.Guid, &gEfiTtyTermGuid);
- EfiBootManagerUpdateConsoleVariable (ConIn,
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
- EfiBootManagerUpdateConsoleVariable (ConOut,
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
- EfiBootManagerUpdateConsoleVariable (ErrOut,
- (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole, NULL);
+ EfiBootManagerUpdateConsoleVariable (
+ ConIn,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,
+ NULL
+ );
+ EfiBootManagerUpdateConsoleVariable (
+ ConOut,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,
+ NULL
+ );
+ EfiBootManagerUpdateConsoleVariable (
+ ErrOut,
+ (EFI_DEVICE_PATH_PROTOCOL *)&mSerialConsole,
+ NULL
+ );
//
// Register platform-specific boot options and keyboard shortcuts.
@@ -660,16 +751,19 @@ HandleCapsules ( VOID
)
{
- ESRT_MANAGEMENT_PROTOCOL *EsrtManagement;
- EFI_PEI_HOB_POINTERS HobPointer;
- EFI_CAPSULE_HEADER *CapsuleHeader;
- BOOLEAN NeedReset;
- EFI_STATUS Status;
+ ESRT_MANAGEMENT_PROTOCOL *EsrtManagement;
+ EFI_PEI_HOB_POINTERS HobPointer;
+ EFI_CAPSULE_HEADER *CapsuleHeader;
+ BOOLEAN NeedReset;
+ EFI_STATUS Status;
DEBUG ((DEBUG_INFO, "%a: processing capsules ...\n", __FUNCTION__));
- Status = gBS->LocateProtocol (&gEsrtManagementProtocolGuid, NULL,
- (VOID **)&EsrtManagement);
+ Status = gBS->LocateProtocol (
+ &gEsrtManagementProtocolGuid,
+ NULL,
+ (VOID **)&EsrtManagement
+ );
if (!EFI_ERROR (Status)) {
EsrtManagement->SyncEsrtFmp ();
}
@@ -678,33 +772,43 @@ HandleCapsules ( // Find all capsule images from hob
//
HobPointer.Raw = GetHobList ();
- NeedReset = FALSE;
- while ((HobPointer.Raw = GetNextHob (EFI_HOB_TYPE_UEFI_CAPSULE,
- HobPointer.Raw)) != NULL) {
+ NeedReset = FALSE;
+ while ((HobPointer.Raw = GetNextHob (
+ EFI_HOB_TYPE_UEFI_CAPSULE,
+ HobPointer.Raw
+ )) != NULL)
+ {
CapsuleHeader = (VOID *)(UINTN)HobPointer.Capsule->BaseAddress;
Status = ProcessCapsuleImage (CapsuleHeader);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "%a: failed to process capsule %p - %r\n",
- __FUNCTION__, CapsuleHeader, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: failed to process capsule %p - %r\n",
+ __FUNCTION__,
+ CapsuleHeader,
+ Status
+ ));
return;
}
- NeedReset = TRUE;
+ NeedReset = TRUE;
HobPointer.Raw = GET_NEXT_HOB (HobPointer);
}
if (NeedReset) {
- DEBUG ((DEBUG_WARN, "%a: capsule update successful, resetting ...\n",
- __FUNCTION__));
-
- gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
- CpuDeadLoop();
+ DEBUG ((
+ DEBUG_WARN,
+ "%a: capsule update successful, resetting ...\n",
+ __FUNCTION__
+ ));
+
+ gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
+ CpuDeadLoop ();
}
}
-
-#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "
+#define VERSION_STRING_PREFIX L"Tianocore/EDK2 firmware version "
/**
This functions checks the value of BootDiscoverPolicy variable and
@@ -722,14 +826,14 @@ BootDiscoveryPolicyHandler ( VOID
)
{
- EFI_STATUS Status;
- UINT32 DiscoveryPolicy;
- UINT32 DiscoveryPolicyOld;
- UINTN Size;
- EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
- EFI_GUID *Class;
-
- Size = sizeof (DiscoveryPolicy);
+ EFI_STATUS Status;
+ UINT32 DiscoveryPolicy;
+ UINT32 DiscoveryPolicyOld;
+ UINTN Size;
+ EFI_BOOT_MANAGER_POLICY_PROTOCOL *BMPolicy;
+ EFI_GUID *Class;
+
+ Size = sizeof (DiscoveryPolicy);
Status = gRT->GetVariable (
BOOT_DISCOVERY_POLICY_VAR,
&gBootDiscoveryPolicyMgrFormsetGuid,
@@ -739,7 +843,7 @@ BootDiscoveryPolicyHandler ( );
if (Status == EFI_NOT_FOUND) {
DiscoveryPolicy = PcdGet32 (PcdBootDiscoveryPolicy);
- Status = PcdSet32S (PcdBootDiscoveryPolicy, DiscoveryPolicy);
+ Status = PcdSet32S (PcdBootDiscoveryPolicy, DiscoveryPolicy);
if (Status == EFI_NOT_FOUND) {
return EFI_SUCCESS;
} else if (EFI_ERROR (Status)) {
@@ -776,13 +880,17 @@ BootDiscoveryPolicyHandler ( (VOID **)&BMPolicy
);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_INFO, "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."
- "Driver connect will be skipped.\n", __FUNCTION__));
+ DEBUG ((
+ DEBUG_INFO,
+ "%a - Failed to locate gEfiBootManagerPolicyProtocolGuid."
+ "Driver connect will be skipped.\n",
+ __FUNCTION__
+ ));
return Status;
}
Status = BMPolicy->ConnectDeviceClass (BMPolicy, Class);
- if (EFI_ERROR (Status)){
+ if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "%a - ConnectDeviceClass returns - %r\n", __FUNCTION__, Status));
return Status;
}
@@ -790,7 +898,7 @@ BootDiscoveryPolicyHandler ( //
// Refresh Boot Options if Boot Discovery Policy has been changed
//
- Size = sizeof (DiscoveryPolicyOld);
+ Size = sizeof (DiscoveryPolicyOld);
Status = gRT->GetVariable (
BOOT_DISCOVERY_POLICY_OLD_VAR,
&gBootDiscoveryPolicyMgrFormsetGuid,
@@ -845,21 +953,33 @@ PlatformBootManagerAfterConsole ( Status = BootLogoEnableLogo ();
if (EFI_ERROR (Status)) {
if (FirmwareVerLength > 0) {
- Print (VERSION_STRING_PREFIX L"%s\n",
- PcdGetPtr (PcdFirmwareVersionString));
+ Print (
+ VERSION_STRING_PREFIX L"%s\n",
+ PcdGetPtr (PcdFirmwareVersionString)
+ );
}
+
Print (L"Press ESCAPE for boot options ");
} else if (FirmwareVerLength > 0) {
- Status = gBS->HandleProtocol (gST->ConsoleOutHandle,
- &gEfiGraphicsOutputProtocolGuid, (VOID **)&GraphicsOutput);
+ Status = gBS->HandleProtocol (
+ gST->ConsoleOutHandle,
+ &gEfiGraphicsOutputProtocolGuid,
+ (VOID **)&GraphicsOutput
+ );
if (!EFI_ERROR (Status)) {
PosX = (GraphicsOutput->Mode->Info->HorizontalResolution -
(StrLen (VERSION_STRING_PREFIX) + FirmwareVerLength) *
EFI_GLYPH_WIDTH) / 2;
PosY = 0;
- PrintXY (PosX, PosY, NULL, NULL, VERSION_STRING_PREFIX L"%s",
- PcdGetPtr (PcdFirmwareVersionString));
+ PrintXY (
+ PosX,
+ PosY,
+ NULL,
+ NULL,
+ VERSION_STRING_PREFIX L"%s",
+ PcdGetPtr (PcdFirmwareVersionString)
+ );
}
}
@@ -881,8 +1001,8 @@ PlatformBootManagerAfterConsole ( //
// Register UEFI Shell
//
- Key.ScanCode = SCAN_NULL;
- Key.UnicodeChar = L's';
+ Key.ScanCode = SCAN_NULL;
+ Key.UnicodeChar = L's';
PlatformRegisterFvBootOption (&gUefiShellFileGuid, L"UEFI Shell", 0, &Key);
}
@@ -895,13 +1015,13 @@ PlatformBootManagerAfterConsole ( VOID
EFIAPI
PlatformBootManagerWaitCallback (
- UINT16 TimeoutRemain
+ UINT16 TimeoutRemain
)
{
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black;
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White;
- UINT16 Timeout;
- EFI_STATUS Status;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION Black;
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL_UNION White;
+ UINT16 Timeout;
+ EFI_STATUS Status;
Timeout = PcdGet16 (PcdPlatformBootTimeOut);
@@ -934,17 +1054,19 @@ PlatformBootManagerUnableToBoot ( VOID
)
{
- EFI_STATUS Status;
- EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu;
- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
- UINTN OldBootOptionCount;
- UINTN NewBootOptionCount;
+ EFI_STATUS Status;
+ EFI_BOOT_MANAGER_LOAD_OPTION BootManagerMenu;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN OldBootOptionCount;
+ UINTN NewBootOptionCount;
//
// Record the total number of boot configured boot options
//
- BootOptions = EfiBootManagerGetLoadOptions (&OldBootOptionCount,
- LoadOptionTypeBoot);
+ BootOptions = EfiBootManagerGetLoadOptions (
+ &OldBootOptionCount,
+ LoadOptionTypeBoot
+ );
EfiBootManagerFreeLoadOptions (BootOptions, OldBootOptionCount);
//
@@ -956,8 +1078,10 @@ PlatformBootManagerUnableToBoot ( //
// Record the updated number of boot configured boot options
//
- BootOptions = EfiBootManagerGetLoadOptions (&NewBootOptionCount,
- LoadOptionTypeBoot);
+ BootOptions = EfiBootManagerGetLoadOptions (
+ &NewBootOptionCount,
+ LoadOptionTypeBoot
+ );
EfiBootManagerFreeLoadOptions (BootOptions, NewBootOptionCount);
//
@@ -969,8 +1093,11 @@ PlatformBootManagerUnableToBoot ( //
if (!PcdGetBool (PcdEmuVariableNvModeEnable)) {
if (NewBootOptionCount != OldBootOptionCount) {
- DEBUG ((DEBUG_WARN, "%a: rebooting after refreshing all boot options\n",
- __FUNCTION__));
+ DEBUG ((
+ DEBUG_WARN,
+ "%a: rebooting after refreshing all boot options\n",
+ __FUNCTION__
+ ));
gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
}
}
@@ -980,7 +1107,7 @@ PlatformBootManagerUnableToBoot ( return;
}
- for (;;) {
+ for ( ; ;) {
EfiBootManagerBoot (&BootManagerMenu);
}
}
diff --git a/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c b/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c index 80e531921c..6539c01763 100644 --- a/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c +++ b/ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.c @@ -39,18 +39,18 @@ WriteStringToFile ( // This gets you all the symbols except for SEC. To get SEC symbols you need to copy the
// debug print in the SEC into the debugger manually
SemihostWriteString (Buffer);
-/*
- I'm currently having issues with this code crashing the debugger. Seems like it should work.
- UINT32 SemihostHandle;
- UINT32 SemihostMode = SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;
+ /*
+ I'm currently having issues with this code crashing the debugger. Seems like it should work.
- SemihostFileOpen ("c:\rvi_symbols.inc", SemihostMode, &SemihostHandle);
- SemihostFileWrite (SemihostHandle, &Length, Buffer);
- SemihostFileClose (SemihostHandle);
- */
-}
+ UINT32 SemihostHandle;
+ UINT32 SemihostMode = SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY | SEMIHOST_FILE_MODE_UPDATE;
+ SemihostFileOpen ("c:\rvi_symbols.inc", SemihostMode, &SemihostHandle);
+ SemihostFileWrite (SemihostHandle, &Length, Buffer);
+ SemihostFileClose (SemihostHandle);
+ */
+}
/**
If the build is done on cygwin the paths are cygpaths.
@@ -62,12 +62,12 @@ WriteStringToFile ( **/
CHAR8 *
DeCygwinPathIfNeeded (
- IN CHAR8 *Name
+ IN CHAR8 *Name
)
{
- CHAR8 *Ptr;
- UINTN Index;
- UINTN Len;
+ CHAR8 *Ptr;
+ UINTN Index;
+ UINTN Len;
Ptr = AsciiStrStr (Name, "/cygdrive/");
if (Ptr == NULL) {
@@ -88,14 +88,13 @@ DeCygwinPathIfNeeded ( // switch path separators
for (Index = 11; Index < Len; Index++) {
if (Ptr[Index] == '/') {
- Ptr[Index] = '\\' ;
+ Ptr[Index] = '\\';
}
}
return Name;
}
-
/**
Performs additional actions after a PE/COFF image has been loaded and relocated.
@@ -111,20 +110,18 @@ PeCoffLoaderRelocateImageExtraAction ( IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
- CHAR8 Buffer[256];
+ CHAR8 Buffer[256];
-#if (__ARMCC_VERSION < 500000)
- AsciiSPrint (Buffer, sizeof(Buffer), "load /a /ni /np \"%a\" &0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
-#else
- AsciiSPrint (Buffer, sizeof(Buffer), "add-symbol-file %a 0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
-#endif
+ #if (__ARMCC_VERSION < 500000)
+ AsciiSPrint (Buffer, sizeof (Buffer), "load /a /ni /np \"%a\" &0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
+ #else
+ AsciiSPrint (Buffer, sizeof (Buffer), "add-symbol-file %a 0x%08x\n", ImageContext->PdbPointer, (UINTN)(ImageContext->ImageAddress + ImageContext->SizeOfHeaders));
+ #endif
DeCygwinPathIfNeeded (&Buffer[16]);
WriteStringToFile (Buffer, AsciiStrSize (Buffer));
}
-
-
/**
Performs additional actions just before a PE/COFF image is unloaded. Any resources
that were allocated by PeCoffLoaderRelocateImageExtraAction() must be freed.
@@ -141,9 +138,9 @@ PeCoffLoaderUnloadImageExtraAction ( IN OUT PE_COFF_LOADER_IMAGE_CONTEXT *ImageContext
)
{
- CHAR8 Buffer[256];
+ CHAR8 Buffer[256];
- AsciiSPrint (Buffer, sizeof(Buffer), "unload symbols_only \"%a\"\n", ImageContext->PdbPointer);
+ AsciiSPrint (Buffer, sizeof (Buffer), "unload symbols_only \"%a\"\n", ImageContext->PdbPointer);
DeCygwinPathIfNeeded (Buffer);
WriteStringToFile (Buffer, AsciiStrSize (Buffer));
diff --git a/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c b/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c index ae762d8bea..c3ea568dc4 100644 --- a/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c +++ b/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c @@ -7,7 +7,6 @@ **/
-
#include <Uefi.h>
#include <Library/DebugLib.h>
#include <Library/PrintLib.h>
@@ -25,7 +24,7 @@ // VA_LIST can not initialize to NULL for all compiler, so we use this to
// indicate a null VA_LIST
//
-VA_LIST mVaListNull;
+VA_LIST mVaListNull;
/**
@@ -49,14 +48,13 @@ DebugPrint ( ...
)
{
- VA_LIST Marker;
+ VA_LIST Marker;
VA_START (Marker, Format);
DebugVPrint (ErrorLevel, Format, Marker);
VA_END (Marker);
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled base on Null-terminated format string and a
@@ -76,13 +74,13 @@ DebugPrint ( **/
VOID
DebugPrintMarker (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker,
- IN BASE_LIST BaseListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker,
+ IN BASE_LIST BaseListMarker
)
{
- CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
+ CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
//
// If Format is NULL, then ASSERT().
@@ -92,7 +90,7 @@ DebugPrintMarker ( //
// Check driver debug mask value and global mask
//
- if ((ErrorLevel & PcdGet32(PcdDebugPrintErrorLevel)) == 0) {
+ if ((ErrorLevel & PcdGet32 (PcdDebugPrintErrorLevel)) == 0) {
return;
}
@@ -108,7 +106,6 @@ DebugPrintMarker ( SemihostWriteString (AsciiBuffer);
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -127,15 +124,14 @@ DebugPrintMarker ( VOID
EFIAPI
DebugVPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN VA_LIST VaListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN VA_LIST VaListMarker
)
{
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);
}
-
/**
Prints a debug message to the debug output device if the specified
error level is enabled.
@@ -156,15 +152,14 @@ DebugVPrint ( VOID
EFIAPI
DebugBPrint (
- IN UINTN ErrorLevel,
- IN CONST CHAR8 *Format,
- IN BASE_LIST BaseListMarker
+ IN UINTN ErrorLevel,
+ IN CONST CHAR8 *Format,
+ IN BASE_LIST BaseListMarker
)
{
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);
}
-
/**
Prints an assert message containing a filename, line number, and description.
@@ -196,7 +191,7 @@ DebugAssert ( IN CONST CHAR8 *Description
)
{
- CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
+ CHAR8 AsciiBuffer[MAX_DEBUG_MESSAGE_LENGTH];
//
// Generate the ASSERT() message in Unicode format
@@ -208,14 +203,13 @@ DebugAssert ( //
// Generate a Breakpoint, DeadLoop, or NOP based on PCD settings
//
- if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
+ if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_BREAKPOINT_ENABLED) != 0) {
CpuBreakpoint ();
- } else if ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
+ } else if ((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_ASSERT_DEADLOOP_ENABLED) != 0) {
CpuDeadLoop ();
}
}
-
/**
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.
@@ -248,10 +242,9 @@ DebugClearMemory ( //
// SetMem() checks for the ASSERT() condition on Length and returns Buffer
//
- return SetMem (Buffer, Length, PcdGet8(PcdDebugClearMemoryValue));
+ return SetMem (Buffer, Length, PcdGet8 (PcdDebugClearMemoryValue));
}
-
/**
Returns TRUE if ASSERT() macros are enabled.
@@ -269,10 +262,9 @@ DebugAssertEnabled ( VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG()macros are enabled.
@@ -290,10 +282,9 @@ DebugPrintEnabled ( VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG_CODE()macros are enabled.
@@ -311,10 +302,9 @@ DebugCodeEnabled ( VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);
}
-
/**
Returns TRUE if DEBUG_CLEAR_MEMORY()macro is enabled.
@@ -332,5 +322,5 @@ DebugClearMemoryEnabled ( VOID
)
{
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);
}
diff --git a/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c b/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c index b6a07dd466..5ff8a5b7a6 100644 --- a/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c +++ b/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c @@ -13,7 +13,6 @@ #include <Library/SemihostLib.h>
#include <Library/SerialPortLib.h>
-
/*
Programmed hardware of Serial port.
@@ -51,55 +50,50 @@ SerialPortInitialize ( UINTN
EFIAPI
SerialPortWrite (
- IN UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
{
- UINT8 PrintBuffer[PRINT_BUFFER_SIZE];
- UINTN SourceIndex;
- UINTN DestinationIndex;
- UINT8 CurrentCharacter;
+ UINT8 PrintBuffer[PRINT_BUFFER_SIZE];
+ UINTN SourceIndex;
+ UINTN DestinationIndex;
+ UINT8 CurrentCharacter;
SourceIndex = 0;
DestinationIndex = 0;
- while (SourceIndex < NumberOfBytes)
- {
- CurrentCharacter = Buffer[SourceIndex++];
+ while (SourceIndex < NumberOfBytes) {
+ CurrentCharacter = Buffer[SourceIndex++];
- switch (CurrentCharacter)
- {
+ switch (CurrentCharacter) {
case '\r':
- continue;
+ continue;
case '\n':
- PrintBuffer[DestinationIndex++] = ' ';
- // fall through
+ PrintBuffer[DestinationIndex++] = ' ';
+ // fall through
default:
- PrintBuffer[DestinationIndex++] = CurrentCharacter;
- break;
- }
+ PrintBuffer[DestinationIndex++] = CurrentCharacter;
+ break;
+ }
- if (DestinationIndex > PRINT_BUFFER_THRESHOLD)
- {
- PrintBuffer[DestinationIndex] = '\0';
- SemihostWriteString ((CHAR8 *) PrintBuffer);
+ if (DestinationIndex > PRINT_BUFFER_THRESHOLD) {
+ PrintBuffer[DestinationIndex] = '\0';
+ SemihostWriteString ((CHAR8 *)PrintBuffer);
- DestinationIndex = 0;
- }
+ DestinationIndex = 0;
+ }
}
- if (DestinationIndex > 0)
- {
- PrintBuffer[DestinationIndex] = '\0';
- SemihostWriteString ((CHAR8 *) PrintBuffer);
+ if (DestinationIndex > 0) {
+ PrintBuffer[DestinationIndex] = '\0';
+ SemihostWriteString ((CHAR8 *)PrintBuffer);
}
return NumberOfBytes;
}
-
/**
Read data from serial device and save the datas in buffer.
@@ -113,16 +107,14 @@ SerialPortWrite ( UINTN
EFIAPI
SerialPortRead (
- OUT UINT8 *Buffer,
- IN UINTN NumberOfBytes
-)
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+ )
{
*Buffer = SemihostReadCharacter ();
return 1;
}
-
-
/**
Check to see if any data is available to be read from the debug device.
@@ -139,4 +131,3 @@ SerialPortPoll ( // Since SemiHosting read character is blocking always say we have a char ready?
return SemihostConnectionSupported ();
}
-
diff --git a/ArmPkg/Library/SemihostLib/SemihostLib.c b/ArmPkg/Library/SemihostLib/SemihostLib.c index d66de71182..9e6fc379d9 100644 --- a/ArmPkg/Library/SemihostLib/SemihostLib.c +++ b/ArmPkg/Library/SemihostLib/SemihostLib.c @@ -23,9 +23,9 @@ SemihostConnectionSupported ( RETURN_STATUS
SemihostFileOpen (
- IN CHAR8 *FileName,
- IN UINT32 Mode,
- OUT UINTN *FileHandle
+ IN CHAR8 *FileName,
+ IN UINT32 Mode,
+ OUT UINTN *FileHandle
)
{
SEMIHOST_FILE_OPEN_BLOCK OpenBlock;
@@ -40,9 +40,9 @@ SemihostFileOpen ( FileName++;
}
- OpenBlock.FileName = FileName;
- OpenBlock.Mode = Mode;
- OpenBlock.NameLength = AsciiStrLen(FileName);
+ OpenBlock.FileName = FileName;
+ OpenBlock.Mode = Mode;
+ OpenBlock.NameLength = AsciiStrLen (FileName);
Result = SEMIHOST_SYS_OPEN (&OpenBlock);
@@ -124,10 +124,11 @@ SemihostFileWrite ( *Length = SEMIHOST_SYS_WRITE (&WriteBlock);
- if (*Length != 0)
+ if (*Length != 0) {
return RETURN_ABORTED;
- else
+ } else {
return RETURN_SUCCESS;
+ }
}
RETURN_STATUS
@@ -148,7 +149,7 @@ SemihostFileLength ( OUT UINTN *Length
)
{
- INT32 Result;
+ INT32 Result;
if (Length == NULL) {
return RETURN_INVALID_PARAMETER;
@@ -178,7 +179,7 @@ SemihostFileLength ( **/
RETURN_STATUS
-SemihostFileTmpName(
+SemihostFileTmpName (
OUT VOID *Buffer,
IN UINT8 Identifier,
IN UINTN Length
@@ -198,15 +199,15 @@ SemihostFileTmpName( Result = SEMIHOST_SYS_TMPNAME (&TmpNameBlock);
if (Result != 0) {
- return RETURN_ABORTED;
+ return RETURN_ABORTED;
} else {
- return RETURN_SUCCESS;
+ return RETURN_SUCCESS;
}
}
RETURN_STATUS
SemihostFileRemove (
- IN CHAR8 *FileName
+ IN CHAR8 *FileName
)
{
SEMIHOST_FILE_REMOVE_BLOCK RemoveBlock;
@@ -217,8 +218,8 @@ SemihostFileRemove ( FileName++;
}
- RemoveBlock.FileName = FileName;
- RemoveBlock.NameLength = AsciiStrLen(FileName);
+ RemoveBlock.FileName = FileName;
+ RemoveBlock.NameLength = AsciiStrLen (FileName);
Result = SEMIHOST_SYS_REMOVE (&RemoveBlock);
@@ -241,7 +242,7 @@ SemihostFileRemove ( **/
RETURN_STATUS
-SemihostFileRename(
+SemihostFileRename (
IN CHAR8 *FileName,
IN CHAR8 *NewFileName
)
@@ -261,9 +262,9 @@ SemihostFileRename( Result = SEMIHOST_SYS_RENAME (&RenameBlock);
if (Result != 0) {
- return RETURN_ABORTED;
+ return RETURN_ABORTED;
} else {
- return RETURN_SUCCESS;
+ return RETURN_SUCCESS;
}
}
@@ -277,7 +278,7 @@ SemihostReadCharacter ( VOID
SemihostWriteCharacter (
- IN CHAR8 Character
+ IN CHAR8 Character
)
{
SEMIHOST_SYS_WRITEC (&Character);
@@ -285,7 +286,7 @@ SemihostWriteCharacter ( VOID
SemihostWriteString (
- IN CHAR8 *String
+ IN CHAR8 *String
)
{
SEMIHOST_SYS_WRITE0 (String);
@@ -293,13 +294,13 @@ SemihostWriteString ( UINT32
SemihostSystem (
- IN CHAR8 *CommandLine
+ IN CHAR8 *CommandLine
)
{
- SEMIHOST_SYSTEM_BLOCK SystemBlock;
+ SEMIHOST_SYSTEM_BLOCK SystemBlock;
SystemBlock.CommandLine = CommandLine;
- SystemBlock.CommandLength = AsciiStrLen(CommandLine);
+ SystemBlock.CommandLength = AsciiStrLen (CommandLine);
return SEMIHOST_SYS_SYSTEM (&SystemBlock);
}
diff --git a/ArmPkg/Library/SemihostLib/SemihostPrivate.h b/ArmPkg/Library/SemihostLib/SemihostPrivate.h index 8864726116..22abbf3bae 100644 --- a/ArmPkg/Library/SemihostLib/SemihostPrivate.h +++ b/ArmPkg/Library/SemihostLib/SemihostPrivate.h @@ -11,14 +11,14 @@ #define SEMIHOST_PRIVATE_H_
typedef struct {
- CHAR8 *FileName;
+ CHAR8 *FileName;
UINTN Mode;
UINTN NameLength;
} SEMIHOST_FILE_OPEN_BLOCK;
typedef struct {
UINTN Handle;
- VOID *Buffer;
+ VOID *Buffer;
UINTN Length;
} SEMIHOST_FILE_READ_WRITE_BLOCK;
@@ -28,127 +28,127 @@ typedef struct { } SEMIHOST_FILE_SEEK_BLOCK;
typedef struct {
- VOID *Buffer;
+ VOID *Buffer;
UINTN Identifier;
UINTN Length;
} SEMIHOST_FILE_TMPNAME_BLOCK;
typedef struct {
- CHAR8 *FileName;
+ CHAR8 *FileName;
UINTN NameLength;
} SEMIHOST_FILE_REMOVE_BLOCK;
typedef struct {
- CHAR8 *FileName;
+ CHAR8 *FileName;
UINTN FileNameLength;
- CHAR8 *NewFileName;
+ CHAR8 *NewFileName;
UINTN NewFileNameLength;
} SEMIHOST_FILE_RENAME_BLOCK;
typedef struct {
- CHAR8 *CommandLine;
+ CHAR8 *CommandLine;
UINTN CommandLength;
} SEMIHOST_SYSTEM_BLOCK;
-#if defined(__CC_ARM)
+#if defined (__CC_ARM)
-#if defined(__thumb__)
-#define SWI 0xAB
-#else
-#define SWI 0x123456
-#endif
+ #if defined (__thumb__)
+#define SWI 0xAB
+ #else
+#define SWI 0x123456
+ #endif
#define SEMIHOST_SUPPORTED TRUE
-__swi(SWI)
+__swi (SWI)
INT32
-_Semihost_SYS_OPEN(
- IN UINTN SWI_0x01,
- IN SEMIHOST_FILE_OPEN_BLOCK *OpenBlock
+_Semihost_SYS_OPEN (
+ IN UINTN SWI_0x01,
+ IN SEMIHOST_FILE_OPEN_BLOCK *OpenBlock
);
-__swi(SWI)
+__swi (SWI)
INT32
-_Semihost_SYS_CLOSE(
- IN UINTN SWI_0x02,
- IN UINT32 *Handle
+_Semihost_SYS_CLOSE (
+ IN UINTN SWI_0x02,
+ IN UINT32 *Handle
);
-__swi(SWI)
+__swi (SWI)
VOID
-_Semihost_SYS_WRITEC(
- IN UINTN SWI_0x03,
- IN CHAR8 *Character
+_Semihost_SYS_WRITEC (
+ IN UINTN SWI_0x03,
+ IN CHAR8 *Character
);
-__swi(SWI)
+__swi (SWI)
VOID
-_Semihost_SYS_WRITE0(
- IN UINTN SWI_0x04,
- IN CHAR8 *String
+_Semihost_SYS_WRITE0 (
+ IN UINTN SWI_0x04,
+ IN CHAR8 *String
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_WRITE(
- IN UINTN SWI_0x05,
- IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *WriteBlock
+_Semihost_SYS_WRITE (
+ IN UINTN SWI_0x05,
+ IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *WriteBlock
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_READ(
- IN UINTN SWI_0x06,
- IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *ReadBlock
+_Semihost_SYS_READ (
+ IN UINTN SWI_0x06,
+ IN OUT SEMIHOST_FILE_READ_WRITE_BLOCK *ReadBlock
);
-__swi(SWI)
+__swi (SWI)
CHAR8
-_Semihost_SYS_READC(
- IN UINTN SWI_0x07,
- IN UINTN Zero
+_Semihost_SYS_READC (
+ IN UINTN SWI_0x07,
+ IN UINTN Zero
);
-__swi(SWI)
+__swi (SWI)
INT32
-_Semihost_SYS_SEEK(
- IN UINTN SWI_0x0A,
- IN SEMIHOST_FILE_SEEK_BLOCK *SeekBlock
+_Semihost_SYS_SEEK (
+ IN UINTN SWI_0x0A,
+ IN SEMIHOST_FILE_SEEK_BLOCK *SeekBlock
);
-__swi(SWI)
+__swi (SWI)
INT32
-_Semihost_SYS_FLEN(
- IN UINTN SWI_0x0C,
- IN UINT32 *Handle
+_Semihost_SYS_FLEN (
+ IN UINTN SWI_0x0C,
+ IN UINT32 *Handle
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_TMPNAME(
- IN UINTN SWI_0x0D,
- IN SEMIHOST_FILE_TMPNAME_BLOCK *TmpNameBlock
+_Semihost_SYS_TMPNAME (
+ IN UINTN SWI_0x0D,
+ IN SEMIHOST_FILE_TMPNAME_BLOCK *TmpNameBlock
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_REMOVE(
- IN UINTN SWI_0x0E,
- IN SEMIHOST_FILE_REMOVE_BLOCK *RemoveBlock
+_Semihost_SYS_REMOVE (
+ IN UINTN SWI_0x0E,
+ IN SEMIHOST_FILE_REMOVE_BLOCK *RemoveBlock
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_RENAME(
- IN UINTN SWI_0x0F,
- IN SEMIHOST_FILE_RENAME_BLOCK *RenameBlock
+_Semihost_SYS_RENAME (
+ IN UINTN SWI_0x0F,
+ IN SEMIHOST_FILE_RENAME_BLOCK *RenameBlock
);
-__swi(SWI)
+__swi (SWI)
UINT32
-_Semihost_SYS_SYSTEM(
- IN UINTN SWI_0x12,
- IN SEMIHOST_SYSTEM_BLOCK *SystemBlock
+_Semihost_SYS_SYSTEM (
+ IN UINTN SWI_0x12,
+ IN SEMIHOST_SYSTEM_BLOCK *SystemBlock
);
#define SEMIHOST_SYS_OPEN(OpenBlock) _Semihost_SYS_OPEN(0x01, OpenBlock)
@@ -165,14 +165,14 @@ _Semihost_SYS_SYSTEM( #define SEMIHOST_SYS_RENAME(RenameBlock) _Semihost_SYS_RENAME(0x0F, RenameBlock)
#define SEMIHOST_SYS_SYSTEM(SystemBlock) _Semihost_SYS_SYSTEM(0x12, SystemBlock)
-#elif defined(__GNUC__) // __CC_ARM
+#elif defined (__GNUC__) // __CC_ARM
#define SEMIHOST_SUPPORTED TRUE
UINT32
GccSemihostCall (
- IN UINT32 Operation,
- IN UINTN SystemBlockAddress
+ IN UINT32 Operation,
+ IN UINTN SystemBlockAddress
); // __attribute__ ((interrupt ("SVC")));
#define SEMIHOST_SYS_OPEN(OpenBlock) GccSemihostCall(0x01, (UINTN)(OpenBlock))
@@ -193,8 +193,8 @@ GccSemihostCall ( #define SEMIHOST_SUPPORTED FALSE
-#define SEMIHOST_SYS_OPEN(OpenBlock) (-1)
-#define SEMIHOST_SYS_CLOSE(Handle) (-1)
+#define SEMIHOST_SYS_OPEN(OpenBlock) (-1)
+#define SEMIHOST_SYS_CLOSE(Handle) (-1)
#define SEMIHOST_SYS_WRITE0(String)
#define SEMIHOST_SYS_WRITEC(Character)
#define SEMIHOST_SYS_WRITE(WriteBlock) (0)
diff --git a/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c index 20f873e680..d55aff7620 100644 --- a/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c +++ b/ArmPkg/Library/StandaloneMmMmuLib/ArmMmuStandaloneMmLib.c @@ -45,8 +45,8 @@ STATIC
EFI_STATUS
SendMemoryPermissionRequest (
- IN OUT ARM_SVC_ARGS *SvcArgs,
- OUT INT32 *RetVal
+ IN OUT ARM_SVC_ARGS *SvcArgs,
+ OUT INT32 *RetVal
)
{
if ((SvcArgs == NULL) || (RetVal == NULL)) {
@@ -148,8 +148,8 @@ SendMemoryPermissionRequest ( STATIC
EFI_STATUS
GetMemoryPermissions (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- OUT UINT32 *MemoryAttributes
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ OUT UINT32 *MemoryAttributes
)
{
EFI_STATUS Status;
@@ -207,9 +207,9 @@ GetMemoryPermissions ( STATIC
EFI_STATUS
RequestMemoryPermissionChange (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length,
- IN UINT32 Permissions
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length,
+ IN UINT32 Permissions
)
{
INT32 Ret;
@@ -239,13 +239,13 @@ RequestMemoryPermissionChange ( EFI_STATUS
ArmSetMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINT32 MemoryAttributes;
- UINT32 CodePermission;
+ EFI_STATUS Status;
+ UINT32 MemoryAttributes;
+ UINT32 CodePermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
@@ -256,18 +256,19 @@ ArmSetMemoryRegionNoExec ( MemoryAttributes | CodePermission
);
}
+
return Status;
}
EFI_STATUS
ArmClearMemoryRegionNoExec (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINT32 MemoryAttributes;
- UINT32 CodePermission;
+ EFI_STATUS Status;
+ UINT32 MemoryAttributes;
+ UINT32 CodePermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
@@ -278,18 +279,19 @@ ArmClearMemoryRegionNoExec ( MemoryAttributes & ~CodePermission
);
}
+
return Status;
}
EFI_STATUS
ArmSetMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINT32 MemoryAttributes;
- UINT32 DataPermission;
+ EFI_STATUS Status;
+ UINT32 MemoryAttributes;
+ UINT32 DataPermission;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
@@ -300,28 +302,32 @@ ArmSetMemoryRegionReadOnly ( MemoryAttributes | DataPermission
);
}
+
return Status;
}
EFI_STATUS
ArmClearMemoryRegionReadOnly (
- IN EFI_PHYSICAL_ADDRESS BaseAddress,
- IN UINT64 Length
+ IN EFI_PHYSICAL_ADDRESS BaseAddress,
+ IN UINT64 Length
)
{
- EFI_STATUS Status;
- UINT32 MemoryAttributes;
- UINT32 PermissionRequest;
+ EFI_STATUS Status;
+ UINT32 MemoryAttributes;
+ UINT32 PermissionRequest;
Status = GetMemoryPermissions (BaseAddress, &MemoryAttributes);
if (!EFI_ERROR (Status)) {
- PermissionRequest = SET_MEM_ATTR_MAKE_PERM_REQUEST (SET_MEM_ATTR_DATA_PERM_RW,
- MemoryAttributes);
+ PermissionRequest = SET_MEM_ATTR_MAKE_PERM_REQUEST (
+ SET_MEM_ATTR_DATA_PERM_RW,
+ MemoryAttributes
+ );
return RequestMemoryPermissionChange (
BaseAddress,
Length,
PermissionRequest
);
}
+
return Status;
}
diff --git a/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c b/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c index 3125269735..98970407a6 100644 --- a/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c +++ b/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c @@ -15,7 +15,6 @@ #include <Library/HiiLib.h>
#include <Library/OemMiscLib.h>
-
/** Gets the CPU frequency of the specified processor.
@param ProcessorIndex Index of the processor to get the frequency for.
@@ -25,7 +24,7 @@ UINTN
EFIAPI
OemGetCpuFreq (
- IN UINT8 ProcessorIndex
+ IN UINT8 ProcessorIndex
)
{
ASSERT (FALSE);
@@ -45,10 +44,10 @@ OemGetCpuFreq ( BOOLEAN
EFIAPI
OemGetProcessorInformation (
- IN UINTN ProcessorIndex,
- IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
- IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
- IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
+ IN UINTN ProcessorIndex,
+ IN OUT PROCESSOR_STATUS_DATA *ProcessorStatus,
+ IN OUT PROCESSOR_CHARACTERISTIC_FLAGS *ProcessorCharacteristics,
+ IN OUT OEM_MISC_PROCESSOR_DATA *MiscProcessorData
)
{
ASSERT (FALSE);
@@ -68,11 +67,11 @@ OemGetProcessorInformation ( BOOLEAN
EFIAPI
OemGetCacheInformation (
- IN UINT8 ProcessorIndex,
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache,
- IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
+ IN UINT8 ProcessorIndex,
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache,
+ IN OUT SMBIOS_TABLE_TYPE7 *SmbiosCacheTable
)
{
ASSERT (FALSE);
@@ -116,7 +115,7 @@ OemGetChassisType ( BOOLEAN
EFIAPI
OemIsProcessorPresent (
- IN UINTN ProcessorIndex
+ IN UINTN ProcessorIndex
)
{
ASSERT (FALSE);
@@ -132,9 +131,9 @@ OemIsProcessorPresent ( VOID
EFIAPI
OemUpdateSmbiosInfo (
- IN EFI_HII_HANDLE HiiHandle,
- IN EFI_STRING_ID TokenToUpdate,
- IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
+ IN EFI_HII_HANDLE HiiHandle,
+ IN EFI_STRING_ID TokenToUpdate,
+ IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
)
{
ASSERT (FALSE);
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c index cbdf6df01e..a4f98e6a81 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c @@ -29,12 +29,12 @@ #include "SmbiosProcessor.h"
-extern UINT8 ProcessorSubClassStrings[];
+extern UINT8 ProcessorSubClassStrings[];
-#define CACHE_SOCKETED_SHIFT 3
-#define CACHE_LOCATION_SHIFT 5
-#define CACHE_ENABLED_SHIFT 7
-#define CACHE_OPERATION_MODE_SHIFT 8
+#define CACHE_SOCKETED_SHIFT 3
+#define CACHE_LOCATION_SHIFT 5
+#define CACHE_ENABLED_SHIFT 7
+#define CACHE_OPERATION_MODE_SHIFT 8
typedef enum {
CacheModeWriteThrough = 0, ///< Cache is write-through
@@ -52,51 +52,51 @@ typedef enum { CacheLocationMax
} CACHE_LOCATION;
-EFI_HII_HANDLE mHiiHandle;
+EFI_HII_HANDLE mHiiHandle;
EFI_SMBIOS_PROTOCOL *mSmbios;
-SMBIOS_TABLE_TYPE4 mSmbiosProcessorTableTemplate = {
- { // Hdr
- EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // Type
- sizeof (SMBIOS_TABLE_TYPE4), // Length
- 0 // Handle
- },
- 1, // Socket
- CentralProcessor, // ProcessorType
- ProcessorFamilyIndicatorFamily2, // ProcessorFamily
- 2, // ProcessorManufacture
- { // ProcessorId
- { // Signature
- 0
- },
- { // FeatureFlags
- 0
- }
- },
- 3, // ProcessorVersion
- { // Voltage
+SMBIOS_TABLE_TYPE4 mSmbiosProcessorTableTemplate = {
+ { // Hdr
+ EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, // Type
+ sizeof (SMBIOS_TABLE_TYPE4), // Length
+ 0 // Handle
+ },
+ 1, // Socket
+ CentralProcessor, // ProcessorType
+ ProcessorFamilyIndicatorFamily2, // ProcessorFamily
+ 2, // ProcessorManufacture
+ { // ProcessorId
+ { // Signature
0
},
- 0, // ExternalClock
- 0, // MaxSpeed
- 0, // CurrentSpeed
- 0, // Status
- ProcessorUpgradeUnknown, // ProcessorUpgrade
- 0xFFFF, // L1CacheHandle
- 0xFFFF, // L2CacheHandle
- 0xFFFF, // L3CacheHandle
- 4, // SerialNumber
- 5, // AssetTag
- 6, // PartNumber
- 0, // CoreCount
- 0, //EnabledCoreCount
- 0, // ThreadCount
- 0, // ProcessorCharacteristics
- ProcessorFamilyARM, // ProcessorFamily2
- 0, // CoreCount2
- 0, // EnabledCoreCount2
- 0 // ThreadCount2
+ { // FeatureFlags
+ 0
+ }
+ },
+ 3, // ProcessorVersion
+ { // Voltage
+ 0
+ },
+ 0, // ExternalClock
+ 0, // MaxSpeed
+ 0, // CurrentSpeed
+ 0, // Status
+ ProcessorUpgradeUnknown, // ProcessorUpgrade
+ 0xFFFF, // L1CacheHandle
+ 0xFFFF, // L2CacheHandle
+ 0xFFFF, // L3CacheHandle
+ 4, // SerialNumber
+ 5, // AssetTag
+ 6, // PartNumber
+ 0, // CoreCount
+ 0, // EnabledCoreCount
+ 0, // ThreadCount
+ 0, // ProcessorCharacteristics
+ ProcessorFamilyARM, // ProcessorFamily2
+ 0, // CoreCount2
+ 0, // EnabledCoreCount2
+ 0 // ThreadCount2
};
/** Sets the HII variable `StringId` is `Pcd` isn't empty.
@@ -122,7 +122,7 @@ SMBIOS_TABLE_TYPE4 mSmbiosProcessorTableTemplate = { **/
UINT16
GetCpuFrequency (
- IN UINT8 ProcessorNumber
+ IN UINT8 ProcessorNumber
)
{
return (UINT16)(OemGetCpuFreq (ProcessorNumber) / 1000 / 1000);
@@ -140,30 +140,35 @@ GetCpuFrequency ( **/
UINTN
GetCacheSocketStr (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache,
- OUT CHAR16 *CacheSocketStr
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache,
+ OUT CHAR16 *CacheSocketStr
)
{
- UINTN CacheSocketStrLen;
+ UINTN CacheSocketStrLen;
- if (CacheLevel == CpuCacheL1 && !DataCache && !UnifiedCache) {
+ if ((CacheLevel == CpuCacheL1) && !DataCache && !UnifiedCache) {
CacheSocketStrLen = UnicodeSPrint (
CacheSocketStr,
SMBIOS_STRING_MAX_LENGTH - 1,
L"L%x Instruction Cache",
- CacheLevel);
- } else if (CacheLevel == CpuCacheL1 && DataCache) {
- CacheSocketStrLen = UnicodeSPrint (CacheSocketStr,
+ CacheLevel
+ );
+ } else if ((CacheLevel == CpuCacheL1) && DataCache) {
+ CacheSocketStrLen = UnicodeSPrint (
+ CacheSocketStr,
SMBIOS_STRING_MAX_LENGTH - 1,
L"L%x Data Cache",
- CacheLevel);
+ CacheLevel
+ );
} else {
- CacheSocketStrLen = UnicodeSPrint (CacheSocketStr,
+ CacheSocketStrLen = UnicodeSPrint (
+ CacheSocketStr,
SMBIOS_STRING_MAX_LENGTH - 1,
L"L%x Cache",
- CacheLevel);
+ CacheLevel
+ );
}
return CacheSocketStrLen;
@@ -180,16 +185,16 @@ GetCacheSocketStr ( **/
VOID
ConfigureCacheArchitectureInformation (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache,
- OUT SMBIOS_TABLE_TYPE7 *Type7Record
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache,
+ OUT SMBIOS_TABLE_TYPE7 *Type7Record
)
{
- UINT8 Associativity;
- UINT32 CacheSize32;
- UINT16 CacheSize16;
- UINT64 CacheSize64;
+ UINT8 Associativity;
+ UINT32 CacheSize32;
+ UINT16 CacheSize16;
+ UINT64 CacheSize64;
if (!DataCache && !UnifiedCache) {
Type7Record->SystemCacheType = CacheTypeInstruction;
@@ -198,18 +203,20 @@ ConfigureCacheArchitectureInformation ( } else if (UnifiedCache) {
Type7Record->SystemCacheType = CacheTypeUnified;
} else {
- ASSERT(FALSE);
+ ASSERT (FALSE);
}
- CacheSize64 = SmbiosProcessorGetCacheSize (CacheLevel,
- DataCache,
- UnifiedCache
- );
+ CacheSize64 = SmbiosProcessorGetCacheSize (
+ CacheLevel,
+ DataCache,
+ UnifiedCache
+ );
- Associativity = SmbiosProcessorGetCacheAssociativity (CacheLevel,
- DataCache,
- UnifiedCache
- );
+ Associativity = SmbiosProcessorGetCacheAssociativity (
+ CacheLevel,
+ DataCache,
+ UnifiedCache
+ );
CacheSize64 /= 1024; // Minimum granularity is 1K
@@ -230,10 +237,10 @@ ConfigureCacheArchitectureInformation ( CacheSize16 = -1;
}
- Type7Record->MaximumCacheSize = CacheSize16;
- Type7Record->InstalledSize = CacheSize16;
+ Type7Record->MaximumCacheSize = CacheSize16;
+ Type7Record->InstalledSize = CacheSize16;
Type7Record->MaximumCacheSize2 = CacheSize32;
- Type7Record->InstalledSize2 = CacheSize32;
+ Type7Record->InstalledSize2 = CacheSize32;
switch (Associativity) {
case 2:
@@ -278,7 +285,6 @@ ConfigureCacheArchitectureInformation ( (CacheLevel - 1);
}
-
/** Allocates and initializes an SMBIOS_TABLE_TYPE7 structure.
@param[in] CacheLevel The cache level (L1-L7).
@@ -289,9 +295,9 @@ ConfigureCacheArchitectureInformation ( **/
SMBIOS_TABLE_TYPE7 *
AllocateAndInitCacheInformation (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
)
{
SMBIOS_TABLE_TYPE7 *Type7Record;
@@ -303,33 +309,35 @@ AllocateAndInitCacheInformation ( // Allocate and fetch the cache description
StringBufferSize = sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH;
- CacheSocketStr = AllocateZeroPool (StringBufferSize);
+ CacheSocketStr = AllocateZeroPool (StringBufferSize);
if (CacheSocketStr == NULL) {
return NULL;
}
- CacheSocketStrLen = GetCacheSocketStr (CacheLevel,
- DataCache,
- UnifiedCache,
- CacheSocketStr);
+ CacheSocketStrLen = GetCacheSocketStr (
+ CacheLevel,
+ DataCache,
+ UnifiedCache,
+ CacheSocketStr
+ );
- TableSize = sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1;
+ TableSize = sizeof (SMBIOS_TABLE_TYPE7) + CacheSocketStrLen + 1 + 1;
Type7Record = AllocateZeroPool (TableSize);
if (Type7Record == NULL) {
- FreePool(CacheSocketStr);
+ FreePool (CacheSocketStr);
return NULL;
}
- Type7Record->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;
+ Type7Record->Hdr.Type = EFI_SMBIOS_TYPE_CACHE_INFORMATION;
Type7Record->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE7);
Type7Record->Hdr.Handle = SMBIOS_HANDLE_PI_RESERVED;
Type7Record->SocketDesignation = 1;
Type7Record->SupportedSRAMType.Unknown = 1;
- Type7Record->CurrentSRAMType.Unknown = 1;
- Type7Record->CacheSpeed = 0;
- Type7Record->ErrorCorrectionType = CacheErrorUnknown;
+ Type7Record->CurrentSRAMType.Unknown = 1;
+ Type7Record->CacheSpeed = 0;
+ Type7Record->ErrorCorrectionType = CacheErrorUnknown;
OptionalStrStart = (CHAR8 *)(Type7Record + 1);
UnicodeStrToAsciiStrS (CacheSocketStr, OptionalStrStart, CacheSocketStrLen + 1);
@@ -349,19 +357,19 @@ AllocateAndInitCacheInformation ( **/
VOID
AddSmbiosCacheTypeTable (
- IN UINTN ProcessorIndex,
- OUT EFI_SMBIOS_HANDLE *L1CacheHandle,
- OUT EFI_SMBIOS_HANDLE *L2CacheHandle,
- OUT EFI_SMBIOS_HANDLE *L3CacheHandle
+ IN UINTN ProcessorIndex,
+ OUT EFI_SMBIOS_HANDLE *L1CacheHandle,
+ OUT EFI_SMBIOS_HANDLE *L2CacheHandle,
+ OUT EFI_SMBIOS_HANDLE *L3CacheHandle
)
{
- EFI_STATUS Status;
- SMBIOS_TABLE_TYPE7 *Type7Record;
- EFI_SMBIOS_HANDLE SmbiosHandle;
- UINT8 CacheLevel;
- UINT8 MaxCacheLevel;
- BOOLEAN DataCacheType;
- BOOLEAN SeparateCaches;
+ EFI_STATUS Status;
+ SMBIOS_TABLE_TYPE7 *Type7Record;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ UINT8 CacheLevel;
+ UINT8 MaxCacheLevel;
+ BOOLEAN DataCacheType;
+ BOOLEAN SeparateCaches;
Status = EFI_SUCCESS;
@@ -385,34 +393,46 @@ AddSmbiosCacheTypeTable ( // process the instruction cache.
for (DataCacheType = 0; DataCacheType <= 1; DataCacheType++) {
// If there's no separate data/instruction cache, skip the second iteration
- if (DataCacheType == 1 && !SeparateCaches) {
+ if ((DataCacheType == 1) && !SeparateCaches) {
continue;
}
- Type7Record = AllocateAndInitCacheInformation (CacheLevel,
- DataCacheType,
- !SeparateCaches
- );
+ Type7Record = AllocateAndInitCacheInformation (
+ CacheLevel,
+ DataCacheType,
+ !SeparateCaches
+ );
if (Type7Record == NULL) {
continue;
}
- ConfigureCacheArchitectureInformation(CacheLevel,
- DataCacheType,
- !SeparateCaches,
- Type7Record
- );
+ ConfigureCacheArchitectureInformation (
+ CacheLevel,
+ DataCacheType,
+ !SeparateCaches,
+ Type7Record
+ );
// Allow the platform to fill in other information such as speed, SRAM type etc.
- if (!OemGetCacheInformation (ProcessorIndex, CacheLevel,
- DataCacheType, !SeparateCaches, Type7Record)) {
+ if (!OemGetCacheInformation (
+ ProcessorIndex,
+ CacheLevel,
+ DataCacheType,
+ !SeparateCaches,
+ Type7Record
+ ))
+ {
continue;
}
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
// Finally, install the table
- Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle,
- (EFI_SMBIOS_TABLE_HEADER *)Type7Record);
+ Status = mSmbios->Add (
+ mSmbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER *)Type7Record
+ );
if (EFI_ERROR (Status)) {
continue;
}
@@ -449,33 +469,33 @@ AddSmbiosCacheTypeTable ( **/
EFI_STATUS
AllocateType4AndSetProcessorInformationStrings (
- SMBIOS_TABLE_TYPE4 **Type4Record,
- UINT8 ProcessorIndex,
- BOOLEAN Populated
+ SMBIOS_TABLE_TYPE4 **Type4Record,
+ UINT8 ProcessorIndex,
+ BOOLEAN Populated
)
{
- EFI_STATUS Status;
- EFI_STRING_ID ProcessorManu;
- EFI_STRING_ID ProcessorVersion;
- EFI_STRING_ID SerialNumber;
- EFI_STRING_ID AssetTag;
- EFI_STRING_ID PartNumber;
- EFI_STRING ProcessorStr;
- EFI_STRING ProcessorManuStr;
- EFI_STRING ProcessorVersionStr;
- EFI_STRING SerialNumberStr;
- EFI_STRING AssetTagStr;
- EFI_STRING PartNumberStr;
- CHAR8 *OptionalStrStart;
- CHAR8 *StrStart;
- UINTN ProcessorStrLen;
- UINTN ProcessorManuStrLen;
- UINTN ProcessorVersionStrLen;
- UINTN SerialNumberStrLen;
- UINTN AssetTagStrLen;
- UINTN PartNumberStrLen;
- UINTN TotalSize;
- UINTN StringBufferSize;
+ EFI_STATUS Status;
+ EFI_STRING_ID ProcessorManu;
+ EFI_STRING_ID ProcessorVersion;
+ EFI_STRING_ID SerialNumber;
+ EFI_STRING_ID AssetTag;
+ EFI_STRING_ID PartNumber;
+ EFI_STRING ProcessorStr;
+ EFI_STRING ProcessorManuStr;
+ EFI_STRING ProcessorVersionStr;
+ EFI_STRING SerialNumberStr;
+ EFI_STRING AssetTagStr;
+ EFI_STRING PartNumberStr;
+ CHAR8 *OptionalStrStart;
+ CHAR8 *StrStart;
+ UINTN ProcessorStrLen;
+ UINTN ProcessorManuStrLen;
+ UINTN ProcessorVersionStrLen;
+ UINTN SerialNumberStrLen;
+ UINTN AssetTagStrLen;
+ UINTN PartNumberStrLen;
+ UINTN TotalSize;
+ UINTN StringBufferSize;
Status = EFI_SUCCESS;
@@ -485,11 +505,11 @@ AllocateType4AndSetProcessorInformationStrings ( AssetTagStr = NULL;
PartNumberStr = NULL;
- ProcessorManu = STRING_TOKEN (STR_PROCESSOR_MANUFACTURE);
- ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_VERSION);
- SerialNumber = STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER);
- AssetTag = STRING_TOKEN (STR_PROCESSOR_ASSET_TAG);
- PartNumber = STRING_TOKEN (STR_PROCESSOR_PART_NUMBER);
+ ProcessorManu = STRING_TOKEN (STR_PROCESSOR_MANUFACTURE);
+ ProcessorVersion = STRING_TOKEN (STR_PROCESSOR_VERSION);
+ SerialNumber = STRING_TOKEN (STR_PROCESSOR_SERIAL_NUMBER);
+ AssetTag = STRING_TOKEN (STR_PROCESSOR_ASSET_TAG);
+ PartNumber = STRING_TOKEN (STR_PROCESSOR_PART_NUMBER);
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorManufacturer, ProcessorManu);
SET_HII_STRING_IF_PCD_NOT_EMPTY (PcdProcessorVersion, ProcessorVersion);
@@ -499,32 +519,36 @@ AllocateType4AndSetProcessorInformationStrings ( // Processor Designation
StringBufferSize = sizeof (CHAR16) * SMBIOS_STRING_MAX_LENGTH;
- ProcessorStr = AllocateZeroPool (StringBufferSize);
+ ProcessorStr = AllocateZeroPool (StringBufferSize);
if (ProcessorStr == NULL) {
return EFI_OUT_OF_RESOURCES;
}
- ProcessorStrLen = UnicodeSPrint (ProcessorStr, StringBufferSize,
- L"CPU%02d", ProcessorIndex + 1);
+ ProcessorStrLen = UnicodeSPrint (
+ ProcessorStr,
+ StringBufferSize,
+ L"CPU%02d",
+ ProcessorIndex + 1
+ );
// Processor Manufacture
- ProcessorManuStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorManu, NULL);
+ ProcessorManuStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorManu, NULL);
ProcessorManuStrLen = StrLen (ProcessorManuStr);
// Processor Version
- ProcessorVersionStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorVersion, NULL);
+ ProcessorVersionStr = HiiGetPackageString (&gEfiCallerIdGuid, ProcessorVersion, NULL);
ProcessorVersionStrLen = StrLen (ProcessorVersionStr);
// Serial Number
- SerialNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber, NULL);
+ SerialNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, SerialNumber, NULL);
SerialNumberStrLen = StrLen (SerialNumberStr);
// Asset Tag
- AssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL);
+ AssetTagStr = HiiGetPackageString (&gEfiCallerIdGuid, AssetTag, NULL);
AssetTagStrLen = StrLen (AssetTagStr);
// Part Number
- PartNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NULL);
+ PartNumberStr = HiiGetPackageString (&gEfiCallerIdGuid, PartNumber, NULL);
PartNumberStrLen = StrLen (PartNumberStr);
TotalSize = sizeof (SMBIOS_TABLE_TYPE4) +
@@ -604,33 +628,33 @@ Exit: **/
EFI_STATUS
AddSmbiosProcessorTypeTable (
- IN UINTN ProcessorIndex
+ IN UINTN ProcessorIndex
)
{
- EFI_STATUS Status;
- SMBIOS_TABLE_TYPE4 *Type4Record;
- EFI_SMBIOS_HANDLE SmbiosHandle;
- EFI_SMBIOS_HANDLE L1CacheHandle;
- EFI_SMBIOS_HANDLE L2CacheHandle;
- EFI_SMBIOS_HANDLE L3CacheHandle;
- UINT8 *LegacyVoltage;
- PROCESSOR_STATUS_DATA ProcessorStatus;
- UINT64 *ProcessorId;
- PROCESSOR_CHARACTERISTIC_FLAGS ProcessorCharacteristics;
- OEM_MISC_PROCESSOR_DATA MiscProcessorData;
- BOOLEAN ProcessorPopulated;
-
- Type4Record = NULL;
-
- MiscProcessorData.Voltage = 0;
- MiscProcessorData.CurrentSpeed = 0;
- MiscProcessorData.CoreCount = 0;
- MiscProcessorData.CoresEnabled = 0;
- MiscProcessorData.ThreadCount = 0;
- MiscProcessorData.MaxSpeed = 0;
- L1CacheHandle = 0xFFFF;
- L2CacheHandle = 0xFFFF;
- L3CacheHandle = 0xFFFF;
+ EFI_STATUS Status;
+ SMBIOS_TABLE_TYPE4 *Type4Record;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ EFI_SMBIOS_HANDLE L1CacheHandle;
+ EFI_SMBIOS_HANDLE L2CacheHandle;
+ EFI_SMBIOS_HANDLE L3CacheHandle;
+ UINT8 *LegacyVoltage;
+ PROCESSOR_STATUS_DATA ProcessorStatus;
+ UINT64 *ProcessorId;
+ PROCESSOR_CHARACTERISTIC_FLAGS ProcessorCharacteristics;
+ OEM_MISC_PROCESSOR_DATA MiscProcessorData;
+ BOOLEAN ProcessorPopulated;
+
+ Type4Record = NULL;
+
+ MiscProcessorData.Voltage = 0;
+ MiscProcessorData.CurrentSpeed = 0;
+ MiscProcessorData.CoreCount = 0;
+ MiscProcessorData.CoresEnabled = 0;
+ MiscProcessorData.ThreadCount = 0;
+ MiscProcessorData.MaxSpeed = 0;
+ L1CacheHandle = 0xFFFF;
+ L2CacheHandle = 0xFFFF;
+ L3CacheHandle = 0xFFFF;
ProcessorPopulated = OemIsProcessorPresent (ProcessorIndex);
@@ -643,54 +667,70 @@ AddSmbiosProcessorTypeTable ( return Status;
}
- OemGetProcessorInformation (ProcessorIndex,
- &ProcessorStatus,
- (PROCESSOR_CHARACTERISTIC_FLAGS*)
- &Type4Record->ProcessorCharacteristics,
- &MiscProcessorData);
+ OemGetProcessorInformation (
+ ProcessorIndex,
+ &ProcessorStatus,
+ (PROCESSOR_CHARACTERISTIC_FLAGS *)
+ &Type4Record->ProcessorCharacteristics,
+ &MiscProcessorData
+ );
if (ProcessorPopulated) {
- AddSmbiosCacheTypeTable (ProcessorIndex, &L1CacheHandle,
- &L2CacheHandle, &L3CacheHandle);
+ AddSmbiosCacheTypeTable (
+ ProcessorIndex,
+ &L1CacheHandle,
+ &L2CacheHandle,
+ &L3CacheHandle
+ );
}
- LegacyVoltage = (UINT8*)&Type4Record->Voltage;
-
- *LegacyVoltage = MiscProcessorData.Voltage;
- Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;
- Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;
- Type4Record->Status = ProcessorStatus.Data;
- Type4Record->L1CacheHandle = L1CacheHandle;
- Type4Record->L2CacheHandle = L2CacheHandle;
- Type4Record->L3CacheHandle = L3CacheHandle;
- Type4Record->CoreCount = MiscProcessorData.CoreCount;
- Type4Record->CoreCount2 = MiscProcessorData.CoreCount;
- Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;
- Type4Record->EnabledCoreCount2 = MiscProcessorData.CoresEnabled;
- Type4Record->ThreadCount = MiscProcessorData.ThreadCount;
- Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;
-
- Type4Record->CurrentSpeed = GetCpuFrequency (ProcessorIndex);
+ LegacyVoltage = (UINT8 *)&Type4Record->Voltage;
+
+ *LegacyVoltage = MiscProcessorData.Voltage;
+ Type4Record->CurrentSpeed = MiscProcessorData.CurrentSpeed;
+ Type4Record->MaxSpeed = MiscProcessorData.MaxSpeed;
+ Type4Record->Status = ProcessorStatus.Data;
+ Type4Record->L1CacheHandle = L1CacheHandle;
+ Type4Record->L2CacheHandle = L2CacheHandle;
+ Type4Record->L3CacheHandle = L3CacheHandle;
+ Type4Record->CoreCount = MiscProcessorData.CoreCount;
+ Type4Record->CoreCount2 = MiscProcessorData.CoreCount;
+ Type4Record->EnabledCoreCount = MiscProcessorData.CoresEnabled;
+ Type4Record->EnabledCoreCount2 = MiscProcessorData.CoresEnabled;
+ Type4Record->ThreadCount = MiscProcessorData.ThreadCount;
+ Type4Record->ThreadCount2 = MiscProcessorData.ThreadCount;
+
+ Type4Record->CurrentSpeed = GetCpuFrequency (ProcessorIndex);
Type4Record->ExternalClock =
(UINT16)(SmbiosGetExternalClockFrequency () / 1000 / 1000);
- ProcessorId = (UINT64*)&Type4Record->ProcessorId;
+ ProcessorId = (UINT64 *)&Type4Record->ProcessorId;
*ProcessorId = SmbiosGetProcessorId ();
- ProcessorCharacteristics = SmbiosGetProcessorCharacteristics ();
- Type4Record->ProcessorCharacteristics |= *((UINT64*)&ProcessorCharacteristics);
+ ProcessorCharacteristics = SmbiosGetProcessorCharacteristics ();
+ Type4Record->ProcessorCharacteristics |= *((UINT64 *)&ProcessorCharacteristics);
- Type4Record->ProcessorFamily = SmbiosGetProcessorFamily ();
+ Type4Record->ProcessorFamily = SmbiosGetProcessorFamily ();
Type4Record->ProcessorFamily2 = SmbiosGetProcessorFamily2 ();
SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
- Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle,
- (EFI_SMBIOS_TABLE_HEADER *)Type4Record);
+ Status = mSmbios->Add (
+ mSmbios,
+ NULL,
+ &SmbiosHandle,
+ (EFI_SMBIOS_TABLE_HEADER *)Type4Record
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a]:[%dL] Smbios Type04 Table Log Failed! %r \n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Status
+ ));
}
+
FreePool (Type4Record);
return Status;
@@ -707,18 +747,18 @@ AddSmbiosProcessorTypeTable ( **/
EFI_STATUS
EFIAPI
-ProcessorSubClassEntryPoint(
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+ProcessorSubClassEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
- UINT32 ProcessorIndex;
+ EFI_STATUS Status;
+ UINT32 ProcessorIndex;
//
// Locate dependent protocols
//
- Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID**)&mSmbios);
+ Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID **)&mSmbios);
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", Status));
return Status;
@@ -727,12 +767,13 @@ ProcessorSubClassEntryPoint( //
// Add our default strings to the HII database. They will be modified later.
//
- mHiiHandle = HiiAddPackages (&gEfiCallerIdGuid,
- NULL,
- ProcessorSubClassStrings,
- NULL,
- NULL
- );
+ mHiiHandle = HiiAddPackages (
+ &gEfiCallerIdGuid,
+ NULL,
+ ProcessorSubClassStrings,
+ NULL,
+ NULL
+ );
if (mHiiHandle == NULL) {
return EFI_OUT_OF_RESOURCES;
}
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessor.h b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessor.h index f64d5cd1a1..8eb285d154 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessor.h +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessor.h @@ -30,7 +30,7 @@ SmbiosProcessorGetMaxCacheLevel ( **/
BOOLEAN
SmbiosProcessorHasSeparateCaches (
- UINT8 CacheLevel
+ UINT8 CacheLevel
);
/** Gets the size of the specified cache.
@@ -43,9 +43,9 @@ SmbiosProcessorHasSeparateCaches ( **/
UINT64
SmbiosProcessorGetCacheSize (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
);
/** Gets the associativity of the specified cache.
@@ -58,9 +58,9 @@ SmbiosProcessorGetCacheSize ( **/
UINT32
SmbiosProcessorGetCacheAssociativity (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
);
/** Returns a value for the Processor ID field that conforms to SMBIOS
@@ -69,34 +69,44 @@ SmbiosProcessorGetCacheAssociativity ( @return Processor ID.
**/
UINT64
-SmbiosGetProcessorId (VOID);
+SmbiosGetProcessorId (
+ VOID
+ );
/** Returns the external clock frequency.
@return The external CPU clock frequency.
**/
UINTN
-SmbiosGetExternalClockFrequency (VOID);
+SmbiosGetExternalClockFrequency (
+ VOID
+ );
/** Returns the SMBIOS ProcessorFamily field value.
@return The value for the ProcessorFamily field.
**/
UINT8
-SmbiosGetProcessorFamily (VOID);
+SmbiosGetProcessorFamily (
+ VOID
+ );
/** Returns the ProcessorFamily2 field value.
@return The value for the ProcessorFamily2 field.
**/
UINT16
-SmbiosGetProcessorFamily2 (VOID);
+SmbiosGetProcessorFamily2 (
+ VOID
+ );
/** Returns the SMBIOS Processor Characteristics.
@return Processor Characteristics bitfield.
**/
PROCESSOR_CHARACTERISTIC_FLAGS
-SmbiosGetProcessorCharacteristics (VOID);
+SmbiosGetProcessorCharacteristics (
+ VOID
+ );
#endif // SMBIOS_PROCESSOR_H_
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c index 6fbb95afb2..42d56ad28f 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorAArch64.c @@ -23,19 +23,19 @@ **/
UINT64
SmbiosProcessorGetCacheSize (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
-)
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
+ )
{
- CCSIDR_DATA Ccsidr;
- CSSELR_DATA Csselr;
- BOOLEAN CcidxSupported;
- UINT64 CacheSize;
+ CCSIDR_DATA Ccsidr;
+ CSSELR_DATA Csselr;
+ BOOLEAN CcidxSupported;
+ UINT64 CacheSize;
- Csselr.Data = 0;
+ Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
@@ -43,12 +43,12 @@ SmbiosProcessorGetCacheSize ( if (CcidxSupported) {
CacheSize = (1 << (Ccsidr.BitsCcidxAA64.LineSize + 4)) *
- (Ccsidr.BitsCcidxAA64.Associativity + 1) *
- (Ccsidr.BitsCcidxAA64.NumSets + 1);
+ (Ccsidr.BitsCcidxAA64.Associativity + 1) *
+ (Ccsidr.BitsCcidxAA64.NumSets + 1);
} else {
CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *
- (Ccsidr.BitsNonCcidx.Associativity + 1) *
- (Ccsidr.BitsNonCcidx.NumSets + 1);
+ (Ccsidr.BitsNonCcidx.Associativity + 1) *
+ (Ccsidr.BitsNonCcidx.NumSets + 1);
}
return CacheSize;
@@ -64,19 +64,19 @@ SmbiosProcessorGetCacheSize ( **/
UINT32
SmbiosProcessorGetCacheAssociativity (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
)
{
- CCSIDR_DATA Ccsidr;
- CSSELR_DATA Csselr;
- BOOLEAN CcidxSupported;
- UINT32 Associativity;
+ CCSIDR_DATA Ccsidr;
+ CSSELR_DATA Csselr;
+ BOOLEAN CcidxSupported;
+ UINT32 Associativity;
- Csselr.Data = 0;
+ Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
@@ -90,4 +90,3 @@ SmbiosProcessorGetCacheAssociativity ( return Associativity;
}
-
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c index 7616fca425..ddee0e4489 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArm.c @@ -23,21 +23,21 @@ **/
UINT64
SmbiosProcessorGetCacheSize (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
)
{
- CCSIDR_DATA Ccsidr;
- CCSIDR2_DATA Ccsidr2;
- CSSELR_DATA Csselr;
- BOOLEAN CcidxSupported;
- UINT64 CacheSize;
+ CCSIDR_DATA Ccsidr;
+ CCSIDR2_DATA Ccsidr2;
+ CSSELR_DATA Csselr;
+ BOOLEAN CcidxSupported;
+ UINT64 CacheSize;
// Read the CCSIDR register to get the cache architecture
- Csselr.Data = 0;
+ Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
@@ -45,13 +45,13 @@ SmbiosProcessorGetCacheSize ( if (CcidxSupported) {
Ccsidr2.Data = ReadCCSIDR2 (Csselr.Data);
- CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *
- (Ccsidr.BitsCcidxAA32.Associativity + 1) *
- (Ccsidr2.Bits.NumSets + 1);
+ CacheSize = (1 << (Ccsidr.BitsCcidxAA32.LineSize + 4)) *
+ (Ccsidr.BitsCcidxAA32.Associativity + 1) *
+ (Ccsidr2.Bits.NumSets + 1);
} else {
CacheSize = (1 << (Ccsidr.BitsNonCcidx.LineSize + 4)) *
- (Ccsidr.BitsNonCcidx.Associativity + 1) *
- (Ccsidr.BitsNonCcidx.NumSets + 1);
+ (Ccsidr.BitsNonCcidx.Associativity + 1) *
+ (Ccsidr.BitsNonCcidx.NumSets + 1);
}
return CacheSize;
@@ -67,9 +67,9 @@ SmbiosProcessorGetCacheSize ( **/
UINT32
SmbiosProcessorGetCacheAssociativity (
- IN UINT8 CacheLevel,
- IN BOOLEAN DataCache,
- IN BOOLEAN UnifiedCache
+ IN UINT8 CacheLevel,
+ IN BOOLEAN DataCache,
+ IN BOOLEAN UnifiedCache
)
{
CCSIDR_DATA Ccsidr;
@@ -78,9 +78,9 @@ SmbiosProcessorGetCacheAssociativity ( UINT32 Associativity;
// Read the CCSIDR register to get the cache architecture
- Csselr.Data = 0;
+ Csselr.Data = 0;
Csselr.Bits.Level = CacheLevel - 1;
- Csselr.Bits.InD = (!DataCache && !UnifiedCache);
+ Csselr.Bits.InD = (!DataCache && !UnifiedCache);
Ccsidr.Data = ReadCCSIDR (Csselr.Data);
@@ -94,4 +94,3 @@ SmbiosProcessorGetCacheAssociativity ( return Associativity;
}
-
diff --git a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c index d644cd33d2..7a8c3ca567 100644 --- a/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c +++ b/ArmPkg/Universal/Smbios/ProcessorSubClassDxe/SmbiosProcessorArmCommon.c @@ -27,9 +27,9 @@ SmbiosProcessorGetMaxCacheLevel ( VOID
)
{
- CLIDR_DATA Clidr;
- UINT8 CacheLevel;
- UINT8 MaxCacheLevel;
+ CLIDR_DATA Clidr;
+ UINT8 CacheLevel;
+ UINT8 MaxCacheLevel;
MaxCacheLevel = 0;
@@ -59,12 +59,12 @@ SmbiosProcessorGetMaxCacheLevel ( **/
BOOLEAN
SmbiosProcessorHasSeparateCaches (
- UINT8 CacheLevel
+ UINT8 CacheLevel
)
{
- CLIDR_CACHE_TYPE CacheType;
- CLIDR_DATA Clidr;
- BOOLEAN SeparateCaches;
+ CLIDR_CACHE_TYPE CacheType;
+ CLIDR_DATA Clidr;
+ BOOLEAN SeparateCaches;
SeparateCaches = FALSE;
@@ -88,9 +88,9 @@ HasSmcArm64SocId ( VOID
)
{
- ARM_SMC_ARGS Args;
- INT32 SmcCallStatus;
- BOOLEAN Arm64SocIdSupported;
+ ARM_SMC_ARGS Args;
+ INT32 SmcCallStatus;
+ BOOLEAN Arm64SocIdSupported;
Arm64SocIdSupported = FALSE;
@@ -98,7 +98,7 @@ HasSmcArm64SocId ( ArmCallSmc (&Args);
SmcCallStatus = (INT32)Args.Arg0;
- if (SmcCallStatus < 0 || (SmcCallStatus >> 16) >= 1) {
+ if ((SmcCallStatus < 0) || ((SmcCallStatus >> 16) >= 1)) {
Args.Arg0 = SMCCC_ARCH_FEATURES;
Args.Arg1 = SMCCC_ARCH_SOC_ID;
ArmCallSmc (&Args);
@@ -121,8 +121,8 @@ HasSmcArm64SocId ( **/
EFI_STATUS
SmbiosGetSmcArm64SocId (
- OUT INT32 *Jep106Code,
- OUT INT32 *SocRevision
+ OUT INT32 *Jep106Code,
+ OUT INT32 *SocRevision
)
{
ARM_SMC_ARGS Args;
@@ -166,9 +166,9 @@ SmbiosGetProcessorId ( VOID
)
{
- INT32 Jep106Code;
- INT32 SocRevision;
- UINT64 ProcessorId;
+ INT32 Jep106Code;
+ INT32 SocRevision;
+ UINT64 ProcessorId;
if (HasSmcArm64SocId ()) {
SmbiosGetSmcArm64SocId (&Jep106Code, &SocRevision);
@@ -213,15 +213,15 @@ SmbiosGetProcessorFamily2 ( VOID
)
{
- UINTN MainIdRegister;
- UINT16 ProcessorFamily2;
+ UINTN MainIdRegister;
+ UINT16 ProcessorFamily2;
MainIdRegister = ArmReadMidr ();
if (((MainIdRegister >> 16) & 0xF) < 8) {
ProcessorFamily2 = ProcessorFamilyARM;
} else {
- if (sizeof (VOID*) == 4) {
+ if (sizeof (VOID *) == 4) {
ProcessorFamily2 = ProcessorFamilyARMv7;
} else {
ProcessorFamily2 = ProcessorFamilyARMv8;
@@ -240,7 +240,7 @@ SmbiosGetProcessorCharacteristics ( VOID
)
{
- PROCESSOR_CHARACTERISTIC_FLAGS Characteristics;
+ PROCESSOR_CHARACTERISTIC_FLAGS Characteristics;
ZeroMem (&Characteristics, sizeof (Characteristics));
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h index 4fd37c4cdc..88f60433d5 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMisc.h @@ -20,12 +20,11 @@ //
// Data table entry update function.
//
-typedef EFI_STATUS (EFIAPI SMBIOS_MISC_DATA_FUNCTION) (
+typedef EFI_STATUS (EFIAPI SMBIOS_MISC_DATA_FUNCTION)(
IN VOID *RecordData,
IN EFI_SMBIOS_PROTOCOL *Smbios
);
-
//
// Data table entry definition.
//
@@ -33,11 +32,10 @@ typedef struct { //
// intermediate input data for SMBIOS record
//
- VOID *RecordData;
- SMBIOS_MISC_DATA_FUNCTION *Function;
+ VOID *RecordData;
+ SMBIOS_MISC_DATA_FUNCTION *Function;
} SMBIOS_MISC_DATA_TABLE;
-
//
// SMBIOS table extern definitions
//
@@ -45,7 +43,6 @@ typedef struct { extern NAME1 NAME2 ## Data; \
extern SMBIOS_MISC_DATA_FUNCTION NAME3 ## Function;
-
//
// SMBIOS data table entries
//
@@ -73,15 +70,14 @@ extern SMBIOS_MISC_DATA_FUNCTION NAME3 ## Function; //
// Data Table Array Entries
//
-extern EFI_HII_HANDLE mSmbiosMiscHiiHandle;
+extern EFI_HII_HANDLE mSmbiosMiscHiiHandle;
-typedef struct _SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{
- UINT8 *LanguageSignature;
- EFI_STRING_ID InstallableLanguageLongString;
- EFI_STRING_ID InstallableLanguageAbbreviateString;
+typedef struct _SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING {
+ UINT8 *LanguageSignature;
+ EFI_STRING_ID InstallableLanguageLongString;
+ EFI_STRING_ID InstallableLanguageAbbreviateString;
} SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING;
-
/**
Adds an SMBIOS record.
@@ -101,8 +97,8 @@ typedef struct _SMBIOS_TYPE13_BIOS_LANGUAGE_INFORMATION_STRING{ **/
EFI_STATUS
SmbiosMiscAddRecord (
- IN UINT8 *Buffer,
- IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL
+ IN UINT8 *Buffer,
+ IN OUT EFI_SMBIOS_HANDLE *SmbiosHandle OPTIONAL
);
/**
@@ -114,21 +110,21 @@ SmbiosMiscAddRecord ( **/
VOID
-SmbiosMiscGetLinkTypeHandle(
- IN UINT8 SmbiosType,
- OUT UINT16 **HandleArray,
- OUT UINTN *HandleCount
+SmbiosMiscGetLinkTypeHandle (
+ IN UINT8 SmbiosType,
+ OUT UINT16 **HandleArray,
+ OUT UINTN *HandleCount
);
//
// Data Table Array
//
-extern SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[];
+extern SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[];
//
// Data Table Array Entries
//
-extern UINTN mSmbiosMiscDataTableEntries;
-extern UINT8 mSmbiosMiscDxeStrings[];
+extern UINTN mSmbiosMiscDataTableEntries;
+extern UINT8 mSmbiosMiscDxeStrings[];
#endif // SMBIOS_MISC_H_
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c index ac16c3a268..c1b866fcb8 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscDataTable.c @@ -13,50 +13,72 @@ #include "SmbiosMisc.h"
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE0,
- MiscBiosVendor,
- MiscBiosVendor)
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE1,
- MiscSystemManufacturer,
- MiscSystemManufacturer)
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE3,
- MiscChassisManufacturer,
- MiscChassisManufacturer)
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE2,
- MiscBaseBoardManufacturer,
- MiscBaseBoardManufacturer)
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE13,
- MiscNumberOfInstallableLanguages,
- MiscNumberOfInstallableLanguages)
-SMBIOS_MISC_TABLE_EXTERNS (SMBIOS_TABLE_TYPE32,
- MiscBootInformation,
- MiscBootInformation)
-
+SMBIOS_MISC_TABLE_EXTERNS (
+ SMBIOS_TABLE_TYPE0,
+ MiscBiosVendor,
+ MiscBiosVendor
+ )
+SMBIOS_MISC_TABLE_EXTERNS (
+ SMBIOS_TABLE_TYPE1,
+ MiscSystemManufacturer,
+ MiscSystemManufacturer
+ )
+SMBIOS_MISC_TABLE_EXTERNS (
+ SMBIOS_TABLE_TYPE3,
+ MiscChassisManufacturer,
+ MiscChassisManufacturer
+ )
+SMBIOS_MISC_TABLE_EXTERNS (
+ SMBIOS_TABLE_TYPE2,
+ MiscBaseBoardManufacturer,
+ MiscBaseBoardManufacturer
+ )
+SMBIOS_MISC_TABLE_EXTERNS (
+ SMBIOS_TABLE_TYPE13,
+ MiscNumberOfInstallableLanguages,
+ MiscNumberOfInstallableLanguages
+ )
+SMBIOS_MISC_TABLE_EXTERNS (
+ SMBIOS_TABLE_TYPE32,
+ MiscBootInformation,
+ MiscBootInformation
+ )
SMBIOS_MISC_DATA_TABLE mSmbiosMiscDataTable[] = {
// Type0
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBiosVendor,
- MiscBiosVendor),
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (
+ MiscBiosVendor,
+ MiscBiosVendor
+ ),
// Type1
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscSystemManufacturer,
- MiscSystemManufacturer),
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (
+ MiscSystemManufacturer,
+ MiscSystemManufacturer
+ ),
// Type3
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscChassisManufacturer,
- MiscChassisManufacturer),
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (
+ MiscChassisManufacturer,
+ MiscChassisManufacturer
+ ),
// Type2
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBaseBoardManufacturer,
- MiscBaseBoardManufacturer),
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (
+ MiscBaseBoardManufacturer,
+ MiscBaseBoardManufacturer
+ ),
// Type13
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscNumberOfInstallableLanguages,
- MiscNumberOfInstallableLanguages),
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (
+ MiscNumberOfInstallableLanguages,
+ MiscNumberOfInstallableLanguages
+ ),
// Type32
- SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (MiscBootInformation,
- MiscBootInformation),
+ SMBIOS_MISC_TABLE_ENTRY_DATA_AND_FUNCTION (
+ MiscBootInformation,
+ MiscBootInformation
+ ),
};
-
//
// Number of Data Table entries.
//
-UINTN mSmbiosMiscDataTableEntries =
+UINTN mSmbiosMiscDataTableEntries =
(sizeof (mSmbiosMiscDataTable)) / sizeof (SMBIOS_MISC_DATA_TABLE);
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c index eb7f4cb4c1..3a5626b50c 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/SmbiosMiscEntryPoint.c @@ -21,11 +21,10 @@ #include "SmbiosMisc.h"
-
STATIC EFI_HANDLE mSmbiosMiscImageHandle;
STATIC EFI_SMBIOS_PROTOCOL *mSmbiosMiscSmbios = NULL;
-EFI_HII_HANDLE mSmbiosMiscHiiHandle;
+EFI_HII_HANDLE mSmbiosMiscHiiHandle;
/**
Standard EFI driver point. This driver parses the mSmbiosMiscDataTable
@@ -39,28 +38,32 @@ EFI_HII_HANDLE mSmbiosMiscHiiHandle; **/
EFI_STATUS
EFIAPI
-SmbiosMiscEntryPoint(
- IN EFI_HANDLE ImageHandle,
- IN EFI_SYSTEM_TABLE *SystemTable
+SmbiosMiscEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
)
{
- UINTN Index;
- EFI_STATUS EfiStatus;
+ UINTN Index;
+ EFI_STATUS EfiStatus;
mSmbiosMiscImageHandle = ImageHandle;
- EfiStatus = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL,
- (VOID**)&mSmbiosMiscSmbios);
+ EfiStatus = gBS->LocateProtocol (
+ &gEfiSmbiosProtocolGuid,
+ NULL,
+ (VOID **)&mSmbiosMiscSmbios
+ );
if (EFI_ERROR (EfiStatus)) {
DEBUG ((DEBUG_ERROR, "Could not locate SMBIOS protocol. %r\n", EfiStatus));
return EfiStatus;
}
- mSmbiosMiscHiiHandle = HiiAddPackages (&gEfiCallerIdGuid,
- mSmbiosMiscImageHandle,
- SmbiosMiscDxeStrings,
- NULL
- );
+ mSmbiosMiscHiiHandle = HiiAddPackages (
+ &gEfiCallerIdGuid,
+ mSmbiosMiscImageHandle,
+ SmbiosMiscDxeStrings,
+ NULL
+ );
if (mSmbiosMiscHiiHandle == NULL) {
return EFI_OUT_OF_RESOURCES;
}
@@ -70,13 +73,19 @@ SmbiosMiscEntryPoint( // If the entry have a function pointer, just log the data.
//
if (mSmbiosMiscDataTable[Index].Function != NULL) {
- EfiStatus = (*mSmbiosMiscDataTable[Index].Function)(mSmbiosMiscDataTable[Index].RecordData,
- mSmbiosMiscSmbios
- );
-
- if (EFI_ERROR(EfiStatus)) {
- DEBUG ((DEBUG_ERROR, "Misc smbios store error. Index=%d,"
- "ReturnStatus=%r\n", Index, EfiStatus));
+ EfiStatus = (*mSmbiosMiscDataTable[Index].Function)(
+ mSmbiosMiscDataTable[Index].RecordData,
+ mSmbiosMiscSmbios
+ );
+
+ if (EFI_ERROR (EfiStatus)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "Misc smbios store error. Index=%d,"
+ "ReturnStatus=%r\n",
+ Index,
+ EfiStatus
+ ));
return EfiStatus;
}
}
@@ -85,7 +94,6 @@ SmbiosMiscEntryPoint( return EfiStatus;
}
-
/**
Adds an SMBIOS record.
@@ -119,11 +127,11 @@ SmbiosMiscAddRecord ( }
Status = mSmbiosMiscSmbios->Add (
- mSmbiosMiscSmbios,
- NULL,
- &Handle,
- (EFI_SMBIOS_TABLE_HEADER *)Buffer
- );
+ mSmbiosMiscSmbios,
+ NULL,
+ &Handle,
+ (EFI_SMBIOS_TABLE_HEADER *)Buffer
+ );
if (SmbiosHandle != NULL) {
*SmbiosHandle = Handle;
@@ -132,7 +140,6 @@ SmbiosMiscAddRecord ( return Status;
}
-
/** Fetches the number of handles of the specified SMBIOS type.
*
* @param SmbiosType The type of SMBIOS record to look for.
@@ -143,7 +150,7 @@ SmbiosMiscAddRecord ( STATIC
UINTN
GetHandleCount (
- IN UINT8 SmbiosType
+ IN UINT8 SmbiosType
)
{
UINTN HandleCount;
@@ -155,12 +162,13 @@ GetHandleCount ( // Iterate through entries to get the number
do {
- Status = mSmbiosMiscSmbios->GetNext (mSmbiosMiscSmbios,
- &SmbiosHandle,
- &SmbiosType,
- &Record,
- NULL
- );
+ Status = mSmbiosMiscSmbios->GetNext (
+ mSmbiosMiscSmbios,
+ &SmbiosHandle,
+ &SmbiosType,
+ &Record,
+ NULL
+ );
if (Status == EFI_SUCCESS) {
HandleCount++;
@@ -178,10 +186,10 @@ GetHandleCount ( @param[out] *HandleCount Number of handles in the array
**/
VOID
-SmbiosMiscGetLinkTypeHandle(
- IN UINT8 SmbiosType,
- OUT SMBIOS_HANDLE **HandleArray,
- OUT UINTN *HandleCount
+SmbiosMiscGetLinkTypeHandle (
+ IN UINT8 SmbiosType,
+ OUT SMBIOS_HANDLE **HandleArray,
+ OUT UINTN *HandleCount
)
{
UINTN Index;
@@ -206,12 +214,13 @@ SmbiosMiscGetLinkTypeHandle( SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
for (Index = 0; Index < (*HandleCount); Index++) {
- Status = mSmbiosMiscSmbios->GetNext (mSmbiosMiscSmbios,
- &SmbiosHandle,
- &SmbiosType,
- &Record,
- NULL
- );
+ Status = mSmbiosMiscSmbios->GetNext (
+ mSmbiosMiscSmbios,
+ &SmbiosHandle,
+ &SmbiosType,
+ &Record,
+ NULL
+ );
if (!EFI_ERROR (Status)) {
(*HandleArray)[Index] = Record->Handle;
@@ -220,4 +229,3 @@ SmbiosMiscGetLinkTypeHandle( }
}
}
-
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c index edf0186aea..14ded6011a 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorData.c @@ -11,18 +11,16 @@ **/
-
#include "SmbiosMisc.h"
-
//
// Static (possibly build generated) Bios Vendor data.
//
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = {
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE0, MiscBiosVendor) = {
{ // Hdr
- EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type,
- 0, // Length,
- 0 // Handle
+ EFI_SMBIOS_TYPE_BIOS_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
},
1, // Vendor
2, // BiosVersion
@@ -30,38 +28,38 @@ SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = { 3, // BiosReleaseDate
0, // BiosSize
{ // BiosCharacteristics
- 0, // Reserved :2
- 0, // Unknown :1
- 0, // BiosCharacteristicsNotSupported :1
- 0, // IsaIsSupported :1
- 0, // McaIsSupported :1
- 0, // EisaIsSupported :1
- 1, // PciIsSupported :1
- 0, // PcmciaIsSupported :1
- 1, // PlugAndPlayIsSupported :1
- 0, // ApmIsSupported :1
- 1, // BiosIsUpgradable :1
- 1, // BiosShadowingAllowed :1
- 0, // VlVesaIsSupported :1
- 0, // EscdSupportIsAvailable :1
- 1, // BootFromCdIsSupported :1
- 1, // SelectableBootIsSupported :1
- 0, // RomBiosIsSocketed :1
- 0, // BootFromPcmciaIsSupported :1
- 0, // EDDSpecificationIsSupported :1
- 0, // JapaneseNecFloppyIsSupported :1
- 0, // JapaneseToshibaFloppyIsSupported :1
- 0, // Floppy525_360IsSupported :1
- 0, // Floppy525_12IsSupported :1
- 0, // Floppy35_720IsSupported :1
- 0, // Floppy35_288IsSupported :1
- 0, // PrintScreenIsSupported :1
- 0, // Keyboard8042IsSupported :1
- 0, // SerialIsSupported :1
- 0, // PrinterIsSupported :1
- 0, // CgaMonoIsSupported :1
- 0, // NecPc98 :1
- 0 // ReservedForVendor :32
+ 0, // Reserved :2
+ 0, // Unknown :1
+ 0, // BiosCharacteristicsNotSupported :1
+ 0, // IsaIsSupported :1
+ 0, // McaIsSupported :1
+ 0, // EisaIsSupported :1
+ 1, // PciIsSupported :1
+ 0, // PcmciaIsSupported :1
+ 1, // PlugAndPlayIsSupported :1
+ 0, // ApmIsSupported :1
+ 1, // BiosIsUpgradable :1
+ 1, // BiosShadowingAllowed :1
+ 0, // VlVesaIsSupported :1
+ 0, // EscdSupportIsAvailable :1
+ 1, // BootFromCdIsSupported :1
+ 1, // SelectableBootIsSupported :1
+ 0, // RomBiosIsSocketed :1
+ 0, // BootFromPcmciaIsSupported :1
+ 0, // EDDSpecificationIsSupported :1
+ 0, // JapaneseNecFloppyIsSupported :1
+ 0, // JapaneseToshibaFloppyIsSupported :1
+ 0, // Floppy525_360IsSupported :1
+ 0, // Floppy525_12IsSupported :1
+ 0, // Floppy35_720IsSupported :1
+ 0, // Floppy35_288IsSupported :1
+ 0, // PrintScreenIsSupported :1
+ 0, // Keyboard8042IsSupported :1
+ 0, // SerialIsSupported :1
+ 0, // PrinterIsSupported :1
+ 0, // CgaMonoIsSupported :1
+ 0, // NecPc98 :1
+ 0 // ReservedForVendor :32
},
{
@@ -76,7 +74,7 @@ SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = { // 0, // Boot1394IsSupported :1
// 0 // SmartBatteryIsSupported :1
// },
- 0x0C //BIOSCharacteristicsExtensionBytes[1]
+ 0x0C // BIOSCharacteristicsExtensionBytes[1]
// { //SystemReserved
// 0, //BiosBootSpecIsSupported :1
// 0, //FunctionKeyNetworkBootIsSupported :1
@@ -86,8 +84,8 @@ SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE0, MiscBiosVendor) = { // 0 //ExtensionByte2Reserved :3
// },
},
- 0xFF, // SystemBiosMajorRelease;
- 0xFF, // SystemBiosMinorRelease;
+ 0xFF, // SystemBiosMajorRelease;
+ 0xFF, // SystemBiosMinorRelease;
0xFF, // EmbeddedControllerFirmwareMajorRelease;
0xFF // EmbeddedControllerFirmwareMinorRelease;
};
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c index 2506c03d64..b49c4b754c 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type00/MiscBiosVendorFunction.c @@ -18,27 +18,26 @@ #include "SmbiosMisc.h"
-
typedef struct {
- CONST CHAR8* MonthStr;
- UINT32 MonthInt;
+ CONST CHAR8 *MonthStr;
+ UINT32 MonthInt;
} MONTH_DESCRIPTION;
STATIC CONST
-MONTH_DESCRIPTION mMonthDescription[] = {
- { "Jan", 1 },
- { "Feb", 2 },
- { "Mar", 3 },
- { "Apr", 4 },
- { "May", 5 },
- { "Jun", 6 },
- { "Jul", 7 },
- { "Aug", 8 },
- { "Sep", 9 },
+MONTH_DESCRIPTION mMonthDescription[] = {
+ { "Jan", 1 },
+ { "Feb", 2 },
+ { "Mar", 3 },
+ { "Apr", 4 },
+ { "May", 5 },
+ { "Jun", 6 },
+ { "Jul", 7 },
+ { "Aug", 8 },
+ { "Sep", 9 },
{ "Oct", 10 },
{ "Nov", 11 },
{ "Dec", 12 },
- { "???", 1 }, // Use 1 as default month
+ { "???", 1 }, // Use 1 as default month
};
/**
@@ -55,7 +54,7 @@ Base2ToByteWith64KUnit ( IN UINTN Value
)
{
- UINT8 Size;
+ UINT8 Size;
Size = ((Value + (SIZE_64KB - 1)) >> 16);
@@ -69,12 +68,12 @@ Base2ToByteWith64KUnit ( **/
VOID
GetReleaseTime (
- OUT EFI_TIME *Time
+ OUT EFI_TIME *Time
)
{
- CONST CHAR8 *ReleaseDate = __DATE__;
- CONST CHAR8 *ReleaseTime = __TIME__;
- UINTN i;
+ CONST CHAR8 *ReleaseDate = __DATE__;
+ CONST CHAR8 *ReleaseTime = __TIME__;
+ UINTN i;
for (i = 0; i < 12; i++) {
if (AsciiStrnCmp (ReleaseDate, mMonthDescription[i].MonthStr, 3) == 0) {
@@ -82,10 +81,10 @@ GetReleaseTime ( }
}
- Time->Month = mMonthDescription[i].MonthInt;
- Time->Day = AsciiStrDecimalToUintn (ReleaseDate + 4);
- Time->Year = AsciiStrDecimalToUintn (ReleaseDate + 7);
- Time->Hour = AsciiStrDecimalToUintn (ReleaseTime);
+ Time->Month = mMonthDescription[i].MonthInt;
+ Time->Day = AsciiStrDecimalToUintn (ReleaseDate + 4);
+ Time->Year = AsciiStrDecimalToUintn (ReleaseDate + 7);
+ Time->Hour = AsciiStrDecimalToUintn (ReleaseTime);
Time->Minute = AsciiStrDecimalToUintn (ReleaseTime + 3);
Time->Second = AsciiStrDecimalToUintn (ReleaseTime + 6);
}
@@ -101,23 +100,24 @@ GetBiosReleaseDate ( VOID
)
{
- CHAR16 *ReleaseDate;
- EFI_TIME BuildTime;
+ CHAR16 *ReleaseDate;
+ EFI_TIME BuildTime;
ReleaseDate = AllocateZeroPool ((sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH);
if (ReleaseDate == NULL) {
- return NULL;
+ return NULL;
}
GetReleaseTime (&BuildTime);
- (VOID)UnicodeSPrintAsciiFormat (ReleaseDate,
- (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH,
- "%02d/%02d/%4d",
- BuildTime.Month,
- BuildTime.Day,
- BuildTime.Year
- );
+ (VOID)UnicodeSPrintAsciiFormat (
+ ReleaseDate,
+ (sizeof (CHAR16)) * SMBIOS_STRING_MAX_LENGTH,
+ "%02d/%02d/%4d",
+ BuildTime.Month,
+ BuildTime.Day,
+ BuildTime.Year
+ );
return ReleaseDate;
}
@@ -133,14 +133,13 @@ GetBiosVersion ( VOID
)
{
- CHAR16 *ReleaseString;
+ CHAR16 *ReleaseString;
ReleaseString = (CHAR16 *)FixedPcdGetPtr (PcdFirmwareVersionString);
return ReleaseString;
}
-
/**
This function makes boot time changes to the contents of the
MiscBiosVendor (Type 0) record.
@@ -153,23 +152,22 @@ GetBiosVersion ( @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.
**/
-SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor)
-{
- CHAR8 *OptionalStrStart;
- CHAR8 *StrStart;
- UINTN VendorStrLen;
- UINTN VerStrLen;
- UINTN DateStrLen;
- UINTN BiosPhysicalSize;
- CHAR16 *Vendor;
- CHAR16 *Version;
- CHAR16 *ReleaseDate;
- CHAR16 *Char16String;
- EFI_STATUS Status;
- EFI_STRING_ID TokenToUpdate;
- EFI_STRING_ID TokenToGet;
- SMBIOS_TABLE_TYPE0 *SmbiosRecord;
- SMBIOS_TABLE_TYPE0 *InputData;
+SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) {
+ CHAR8 *OptionalStrStart;
+ CHAR8 *StrStart;
+ UINTN VendorStrLen;
+ UINTN VerStrLen;
+ UINTN DateStrLen;
+ UINTN BiosPhysicalSize;
+ CHAR16 *Vendor;
+ CHAR16 *Version;
+ CHAR16 *ReleaseDate;
+ CHAR16 *Char16String;
+ EFI_STATUS Status;
+ EFI_STRING_ID TokenToUpdate;
+ EFI_STRING_ID TokenToGet;
+ SMBIOS_TABLE_TYPE0 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE0 *InputData;
//
// First check for invalid parameters.
@@ -180,20 +178,20 @@ SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) InputData = (SMBIOS_TABLE_TYPE0 *)RecordData;
- Vendor = (CHAR16 *) PcdGetPtr (PcdFirmwareVendor);
+ Vendor = (CHAR16 *)PcdGetPtr (PcdFirmwareVendor);
if (StrLen (Vendor) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Vendor, NULL);
}
- Version = GetBiosVersion();
+ Version = GetBiosVersion ();
if (StrLen (Version) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL);
} else {
- Version = (CHAR16 *) PcdGetPtr (PcdFirmwareVersionString);
+ Version = (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString);
if (StrLen (Version) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_VERSION);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL);
@@ -201,22 +199,22 @@ SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) }
Char16String = GetBiosReleaseDate ();
- if (StrLen(Char16String) > 0) {
+ if (StrLen (Char16String) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Char16String, NULL);
}
- TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
- Vendor = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VENDOR);
+ Vendor = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
VendorStrLen = StrLen (Vendor);
TokenToGet = STRING_TOKEN (STR_MISC_BIOS_VERSION);
- Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
- VerStrLen = StrLen (Version);
+ Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ VerStrLen = StrLen (Version);
- TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
+ TokenToGet = STRING_TOKEN (STR_MISC_BIOS_RELEASE_DATE);
ReleaseDate = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
- DateStrLen = StrLen (ReleaseDate);
+ DateStrLen = StrLen (ReleaseDate);
//
// Now update the BiosPhysicalSize
@@ -226,9 +224,11 @@ SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) //
// Two zeros following the last string.
//
- SmbiosRecord = AllocateZeroPool (sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 +
- VerStrLen + 1 +
- DateStrLen + 1 + 1);
+ SmbiosRecord = AllocateZeroPool (
+ sizeof (SMBIOS_TABLE_TYPE0) + VendorStrLen + 1 +
+ VerStrLen + 1 +
+ DateStrLen + 1 + 1
+ );
if (SmbiosRecord == NULL) {
Status = EFI_OUT_OF_RESOURCES;
goto Exit;
@@ -236,7 +236,7 @@ SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) (VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE0));
- SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE0);
SmbiosRecord->BiosSegment = (UINT16)(FixedPcdGet32 (PcdFdBaseAddress) / SIZE_64KB);
if (BiosPhysicalSize < SIZE_16MB) {
SmbiosRecord->BiosSize = Base2ToByteWith64KUnit (BiosPhysicalSize) - 1;
@@ -251,13 +251,13 @@ SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) }
}
- SmbiosRecord->SystemBiosMajorRelease = (UINT8) (PcdGet16 (PcdSystemBiosRelease) >> 8);
- SmbiosRecord->SystemBiosMinorRelease = (UINT8) (PcdGet16 (PcdSystemBiosRelease) & 0xFF);
+ SmbiosRecord->SystemBiosMajorRelease = (UINT8)(PcdGet16 (PcdSystemBiosRelease) >> 8);
+ SmbiosRecord->SystemBiosMinorRelease = (UINT8)(PcdGet16 (PcdSystemBiosRelease) & 0xFF);
SmbiosRecord->EmbeddedControllerFirmwareMajorRelease = (UINT16)
- (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) >> 8);
+ (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) >> 8);
SmbiosRecord->EmbeddedControllerFirmwareMinorRelease = (UINT16)
- (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) & 0xFF);
+ (PcdGet16 (PcdEmbeddedControllerFirmwareRelease) & 0xFF);
OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
UnicodeStrToAsciiStrS (Vendor, OptionalStrStart, VendorStrLen + 1);
@@ -268,10 +268,15 @@ SMBIOS_MISC_TABLE_FUNCTION (MiscBiosVendor) //
// Now we have got the full smbios record, call smbios protocol to add this record.
//
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a]:[%dL] Smbios Type00 Table Log Failed! %r \n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Status
+ ));
}
FreePool (SmbiosRecord);
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c index c03b133690..00f448a57d 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerData.c @@ -13,22 +13,21 @@ #include "SmbiosMisc.h"
-
//
// Static (possibly build generated) System Manufacturer data.
//
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) = {
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE1, MiscSystemManufacturer) = {
{ // Hdr
- EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,
- 0, // Length,
- 0 // Handle
+ EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
},
1, // Manufacturer
2, // ProductName
3, // Version
4, // SerialNumber
{ // Uuid
- 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ 0x00000000, 0x0000, 0x0000, { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
SystemWakeupTypePowerSwitch, // SystemWakeupType
5, // SKUNumber,
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c index 555557a2a9..6d08a75580 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c @@ -35,30 +35,29 @@ @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.
**/
-SMBIOS_MISC_TABLE_FUNCTION(MiscSystemManufacturer)
-{
- CHAR8 *OptionalStrStart;
- CHAR8 *StrStart;
- UINTN ManuStrLen;
- UINTN VerStrLen;
- UINTN PdNameStrLen;
- UINTN SerialNumStrLen;
- UINTN SKUNumStrLen;
- UINTN FamilyStrLen;
- UINTN RecordLength;
- EFI_STRING Manufacturer;
- EFI_STRING ProductName;
- EFI_STRING Version;
- EFI_STRING SerialNumber;
- EFI_STRING SKUNumber;
- EFI_STRING Family;
- EFI_STRING_ID TokenToGet;
- SMBIOS_TABLE_TYPE1 *SmbiosRecord;
- SMBIOS_TABLE_TYPE1 *InputData;
- EFI_STATUS Status;
- EFI_STRING_ID TokenToUpdate;
- CHAR16 *Product;
- CHAR16 *pVersion;
+SMBIOS_MISC_TABLE_FUNCTION (MiscSystemManufacturer) {
+ CHAR8 *OptionalStrStart;
+ CHAR8 *StrStart;
+ UINTN ManuStrLen;
+ UINTN VerStrLen;
+ UINTN PdNameStrLen;
+ UINTN SerialNumStrLen;
+ UINTN SKUNumStrLen;
+ UINTN FamilyStrLen;
+ UINTN RecordLength;
+ EFI_STRING Manufacturer;
+ EFI_STRING ProductName;
+ EFI_STRING Version;
+ EFI_STRING SerialNumber;
+ EFI_STRING SKUNumber;
+ EFI_STRING Family;
+ EFI_STRING_ID TokenToGet;
+ SMBIOS_TABLE_TYPE1 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE1 *InputData;
+ EFI_STATUS Status;
+ EFI_STRING_ID TokenToUpdate;
+ CHAR16 *Product;
+ CHAR16 *pVersion;
Status = EFI_SUCCESS;
@@ -71,30 +70,38 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscSystemManufacturer) InputData = (SMBIOS_TABLE_TYPE1 *)RecordData;
- Product = (CHAR16 *) PcdGetPtr (PcdSystemProductName);
+ Product = (CHAR16 *)PcdGetPtr (PcdSystemProductName);
if (StrLen (Product) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Product, NULL);
}
- pVersion = (CHAR16 *) PcdGetPtr (PcdSystemVersion);
+ pVersion = (CHAR16 *)PcdGetPtr (PcdSystemVersion);
if (StrLen (pVersion) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, pVersion, NULL);
}
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
- STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER),
- SerialNumType01);
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
- STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER),
- SystemManufacturerType01);
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
- STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER),
- SkuNumberType01);
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
- STRING_TOKEN (STR_MISC_SYSTEM_FAMILY),
- FamilyType01);
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
+ STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER),
+ SerialNumType01
+ );
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
+ STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER),
+ SystemManufacturerType01
+ );
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
+ STRING_TOKEN (STR_MISC_SYSTEM_SKU_NUMBER),
+ SkuNumberType01
+ );
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
+ STRING_TOKEN (STR_MISC_SYSTEM_FAMILY),
+ FamilyType01
+ );
TokenToGet = STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER);
Manufacturer = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
@@ -141,12 +148,12 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscSystemManufacturer) SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE1);
- CopyGuid(&SmbiosRecord->Uuid, &InputData->Uuid);
+ CopyGuid (&SmbiosRecord->Uuid, &InputData->Uuid);
OptionalStrStart = (CHAR8 *)(SmbiosRecord + 1);
UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1);
StrStart = OptionalStrStart + ManuStrLen + 1;
- UnicodeStrToAsciiStrS (ProductName, StrStart, PdNameStrLen + 1);
+ UnicodeStrToAsciiStrS (ProductName, StrStart, PdNameStrLen + 1);
StrStart += PdNameStrLen + 1;
UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1);
StrStart += VerStrLen + 1;
@@ -159,10 +166,15 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscSystemManufacturer) //
// Now we have got the full smbios record, call smbios protocol to add this record.
//
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a]:[%dL] Smbios Type01 Table Log Failed! %r \n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Status
+ ));
}
FreePool (SmbiosRecord);
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c index dfe1f2d45b..2c3f181e8b 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerData.c @@ -17,7 +17,7 @@ //
// Static (possibly build generated) Chassis Manufacturer data.
//
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) = {
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE2, MiscBaseBoardManufacturer) = {
{ // Hdr
EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, // Type,
0, // Length,
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c index f11295b199..99ba99e913 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type02/MiscBaseBoardManufacturerFunction.c @@ -23,7 +23,6 @@ #include "SmbiosMisc.h"
-
/**
This function makes boot time changes to the contents of the
MiscBaseBoardManufacturer (Type 2) record.
@@ -36,35 +35,34 @@ @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.
**/
-SMBIOS_MISC_TABLE_FUNCTION(MiscBaseBoardManufacturer)
-{
- CHAR8 *OptionalStrStart;
- CHAR8 *StrStart;
- UINTN RecordLength;
- UINTN ManuStrLen;
- UINTN ProductNameStrLen;
- UINTN VerStrLen;
- UINTN SerialNumStrLen;
- UINTN AssetTagStrLen;
- UINTN ChassisLocaStrLen;
- UINTN HandleCount;
- UINT16 *HandleArray;
- CHAR16 *BaseBoardManufacturer;
- CHAR16 *BaseBoardProductName;
- CHAR16 *Version;
- EFI_STRING SerialNumber;
- EFI_STRING AssetTag;
- EFI_STRING ChassisLocation;
- EFI_STRING_ID TokenToGet;
- SMBIOS_TABLE_TYPE2 *SmbiosRecord;
- SMBIOS_TABLE_TYPE2 *InputData;
- EFI_STATUS Status;
-
- EFI_STRING_ID TokenToUpdate;
+SMBIOS_MISC_TABLE_FUNCTION (MiscBaseBoardManufacturer) {
+ CHAR8 *OptionalStrStart;
+ CHAR8 *StrStart;
+ UINTN RecordLength;
+ UINTN ManuStrLen;
+ UINTN ProductNameStrLen;
+ UINTN VerStrLen;
+ UINTN SerialNumStrLen;
+ UINTN AssetTagStrLen;
+ UINTN ChassisLocaStrLen;
+ UINTN HandleCount;
+ UINT16 *HandleArray;
+ CHAR16 *BaseBoardManufacturer;
+ CHAR16 *BaseBoardProductName;
+ CHAR16 *Version;
+ EFI_STRING SerialNumber;
+ EFI_STRING AssetTag;
+ EFI_STRING ChassisLocation;
+ EFI_STRING_ID TokenToGet;
+ SMBIOS_TABLE_TYPE2 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE2 *InputData;
+ EFI_STATUS Status;
+
+ EFI_STRING_ID TokenToUpdate;
HandleCount = 0;
HandleArray = NULL;
- InputData = NULL;
+ InputData = NULL;
//
// First check for invalid parameters.
@@ -73,73 +71,79 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscBaseBoardManufacturer) return EFI_INVALID_PARAMETER;
}
- InputData = (SMBIOS_TABLE_TYPE2*)RecordData;
+ InputData = (SMBIOS_TABLE_TYPE2 *)RecordData;
- BaseBoardManufacturer = (CHAR16 *) PcdGetPtr (PcdBaseBoardManufacturer);
+ BaseBoardManufacturer = (CHAR16 *)PcdGetPtr (PcdBaseBoardManufacturer);
if (StrLen (BaseBoardManufacturer) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, BaseBoardManufacturer, NULL);
}
- BaseBoardProductName = (CHAR16 *) PcdGetPtr (PcdBaseBoardProductName);
+ BaseBoardProductName = (CHAR16 *)PcdGetPtr (PcdBaseBoardProductName);
if (StrLen (BaseBoardProductName) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, BaseBoardProductName, NULL);
}
- Version = (CHAR16 *) PcdGetPtr (PcdBaseBoardVersion);
+ Version = (CHAR16 *)PcdGetPtr (PcdBaseBoardVersion);
if (StrLen (Version) > 0) {
TokenToUpdate = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);
HiiSetString (mSmbiosMiscHiiHandle, TokenToUpdate, Version, NULL);
}
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG),
AssertTagType02
);
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER),
SerialNumberType02
);
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER),
BoardManufacturerType02
);
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER),
SerialNumberType02
);
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_BASE_BOARD_SKU_NUMBER),
SerialNumberType02
);
- OemUpdateSmbiosInfo (mSmbiosMiscHiiHandle,
+ OemUpdateSmbiosInfo (
+ mSmbiosMiscHiiHandle,
STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION),
ChassisLocationType02
);
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_MANUFACTURER);
BaseBoardManufacturer = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
- ManuStrLen = StrLen (BaseBoardManufacturer);
+ ManuStrLen = StrLen (BaseBoardManufacturer);
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_PRODUCT_NAME);
BaseBoardProductName = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
- ProductNameStrLen = StrLen (BaseBoardProductName);
+ ProductNameStrLen = StrLen (BaseBoardProductName);
TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_VERSION);
- Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
- VerStrLen = StrLen (Version);
+ Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ VerStrLen = StrLen (Version);
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER);
- SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_SERIAL_NUMBER);
+ SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
SerialNumStrLen = StrLen (SerialNumber);
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);
- AssetTag = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_ASSET_TAG);
+ AssetTag = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
AssetTagStrLen = StrLen (AssetTag);
- TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);
- ChassisLocation = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ TokenToGet = STRING_TOKEN (STR_MISC_BASE_BOARD_CHASSIS_LOCATION);
+ ChassisLocation = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
ChassisLocaStrLen = StrLen (ChassisLocation);
//
@@ -159,14 +163,17 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscBaseBoardManufacturer) }
(VOID)CopyMem (SmbiosRecord, InputData, sizeof (SMBIOS_TABLE_TYPE2));
- SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2);
+ SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE2);
//
// Update Contained objects Handle
//
SmbiosRecord->NumberOfContainedObjectHandles = 0;
- SmbiosMiscGetLinkTypeHandle (EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, &HandleArray,
- &HandleCount);
+ SmbiosMiscGetLinkTypeHandle (
+ EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE,
+ &HandleArray,
+ &HandleCount
+ );
// It's assumed there's at most a single chassis
ASSERT (HandleCount < 2);
if (HandleCount > 0) {
@@ -195,8 +202,13 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscBaseBoardManufacturer) Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a]:[%dL] Smbios Type02 Table Log Failed! %r \n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Status
+ ));
}
FreePool (SmbiosRecord);
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c index 29449b8719..67cb5fede0 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c @@ -13,11 +13,10 @@ #include "SmbiosMisc.h"
-
//
// Static (possibly build generated) Chassis Manufacturer data.
//
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {
{ // Hdr
EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, // Type,
0, // Length,
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c index d64046182b..d161970c02 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c @@ -35,30 +35,29 @@ @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.
**/
-SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
-{
- CHAR8 *OptionalStrStart;
- CHAR8 *StrStart;
- UINT8 *SkuNumberField;
- UINTN RecordLength;
- UINTN ManuStrLen;
- UINTN VerStrLen;
- UINTN AssertTagStrLen;
- UINTN SerialNumStrLen;
- UINTN ChaNumStrLen;
- EFI_STRING Manufacturer;
- EFI_STRING Version;
- EFI_STRING SerialNumber;
- EFI_STRING AssertTag;
- EFI_STRING ChassisSkuNumber;
- EFI_STRING_ID TokenToGet;
- SMBIOS_TABLE_TYPE3 *SmbiosRecord;
- SMBIOS_TABLE_TYPE3 *InputData;
- EFI_STATUS Status;
-
- UINT8 ContainedElementCount;
- CONTAINED_ELEMENT ContainedElements;
- UINT8 ExtendLength;
+SMBIOS_MISC_TABLE_FUNCTION (MiscChassisManufacturer) {
+ CHAR8 *OptionalStrStart;
+ CHAR8 *StrStart;
+ UINT8 *SkuNumberField;
+ UINTN RecordLength;
+ UINTN ManuStrLen;
+ UINTN VerStrLen;
+ UINTN AssertTagStrLen;
+ UINTN SerialNumStrLen;
+ UINTN ChaNumStrLen;
+ EFI_STRING Manufacturer;
+ EFI_STRING Version;
+ EFI_STRING SerialNumber;
+ EFI_STRING AssertTag;
+ EFI_STRING ChassisSkuNumber;
+ EFI_STRING_ID TokenToGet;
+ SMBIOS_TABLE_TYPE3 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE3 *InputData;
+ EFI_STATUS Status;
+
+ UINT8 ContainedElementCount;
+ CONTAINED_ELEMENT ContainedElements;
+ UINT8 ExtendLength;
ExtendLength = 0;
@@ -97,28 +96,28 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer) SkuNumberType03
);
- TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_MANUFACTURER);
Manufacturer = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
- ManuStrLen = StrLen (Manufacturer);
+ ManuStrLen = StrLen (Manufacturer);
TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_VERSION);
- Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
- VerStrLen = StrLen (Version);
+ Version = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ VerStrLen = StrLen (Version);
- TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);
- SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SERIAL_NUMBER);
+ SerialNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
SerialNumStrLen = StrLen (SerialNumber);
- TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);
- AssertTag = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_ASSET_TAG);
+ AssertTag = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
AssertTagStrLen = StrLen (AssertTag);
- TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER);
+ TokenToGet = STRING_TOKEN (STR_MISC_CHASSIS_SKU_NUMBER);
ChassisSkuNumber = HiiGetPackageString (&gEfiCallerIdGuid, TokenToGet, NULL);
- ChaNumStrLen = StrLen (ChassisSkuNumber);
+ ChaNumStrLen = StrLen (ChassisSkuNumber);
ContainedElementCount = InputData->ContainedElementCount;
- ExtendLength = ContainedElementCount * sizeof (CONTAINED_ELEMENT);
+ ExtendLength = ContainedElementCount * sizeof (CONTAINED_ELEMENT);
//
// Two zeros following the last string.
@@ -142,11 +141,11 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer) SmbiosRecord->Type = OemGetChassisType ();
- //ContainedElements
+ // ContainedElements
ASSERT (ContainedElementCount < 2);
(VOID)CopyMem (SmbiosRecord + 1, &ContainedElements, ExtendLength);
- //ChassisSkuNumber
+ // ChassisSkuNumber
SkuNumberField = (UINT8 *)SmbiosRecord +
sizeof (SMBIOS_TABLE_TYPE3) -
sizeof (CONTAINED_ELEMENT) + ExtendLength;
@@ -154,7 +153,7 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer) *SkuNumberField = 5;
OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) +
- ExtendLength + 1);
+ ExtendLength + 1);
UnicodeStrToAsciiStrS (Manufacturer, OptionalStrStart, ManuStrLen + 1);
StrStart = OptionalStrStart + ManuStrLen + 1;
UnicodeStrToAsciiStrS (Version, StrStart, VerStrLen + 1);
@@ -165,20 +164,25 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer) StrStart += AssertTagStrLen + 1;
UnicodeStrToAsciiStrS (ChassisSkuNumber, StrStart, ChaNumStrLen + 1);
- SmbiosRecord->BootupState = OemGetChassisBootupState ();
- SmbiosRecord->PowerSupplyState = OemGetChassisPowerSupplyState ();
- SmbiosRecord->ThermalState = OemGetChassisThermalState ();
- SmbiosRecord->SecurityStatus = OemGetChassisSecurityStatus ();
- SmbiosRecord->Height = OemGetChassisHeight ();
+ SmbiosRecord->BootupState = OemGetChassisBootupState ();
+ SmbiosRecord->PowerSupplyState = OemGetChassisPowerSupplyState ();
+ SmbiosRecord->ThermalState = OemGetChassisThermalState ();
+ SmbiosRecord->SecurityStatus = OemGetChassisSecurityStatus ();
+ SmbiosRecord->Height = OemGetChassisHeight ();
SmbiosRecord->NumberofPowerCords = OemGetChassisNumPowerCords ();
//
// Now we have got the full smbios record, call smbios protocol to add this record.
//
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a]:[%dL] Smbios Type03 Table Log Failed! %r \n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Status
+ ));
}
FreePool (SmbiosRecord);
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c index 97d7303d1a..014dec52c6 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesData.c @@ -17,12 +17,12 @@ // Static (possibly build generated) Bios Vendor data.
//
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages) =
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE13, MiscNumberOfInstallableLanguages) =
{
{ // Hdr
- EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // Type,
- 0, // Length,
- 0 // Handle
+ EFI_SMBIOS_TYPE_BIOS_LANGUAGE_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
},
0, // InstallableLanguages
0, // Flags
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c index 017b410a16..386b8800e2 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type13/MiscNumberOfInstallableLanguagesFunction.c @@ -32,14 +32,14 @@ VOID
EFIAPI
GetNextLanguage (
- IN OUT CHAR8 **LangCode,
- OUT CHAR8 *Lang
+ IN OUT CHAR8 **LangCode,
+ OUT CHAR8 *Lang
)
{
UINTN Index;
CHAR8 *StringPtr;
- if (LangCode == NULL || *LangCode == NULL || Lang == NULL) {
+ if ((LangCode == NULL) || (*LangCode == NULL) || (Lang == NULL)) {
return;
}
@@ -55,6 +55,7 @@ GetNextLanguage ( if (StringPtr[Index] == ';') {
Index++;
}
+
*LangCode = StringPtr + Index;
}
@@ -69,7 +70,7 @@ GetNextLanguage ( UINT16
EFIAPI
GetSupportedLanguageNumber (
- IN EFI_HII_HANDLE HiiHandle
+ IN EFI_HII_HANDLE HiiHandle
)
{
CHAR8 *Lang;
@@ -83,20 +84,21 @@ GetSupportedLanguageNumber ( }
LangNumber = 0;
- Lang = AllocatePool (AsciiStrSize (Languages));
+ Lang = AllocatePool (AsciiStrSize (Languages));
if (Lang != NULL) {
LanguageString = Languages;
while (*LanguageString != 0) {
GetNextLanguage (&LanguageString, Lang);
LangNumber++;
}
+
FreePool (Lang);
}
+
FreePool (Languages);
return LangNumber;
}
-
/**
This function makes boot time changes to the contents of the
MiscNumberOfInstallableLanguages (Type 13) record.
@@ -109,14 +111,13 @@ GetSupportedLanguageNumber ( @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.
**/
-SMBIOS_MISC_TABLE_FUNCTION(MiscNumberOfInstallableLanguages)
-{
- UINTN LangStrLen;
- CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];
- CHAR8 *OptionalStrStart;
- EFI_STATUS Status;
- SMBIOS_TABLE_TYPE13 *SmbiosRecord;
- SMBIOS_TABLE_TYPE13 *InputData;
+SMBIOS_MISC_TABLE_FUNCTION (MiscNumberOfInstallableLanguages) {
+ UINTN LangStrLen;
+ CHAR8 CurrentLang[SMBIOS_STRING_MAX_LENGTH + 1];
+ CHAR8 *OptionalStrStart;
+ EFI_STATUS Status;
+ SMBIOS_TABLE_TYPE13 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE13 *InputData;
InputData = NULL;
@@ -155,10 +156,15 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscNumberOfInstallableLanguages) //
// Now we have got the full smbios record, call smbios protocol to add this record.
//
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a]:[%dL] Smbios Type13 Table Log Failed! %r \n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Status
+ ));
}
FreePool (SmbiosRecord);
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c index ebe4ad941c..5e1a6e4f2e 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationData.c @@ -14,11 +14,11 @@ //
// Static (possibly build generated) Bios Vendor data.
//
-SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE32, MiscBootInformation) = {
+SMBIOS_MISC_TABLE_DATA (SMBIOS_TABLE_TYPE32, MiscBootInformation) = {
{ // Hdr
- EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,
- 0, // Length,
- 0 // Handle
+ EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, // Type,
+ 0, // Length,
+ 0 // Handle
},
{ // Reserved[6]
0,
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c index c4ce6a5e76..fdf6262aa7 100644 --- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c +++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c @@ -33,11 +33,10 @@ @retval EFI_OUT_OF_RESOURCES Failed to allocate required memory.
**/
-SMBIOS_MISC_TABLE_FUNCTION(MiscBootInformation)
-{
- EFI_STATUS Status;
- SMBIOS_TABLE_TYPE32 *SmbiosRecord;
- SMBIOS_TABLE_TYPE32 *InputData;
+SMBIOS_MISC_TABLE_FUNCTION (MiscBootInformation) {
+ EFI_STATUS Status;
+ SMBIOS_TABLE_TYPE32 *SmbiosRecord;
+ SMBIOS_TABLE_TYPE32 *InputData;
//
// First check for invalid parameters.
@@ -65,10 +64,15 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscBootInformation) //
// Now we have got the full smbios record, call smbios protocol to add this record.
//
- Status = SmbiosMiscAddRecord ((UINT8*)SmbiosRecord, NULL);
+ Status = SmbiosMiscAddRecord ((UINT8 *)SmbiosRecord, NULL);
if (EFI_ERROR (Status)) {
- DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n",
- __FUNCTION__, DEBUG_LINE_NUMBER, Status));
+ DEBUG ((
+ DEBUG_ERROR,
+ "[%a]:[%dL] Smbios Type32 Table Log Failed! %r \n",
+ __FUNCTION__,
+ DEBUG_LINE_NUMBER,
+ Status
+ ));
}
FreePool (SmbiosRecord);
|