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| author | Antoine Cœur <coeur@gmx.fr> | 2019-07-11 16:54:31 +0800 |
|---|---|---|
| committer | Chasel Chiu <chasel.chiu@intel.com> | 2019-07-11 21:07:17 +0800 |
| commit | 91cc60bafc7d6e49b7bc85990f895d6228f51364 (patch) | |
| tree | 4325571c8c0614bfe98e68ef86e526489aed05ae /IntelFsp2Pkg/FspSecCore/Ia32 | |
| parent | efa12a3f029bd6ff4d2ada406c285f001b252907 (diff) | |
| download | edk2-91cc60bafc7d6e49b7bc85990f895d6228f51364.tar.gz edk2-91cc60bafc7d6e49b7bc85990f895d6228f51364.tar.bz2 edk2-91cc60bafc7d6e49b7bc85990f895d6228f51364.zip | |
IntelFsp2Pkg: Fix various typos
Fix various typos in IntelFsp2Pkg.
Signed-off-by: Cœur <coeur@gmx.fr>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore/Ia32')
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 4 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm | 4 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 4 | ||||
| -rw-r--r-- | IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm index f14c18c7b9..e7261b41cd 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -194,9 +194,9 @@ StackSetupDone: ;
; Pass BFV into the PEI Core
- ; It uses relative address to calucate the actual boot FV base
+ ; It uses relative address to calculate the actual boot FV base
; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
- ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
+ ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,
; they are different. The code below can handle both cases.
;
call ASM_PFX(AsmGetFspBaseAddress)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm index e1886ea11b..ebc91c41e4 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits): fldcw [ASM_PFX(mFpuControlWord)]
;
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index b257deb76c..4c321cbece 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -150,7 +150,7 @@ NextAddress: fldcw [FpuControlWord]
;
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm index d72212ed45..5a7e27c240 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm @@ -1,6 +1,6 @@ ;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack): mov esp, eax ; From now, esp is pointed to permanent memory
;
- ; Fixup the ebp point to permenent memory
+ ; Fixup the ebp point to permanent memory
;
mov eax, ebp
sub eax, ebx
|