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authorAntoine Cœur <coeur@gmx.fr>2019-07-11 16:54:31 +0800
committerChasel Chiu <chasel.chiu@intel.com>2019-07-11 21:07:17 +0800
commit91cc60bafc7d6e49b7bc85990f895d6228f51364 (patch)
tree4325571c8c0614bfe98e68ef86e526489aed05ae /IntelFsp2Pkg/FspSecCore
parentefa12a3f029bd6ff4d2ada406c285f001b252907 (diff)
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IntelFsp2Pkg: Fix various typos
Fix various typos in IntelFsp2Pkg. Signed-off-by: Cœur <coeur@gmx.fr> Reviewed-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Diffstat (limited to 'IntelFsp2Pkg/FspSecCore')
-rw-r--r--IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm4
-rw-r--r--IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm4
-rw-r--r--IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc4
-rw-r--r--IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm4
-rw-r--r--IntelFsp2Pkg/FspSecCore/SecFsp.c4
-rw-r--r--IntelFsp2Pkg/FspSecCore/SecMain.c2
-rw-r--r--IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm164
7 files changed, 13 insertions, 13 deletions
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
index f14c18c7b9..e7261b41cd 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm
@@ -194,9 +194,9 @@ StackSetupDone:
;
; Pass BFV into the PEI Core
- ; It uses relative address to calucate the actual boot FV base
+ ; It uses relative address to calculate the actual boot FV base
; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase and
- ; PcdFspAreaBaseAddress are the same. For FSP with mulitple FVs,
+ ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,
; they are different. The code below can handle both cases.
;
call ASM_PFX(AsmGetFspBaseAddress)
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
index e1886ea11b..ebc91c41e4 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/InitializeFpu.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -46,7 +46,7 @@ ASM_PFX(InitializeFloatingPointUnits):
fldcw [ASM_PFX(mFpuControlWord)]
;
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
index b257deb76c..4c321cbece 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -150,7 +150,7 @@ NextAddress:
fldcw [FpuControlWord]
;
- ; Use CpuId instructuion (CPUID.01H:EDX.SSE[bit 25] = 1) to test
+ ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test
; whether the processor supports SSE instruction.
;
mov eax, 1
diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
index d72212ed45..5a7e27c240 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/Stack.nasm
@@ -1,6 +1,6 @@
;------------------------------------------------------------------------------
;
-; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
; Abstract:
@@ -58,7 +58,7 @@ ASM_PFX(SecSwitchStack):
mov esp, eax ; From now, esp is pointed to permanent memory
;
- ; Fixup the ebp point to permenent memory
+ ; Fixup the ebp point to permanent memory
;
mov eax, ebp
sub eax, ebx
diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/SecFsp.c
index 6497c88ebe..446d1730e9 100644
--- a/IntelFsp2Pkg/FspSecCore/SecFsp.c
+++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -169,7 +169,7 @@ FspGlobalDataInit (
SerialPortInitialize ();
//
- // Ensure the golbal data pointer is valid
+ // Ensure the global data pointer is valid
//
ASSERT (GetFspGlobalDataPointer () == PeiFspData);
diff --git a/IntelFsp2Pkg/FspSecCore/SecMain.c b/IntelFsp2Pkg/FspSecCore/SecMain.c
index cd3ab46ce2..a63d1336e4 100644
--- a/IntelFsp2Pkg/FspSecCore/SecMain.c
+++ b/IntelFsp2Pkg/FspSecCore/SecMain.c
@@ -110,7 +110,7 @@ SecStartup (
// |-------------------|---->
// | |
// | |
- // | Heap | PeiTemporayRamSize
+ // | Heap | PeiTemporaryRamSize
// | |
// | |
// |-------------------|----> TempRamBase
diff --git a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
index f25de0206a..c519874809 100644
--- a/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
+++ b/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
@@ -2,7 +2,7 @@
; Reset Vector Data structure
; This structure is located at 0xFFFFFFC0
;
-; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent
;
;;
@@ -61,7 +61,7 @@ ApStartup:
;
; Jmp Rel16 instruction
; Use machine code directly in case of the assembler optimization
- ; SEC entry point relatvie address will be fixed up by some build tool.
+ ; SEC entry point relative address will be fixed up by some build tool.
;
; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
; SecEntry.asm