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authorGerd Hoffmann <kraxel@redhat.com>2024-02-22 11:54:05 +0100
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>2024-02-29 09:56:38 +0000
commit73ac735be8f8d3f8e6e7ab02c34ad360b045452f (patch)
treee75888bfd753ab690c504bf658e888bf60b0e3b3 /MdeModulePkg
parentd9a6e7b0b8a67392a57788d97634256546207a64 (diff)
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MdeModulePkg/DxeIplPeim: fix PcdUse5LevelPageTable assert
PcdUse5LevelPageTable documentation says: Indicates if 5-Level Paging will be enabled in long mode. 5-Level Paging will not be enabled when the PCD is TRUE but CPU doesn't support 5-Level Paging. So running in 4-level paging mode with PcdUse5LevelPageTable=TRUE is possible. The only invalid combination is 5-level paging being active with PcdUse5LevelPageTable=FALSE. Fix the ASSERT accordingly. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Acked-by: Ard Biesheuvel <ardb@kernel.org> Message-Id: <20240222105407.75735-2-kraxel@redhat.com> Cc: Michael Roth <michael.roth@amd.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Liming Gao <gaoliming@byosoft.com.cn> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Tom Lendacky <thomas.lendacky@amd.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Min Xu <min.m.xu@intel.com> Cc: Erdem Aktas <erdemaktas@google.com> Cc: Oliver Steffen <osteffen@redhat.com> Cc: Ard Biesheuvel <ardb@kernel.org> [lersek@redhat.com: turn the "Cc:" message headers from Gerd's on-list posting into "Cc:" tags in the commit message, in order to pacify "PatchCheck.py"]
Diffstat (limited to 'MdeModulePkg')
-rw-r--r--MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
index 980c2002d4..1d240e9596 100644
--- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
+++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
@@ -745,7 +745,9 @@ CreateIdentityMappingPageTables (
//
Cr4.UintN = AsmReadCr4 ();
Page5LevelSupport = (Cr4.Bits.LA57 != 0);
- ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport);
+ if (Page5LevelSupport) {
+ ASSERT (PcdGetBool (PcdUse5LevelPageTable));
+ }
} else {
//
// If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability.