Removed duplicate PalCallStatic functions in different libraries. Moved ReadItc and InvalidateInstructionCacheRange to the BaseLib so other libs don't need .s files.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1809 6f19259b-4bc3-4df7-8a09-765794883524

2 files changed, 42 insertions, 24 deletions

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
index 02ea370151..16d5b20998 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.msa
@@ -1,19 +1,19 @@
 <?xml version="1.0" encoding="UTF-8"?>

-<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0">

+<ModuleSurfaceArea xmlns="http://www.TianoCore.org/2006/Edk2.0" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">

   <MsaHeader>

     <ModuleName>BaseCacheMaintenanceLib</ModuleName>

     <ModuleType>BASE</ModuleType>

     <GuidValue>123dd843-57c9-4158-8418-ce68b3944ce7</GuidValue>

     <Version>1.0</Version>

     <Abstract>Component description file for Base Cache Maintenance Library</Abstract>

-    <Description>Cache Maintenance Library that uses Base Library services to maintain caches.

+    <Description>Cache Maintenance Library that uses Base Library services to maintain caches.
     This library assumes there are no chipset dependencies required to maintain caches.</Description>

     <Copyright>Copyright (c) 2006, Intel Corporation</Copyright>

-    <License>All rights reserved. This program and the accompanying materials

-      are licensed and made available under the terms and conditions of the BSD License

-      which accompanies this distribution.  The full text of the license may be found at

-      http://opensource.org/licenses/bsd-license.php

-      THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

+    <License>All rights reserved. This program and the accompanying materials
+      are licensed and made available under the terms and conditions of the BSD License
+      which accompanies this distribution.  The full text of the license may be found at
+      http://opensource.org/licenses/bsd-license.php
+      THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
       WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>

     <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION   0x00000052</Specification>

   </MsaHeader>

@@ -38,8 +38,6 @@
     <Filename SupArchList="X64">x86Cache.c</Filename>

     <Filename SupArchList="EBC">EbcCache.c</Filename>

     <Filename SupArchList="IPF">IpfCache.c</Filename>

-    <Filename SupArchList="IPF">Ipf/Cpu.s</Filename>

-    <Filename SupArchList="IPF">Ipf/PalCallStatic.s</Filename>

   </SourceFiles>

   <PackageDependencies>

     <Package PackageGuid="5e0e9358-46b6-4ae2-8218-4ab8b9bbdcec"/>

diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
index 7e96d9b76a..0c6f0e4dc8 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/IpfCache.c
@@ -12,21 +12,6 @@
 

 **/

 

-typedef struct {

-  UINT64                            Status;

-  UINT64                            r9;

-  UINT64                            r10;

-  UINT64                            r11;

-} PAL_PROC_RETURN;

-

-PAL_PROC_RETURN

-PalCallStatic (

-  IN      CONST VOID                *PalEntryPoint,

-  IN      UINT64                    Arg1,

-  IN      UINT64                    Arg2,

-  IN      UINT64                    Arg3,

-  IN      UINT64                    Arg4

-  );

 

 /**

   Invalidates the entire instruction cache in cache coherency domain of the

@@ -46,6 +31,41 @@ InvalidateInstructionCache (
 }

 

 /**

+  Invalidates a range of instruction cache lines in the cache coherency domain

+  of the calling CPU.

+

+  Invalidates the instruction cache lines specified by Address and Length. If

+  Address is not aligned on a cache line boundary, then entire instruction

+  cache line containing Address is invalidated. If Address + Length is not

+  aligned on a cache line boundary, then the entire instruction cache line

+  containing Address + Length -1 is invalidated. This function may choose to

+  invalidate the entire instruction cache if that is more efficient than

+  invalidating the specified range. If Length is 0, the no instruction cache

+  lines are invalidated. Address is returned.

+

+  If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().

+

+  @param  Address The base address of the instruction cache lines to

+                  invalidate. If the CPU is in a physical addressing mode, then

+                  Address is a physical address. If the CPU is in a virtual

+                  addressing mode, then Address is a virtual address.

+

+  @param  Length  The number of bytes to invalidate from the instruction cache.

+

+  @return Address

+

+**/

+VOID *

+EFIAPI

+InvalidateInstructionCacheRange (

+  IN      VOID                      *Address,

+  IN      UINTN                     Length

+  )

+{

+  return IpfInvalidateInstructionCacheRange (Address, Length);

+}

+

+/**

   Writes Back and Invalidates the entire data cache in cache coherency domain

   of the calling CPU.