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| author | Laszlo Ersek <lersek@redhat.com> | 2019-05-29 11:51:26 +0200 |
|---|---|---|
| committer | Laszlo Ersek <lersek@redhat.com> | 2019-06-03 19:54:01 +0200 |
| commit | eb4d62b0779c3a5766174e4373c95a8b6a967cb7 (patch) | |
| tree | 6738d11ea384c8574b4b475c8eb83e538a4f47e6 /OvmfPkg/PlatformPei | |
| parent | 305cd4f783fe522230677677d17ae7adc85ebc4b (diff) | |
| download | edk2-eb4d62b0779c3a5766174e4373c95a8b6a967cb7.tar.gz edk2-eb4d62b0779c3a5766174e4373c95a8b6a967cb7.tar.bz2 edk2-eb4d62b0779c3a5766174e4373c95a8b6a967cb7.zip | |
Revert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35"
This reverts commit 75136b29541b0e093a51d2e2c2af8d19855c2b60.
The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814>
triggered a bug / incorrect assumption in QEMU.
QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above
it. When the firmware doesn't satisfy this assumption, QEMU generates an
\_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the
firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign
32-bit MMIO BARs.
Working around the problem in the firmware looks less problematic than
fixing QEMU. Revert the original changes first, before implementing an
alternative fix.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Diffstat (limited to 'OvmfPkg/PlatformPei')
| -rw-r--r-- | OvmfPkg/PlatformPei/Platform.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index fd8eccaf3e..9c013613a1 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -184,13 +184,14 @@ MemMapInitialization ( PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
//
- // The 32-bit PCI host aperture is expected to fall between the top of
- // low RAM and the base of the MMCONFIG area.
+ // The MMCONFIG area is expected to fall between the top of low RAM and
+ // the base of the 32-bit PCI host aperture.
//
PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
- ASSERT (PciBase < PciExBarBase);
+ ASSERT (TopOfLowRam <= PciExBarBase);
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);
- PciSize = (UINT32)(PciExBarBase - PciBase);
+ PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
+ PciSize = 0xFC000000 - PciBase;
} else {
PciSize = 0xFC000000 - PciBase;
}
|