diff options
Diffstat (limited to 'MdePkg/Library/BaseLib/X64')
| -rw-r--r-- | MdePkg/Library/BaseLib/X64/GccInlinePriv.c | 43 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/X64/ReadMsr64.c | 15 | ||||
| -rw-r--r-- | MdePkg/Library/BaseLib/X64/WriteMsr64.c | 13 |
3 files changed, 52 insertions, 19 deletions
diff --git a/MdePkg/Library/BaseLib/X64/GccInlinePriv.c b/MdePkg/Library/BaseLib/X64/GccInlinePriv.c index 98be19b3c7..e4920f2116 100644 --- a/MdePkg/Library/BaseLib/X64/GccInlinePriv.c +++ b/MdePkg/Library/BaseLib/X64/GccInlinePriv.c @@ -2,7 +2,7 @@ GCC inline implementation of BaseLib processor specific functions that use
privlidged instructions.
- Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -10,6 +10,7 @@ #include "BaseLibInternals.h"
+#include <Library/RegisterFilterLib.h>
/**
Enables CPU interrupts.
@@ -64,13 +65,20 @@ AsmReadMsr64 ( {
UINT32 LowData;
UINT32 HighData;
-
- __asm__ __volatile__ (
- "rdmsr"
- : "=a" (LowData), // %0
- "=d" (HighData) // %1
- : "c" (Index) // %2
- );
+ UINT64 Value;
+ BOOLEAN Flag;
+
+ Flag = FilterBeforeMsrRead (Index, &Value);
+ if (Flag) {
+ __asm__ __volatile__ (
+ "rdmsr"
+ : "=a" (LowData), // %0
+ "=d" (HighData) // %1
+ : "c" (Index) // %2
+ );
+ Value = (((UINT64)HighData) << 32) | LowData;
+ }
+ FilterAfterMsrRead (Index, &Value);
return (((UINT64)HighData) << 32) | LowData;
}
@@ -101,17 +109,22 @@ AsmWriteMsr64 ( {
UINT32 LowData;
UINT32 HighData;
+ BOOLEAN Flag;
LowData = (UINT32)(Value);
HighData = (UINT32)(Value >> 32);
- __asm__ __volatile__ (
- "wrmsr"
- :
- : "c" (Index),
- "a" (LowData),
- "d" (HighData)
- );
+ Flag = FilterBeforeMsrWrite (Index, &Value);
+ if (Flag) {
+ __asm__ __volatile__ (
+ "wrmsr"
+ :
+ : "c" (Index),
+ "a" (LowData),
+ "d" (HighData)
+ );
+ }
+ FilterAfterMsrWrite (Index, &Value);
return Value;
}
diff --git a/MdePkg/Library/BaseLib/X64/ReadMsr64.c b/MdePkg/Library/BaseLib/X64/ReadMsr64.c index 5ee7ca53f3..36a349432c 100644 --- a/MdePkg/Library/BaseLib/X64/ReadMsr64.c +++ b/MdePkg/Library/BaseLib/X64/ReadMsr64.c @@ -1,7 +1,7 @@ /** @file
CpuBreakpoint function.
- Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,6 +10,8 @@ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
+#include <Library/RegisterFilterLib.h>
+
unsigned __int64 __readmsr (int register);
#pragma intrinsic(__readmsr)
@@ -28,6 +30,15 @@ AsmReadMsr64 ( IN UINT32 Index
)
{
- return __readmsr (Index);
+ UINT64 Value;
+ BOOLEAN Flag;
+
+ Flag = FilterBeforeMsrRead (Index, &Value);
+ if (Flag) {
+ Value = __readmsr (Index);
+ }
+ FilterAfterMsrRead (Index, &Value);
+
+ return Value;
}
diff --git a/MdePkg/Library/BaseLib/X64/WriteMsr64.c b/MdePkg/Library/BaseLib/X64/WriteMsr64.c index 98c5458d8a..bb030832c4 100644 --- a/MdePkg/Library/BaseLib/X64/WriteMsr64.c +++ b/MdePkg/Library/BaseLib/X64/WriteMsr64.c @@ -1,7 +1,7 @@ /** @file
CpuBreakpoint function.
- Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -10,6 +10,8 @@ Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
**/
+#include <Library/RegisterFilterLib.h>
+
void __writemsr (unsigned long Register, unsigned __int64 Value);
#pragma intrinsic(__writemsr)
@@ -30,7 +32,14 @@ AsmWriteMsr64 ( IN UINT64 Value
)
{
- __writemsr (Index, Value);
+ BOOLEAN Flag;
+
+ Flag = FilterBeforeMsrWrite (Index, &Value);
+ if (Flag) {
+ __writemsr (Index, Value);
+ }
+ FilterAfterMsrWrite (Index, &Value);
+
return Value;
}
|