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* ArmPkg/ArmMmuLib ARM: Isolate the access flag from AP maskArd Biesheuvel2023-03-161-0/+2
| | | | | | | | | | | Split the ARM permission fields in the short descriptors into an access flag and AP[2:1] as per the recommendation in the ARM ARM. This makes the access flag available separately, which allows us to implement EFI_MEMORY_RP memory analogous to how it will be implemented for AArch64. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
* ArmPkg: Remove RVCT supportRebecca Cran2022-05-134-666/+0
| | | | | | | | RVCT is obsolete and no longer used. Remove support for it. Signed-off-by: Rebecca Cran <quic_rcran@quicinc.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
* ArmPkg: Apply uncrustify changesMichael Kubacki2021-12-072-19/+20
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3737 Apply uncrustify changes to .c/.h files in the ArmPkg package Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Andrew Fish <afish@apple.com>
* ArmPkg: Fix Ecc error 8003Pierre Gondois2021-04-281-3/+3
| | | | | | | | | | | | | | | | | | This patch fixes the following Ecc reported error: The #ifndef at the start of an include file should have one postfix underscore, and no prefix underscore character Some include guards have been modified to match the name of the header file. Some comments have also been added on the closing '#endif'. Cc: Bret Barkelew <bret.barkelew@microsoft.com> Cc: Sean Brogan <sean.brogan@microsoft.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org> Cc: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>
* ArmPkg: Add helper to read the CCSIDR2 registerRebecca Cran2021-02-082-0/+20
| | | | | | | | Add helper function to read the CCSIDR2 register. This is used when CCIDX is supported in AARCH32 mode. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Add helper to read CCIDX statusRebecca Cran2021-02-081-1/+18
| | | | | | | | Add a helper function to determine CCIDX support. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Fix the return type of the ReadCCSIDR functionRebecca Cran2021-02-082-2/+2
| | | | | | | | | | | | | When CCIDX is supported, the Current Cache Size ID Register contains data above 32 bits: namely the number of sets. Avoid truncating this by returning a UINTN instead of UINT32. On AARCH32, the expanded number of sets data can be read via the CCSIDR2 register. Also, add Doxygen comments for the function. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg: Add helper function to read the Memory Model Feature Register 4Rebecca Cran2021-02-083-2/+14
| | | | | | | | | In AARCH32, CCIDX support is indicated in the MMFR4 register - unlike under AARCH64 where it's in MMFR2. Add a helper function to read it. Signed-off-by: Rebecca Cran <rebecca@nuviainc.com> Reviewed-by: Sami Mujawar <sami.mujawar@arm.com> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib: move ArmReadIdPfr0/1 into private header ArmV7Lib.hLeif Lindholm2020-12-181-0/+12
| | | | | | | | | | | ArmReadIdPfr0 () and ArmReadIdPfr1 () are now used only inside ArmLib. Remove the prototypes from the public header to discourage new id register accessor additions, and direct id register access in general. Move them into local header Arm/ArmV7Lib.h. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg: add ArmHasSecurityExtensions () helper functionLeif Lindholm2020-12-181-0/+15
| | | | | | | | | | | | | Create a helper function to eliminate direct feature register reading. Returns BOOLEAN True if the CPU implements the Security extensions, otherwise returns BOOL False. This function is only implemented for ARM, not AArch64. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/ArmLib: add ArmHasGicSystemRegisters () helper functionLeif Lindholm2020-12-181-0/+16
| | | | | | | | | | | | Create a helper function to eliminate direct feature register reading, which gets messy in code shared between ARM/AArch64. Returns BOOLEAN True if the CPU implements the GIC System Register Interface (any version), otherwise returns BOOL False. Cc: Ard Biesheuvel <ard.biesheuvel@arm.com> Signed-off-by: Leif Lindholm <leif@nuviainc.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
* ArmPkg/ArmLib: ASSERT on set/way cache ops being used with MMU onArd Biesheuvel2020-03-051-0/+7
| | | | | | | | | | | On ARMv7 and up, doing cache maintenance by set/way is only permitted in the context of on/offlining a core, and any other uses should be avoided. Add ASSERT()s in the right place to ensure that any uses with the MMU enabled are caught in DEBUG builds. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib: clean up library includesArd Biesheuvel2020-03-051-4/+6
| | | | | | | | | | | | Suspiciously, ArmLib's INF does not contain a [LibraryClasses] section at all, but it turns out that all the library includes it contains (except for ArmLib.h itself) are actually bogus so let's just drop all of them. While at it, replace <Uefi.h> with the more accurate <Base.h> for a BASE type module, and put the includes in a consistent order. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib: move set/way helper functions into private headerArd Biesheuvel2020-03-051-0/+18
| | | | | | | | | | | | | The clean/invalidate helper functions that operate on a single cache line identified by set, way and level in a special, architected format are only used by the implementations of the clean/invalidate routines that operate on the entire cache hierarchy, as exposed by ArmLib. The latter routines will be deprecated soon, so move the helpers out of ArmLib.h and into a private header so they are safe from abuse. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif@nuviainc.com>
* ArmPkg/ArmLib ARM: set .fpu to let Clang 7 assemble ArmV7Support.SArd Biesheuvel2019-05-311-0/+2
| | | | | | | | | | | Clang 7 complains about the vmsr instruction in ArmV7Support.S, which is only available on cores that implement some flavour of VFP. So set the .fpu to NEON like we do in some other places. Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0910-70/+10
| | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmLib: add support for reading the max physical address space sizeArd Biesheuvel2018-11-292-0/+16
| | | | | | | | | | | Add a helper function that returns the maximum physical address space size as supported by the current CPU. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memoryArd Biesheuvel2018-06-211-2/+0
| | | | | | | | | | | | Given that these days, our ARM port only supports ARMv7 and later, we can assume that the page table walker's memory accesses are cache coherent, and so there is no need to perform cache maintenance. It does require the page tables themselves to reside in memory mapped as writeback cacheable so ASSERT() that this is the case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
* ArmPkg/Library/ArmLib: add ArmWriteSctlrMichael Zimmermann2018-01-152-0/+7
| | | | | | | | | | This currently isn't needed by anything in the edk2 tree but it's useful for externally maintained platforms which have to set this register e.g. to disable alignment aborts. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
* ArmPkg/ArmLib: remove indirection layer from timer register accessorsArd Biesheuvel2017-01-201-167/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The generic timer support libraries call the actual system register accessor function via a single pair of functions ArmArchTimerReadReg() and ArmArchTimerWriteReg(), which take an enum argument to identify the register, and return output values by pointer reference. Since these functions are never called with a non-immediate argument, we can simply replace each invocation with the underlying system register accessor instead. This is mostly functionally equivalent, with the exception of the bounds check for the enum (which is pointless given the fact that we never pass a variable), the check for the presence of the architected timer (which only makes sense for ARMv7, but is highly unlikely to vary between platforms that are similar enough to run the same firmware image), and a check for enum values that refer to the HYP view of the timer, which we never referred to anywhere in the code in the first place. So get rid of the middle man, and update the ArmGenericTimerPhyCounterLib and ArmGenericTimerVirtCounterLib implementations to call the system register accessors directly. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
* ArmPkg/ArmBaseLib: clean up directory structureArd Biesheuvel2016-09-0811-0/+1606
For historical reasons, the files under ArmLib are split up into 'common' files under Common/, containing common C files as well as AArch64 and Arm specific asm files, and ArmV7 and AArch64 files under ArmV7/ and AArch64/, respectively. This presumably dates back to the time when ArmLib supported different revisions of the 32-bit architecture (i.e., pre-V7) Since the PI spec requires V7 or later, we can simplify this to Arm/ and AArch64, which aligns ArmLib with the majority of other modules that carry ARM or AArch64 specific code. So move the files around so that shared files live at the same level as ArmBaseLib.inf, and ARM/AArch64 specific files live in Arm/ or AArch64/, respectively. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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