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* IntelFsp2Pkg: FspSecCore support for X64Ted Kuo2022-04-161-2/+8
| | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3893 1.Added FspSecCore support for X64. 2.Bumped FSP header revision to 7 to indicate FSP 64bit is supported. 3.Corrected few typos. Cc: Chasel Chiu <chasel.chiu@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Ashraf Ali S <ashraf.ali.s@intel.com> Signed-off-by: Ted Kuo <ted.kuo@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
* IntelFsp2Pkg: Support Multi-Phase SiInit and debug handlers.Chasel Chiu2020-05-141-0/+52
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2698 To enhance FSP silicon initialization flexibility an optional Multi-Phase API is introduced and FSP header needs update for new API offset. Also new SecCore module created for FspMultiPhaseSiInit API New ARCH_UPD introduced for enhancing FSP debug message flexibility now bootloader can pass its own debug handler function pointer and FSP will call the function to handle debug message. To support calling bootloader functions, a FspGlobalData field added to indicate if FSP needs to switch stack when FSP running on separate stack from bootloader. Cc: Maurice Ma <maurice.ma@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com> Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>