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* UefiCpuPkg: CpuPageTableLibTestHost: Disable Random Test SuiteOliver Smith-Denny2024-08-271-7/+8
| | | | | | | | | | | | | Commit 2f499c36db51980ad43fc6b578c7678a1720bd9c commented out the RandomTestCase tests in CpuPageTableLibTestHost, but it left the test suite being registered without any tests. This causes a failure for tools that check to ensure tests are being registered with test suites. This patch comments out the test suite in addition to the tests being added to it. Signed-off-by: Oliver Smith-Denny <osde@linux.microsoft.com>
* UefiCpuPkg:fix issue when splitting paging entryDun Tan2024-06-041-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to fix issue when splitting leaf paging entry in CpuPageTableLib code. In previous code, before we assign the new child paging structure address to the content of splitted paging entry, PageTableLibSetPnle() is called to make sure the bit7 is set to 0, which indicate the previous leaf entry is changed to non-leaf entry now. There is a gap between we change the bit7 and we assign the new child paging structure address to the content of the splitted paging entry. If the address of code execution or data access happens to be in the range covered by the splitted paging entry, this gap may cause issue. In this patch, we prepare the new paging entry content value in a local variable and assign the value to the splitted paging entry at once. The volatile keyword is used to ensure that no optimization will occur in compilation. Signed-off-by: Dun Tan <dun.tan@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Zhou Jianfeng <jianfeng.zhou@intel.com>
* UefiCpuPkg/CpuPageTableLib: qualify page table accesses as volatileZhou Jianfeng2024-03-011-18/+18
| | | | | | | | | | | | | | | | | | | | | Add volatile qualifier to page table related variable to prevent compiler from optimizing away the variables which may lead to unexpected result. Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Pedro Falcato <pedro.falcato@gmail.com> Cc: Zhang Di <di.zhang@intel.com> Cc: Tan Dun <dun.tan@intel.com> Cc: Michael Brown <mcb30@ipxe.org> Message-Id: <20240301025447.41170-1-jianfeng.zhou@intel.com> Reviewed-by: Michael Brown <mcb30@ipxe.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> [lersek@redhat.com: reconstruct commit manually, from corrupt patch email on-list]
* UefiCpuPkg/CpuPageTableLib: Fix IN OUT parameters marked as INZhou Jianfeng2024-03-011-16/+16
| | | | | | | | | | | | | | | | | | | Some IN OUT parameters in CpuPageTableMap.c were mistakenly marked as IN. "IN" replaced with "IN OUT" in the following interfaces: PageTableLibSetPte4K(): Pte4K PageTableLibSetPleB(): PleB PageTableLibSetPle(): Ple PageTableLibSetPnle(): Pnle Reviewed-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Message-Id: <20240222023922.29275-1-jianfeng.zhou@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Fix issue that IsModified is wrongly set in PageTableMapZhiguang Liu2024-02-221-5/+13
| | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4614 About the IsModified, current function doesn't consider that hardware also may change the pagetable. The issue is that in the first call of internal function PageTableLibMapInLevel, the function assume page table is not changed, and add ASSERT to check. But hardware may change the page table, which cause the ASSERT happens. Fix the issue by adding addtional condition to only check if the page table is changed when the software want to modify the page table. Also, add more comment to explain this behavior. Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Crystal Lee <CrystalLee@ami.com.tw> Cc: Pedro Falcato <pedro.falcato@gmail.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Enhance function header for PageTableMap()Zhiguang Liu2024-02-221-0/+1
| | | | | | | | | | | PageTableMap() only modifies the PageTable root pointer when creating from zero. Explicitly explain it in function header. Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Reduce and optimize access to attributeZhou Jianfeng2024-02-061-33/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit is to reduce and optimize access to attribute in CpuPageTableLib. Unreasonable writing to attribute of page table may leads to expection. The assembly code for C code Pnle->Bits.Present = Attribute->Bits.Present looks like: and dword [rcx], 0xfffffffe and eax, 0x1 or [rcx], eax In case Pnle->Bits.Present and Attribute->Bits.Present is 1, Pnle->Bits.Present will be set to 0 for short time(2 instructions) which is unexpected. If some other core is accessing the page, it may leads to expection. This change reduce and optimize access to attribute of page table, attribute of page table is set only when it need to be changed. Signed-off-by: Zhou Jianfeng <jianfeng.zhou@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib/TestCase: Refine test case for PAE paging.Zhiguang Liu2023-12-062-4/+34
| | | | | | | | | | | | Refine test case: 1. Check PAE paging reserved bits is zero. 2. Set stack as random value. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Init local variable before using it.Zhiguang Liu2023-12-061-3/+1
| | | | | | | | | | | | | The local variable OneOfPagingEntry is used before initialized, this may cause reserved bit in page table entry is set especially in PAE paging mode. The bug is random because it depends on the value in stack. Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/Test: Disable random test casesRay Ni2023-03-311-10/+10
| | | | | | | | | | | | The random test cases just run for too long that may cause timeout in CI test. Disable them for now. Co-authored-by: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Michael Kubacki <michael.kubacki@microsoft.com> Reviewed-by: Sean Brogan <sean.brogan@microsoft.com>
* UefiCpuPkg/CpuPageTableLib: Reduce the number of random testsDun Tan2023-03-271-5/+5
| | | | | | | | | | | | | | Reduce the number of random tests. In previous patch, non-1:1 mapping is enbaled and it may need more than an hour and a half for the CI test, which may lead to CI timeout. Reduce the number of random test count to pass the CI. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add RandomTest for PAE pagingDun Tan2023-03-273-6/+11
| | | | | | | | | | | Add RandomTest for PAE paging. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Enable PAE pagingDun Tan2023-03-273-11/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify CpuPageTableLib code to enable PAE paging. In PageTableMap() API: When creating new PAE page table, after creating page table, set all MustBeZero fields of 4 PDPTE to 0. The MustBeZero fields are treated as RW and other attributes by the common map logic. So they might be set to 1. When updating exsiting PAE page table, the special steps are: 1.Prepare 4K-aligned 32bytes memory in stack for 4 temp PDPTE. 2.Copy original 4 PDPTE to the 4 temp PDPTE and set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. 4.After updating the page table, set the MustBeZero fields of 4 temp PDPTE to 0. 5.Copy the temp PDPTE to original PDPTE. In PageTableParse() API, also create 4 temp PDPTE in stack. Copy original 4 PDPTE to the 4 temp PDPTE. Then set the RW, UserSupervisor to 1 and set Nx of 4 temp PDPTE to 0. Finally use the address of temp PDPTE as the page table address. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Combine branch for non-present and leaf ParentEntryDun Tan2023-03-271-53/+32
| | | | | | | | | | | | | Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add check for page table creationDun Tan2023-03-271-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Add code to compare ParentPagingEntry Attribute&Mask and input Attribute&Mask to decide if new next level page table is needed in non-present ParentPagingEntry condition. This can help avoid unneccessary page table creation. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry).And we only want to map [1G, 1G+2M] linear address still as non-present. The expected behaviour should be nothing happens in the process. However, previous code logic doesn't check if ParentPagingEntry Attribute&Mask and input Attribute&Mask are the same in non-present ParentPagingEntry condition. Then a new 4K memory is allocated for Lv2 since 1G+2M is not 1G-aligned. So when ParentPagingEntry is non-present, before allocate 4K memory for next level paging, we also check if ParentPagingEntry Attribute& Mask and input Attribute&Mask are the same. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg: Modify UnitTest code since tested API is changedZhiguang Liu2023-03-273-59/+67
| | | | | | | | | | | | Last commit changed the CpuPageTableLib API PageTableMap, unit test code should also be modified. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg: Fix IA32 build failure in CpuPageTableLib.infZhiguang Liu2023-03-272-73/+74
| | | | | | | | | | | | | | | | | | | The definition of IA32_MAP_ATTRIBUTE has 64 bits, and one of the bit field PageTableBaseAddress is from bit 12 to bit 52. This means if the compiler treats the 64bits value as two UINT32 value, the field PageTableBaseAddress spans two UINT32 value. That's why when building in NOOPT mode in IA32, the below issue is noticed: unresolved external symbol __allshl This patch fix the build failure by seperate field PageTableBaseAddress into two fields, make sure no field spans two UINT32 value. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuPageTableLib: Modify RandomTest to check IsModifiedDun Tan2023-03-271-12/+33
| | | | | | | | | | | | | | Modify RandomTest to check if parameter IsModified of PageTableMap() correctlly indicates whether input page table is modified or not. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Add OUTPUT IsModified parameter.Dun Tan2023-03-273-43/+81
| | | | | | | | | | | | | Add OUTPUT IsModified parameter in PageTableMap() to indicate if page table has been modified. With this parameter, caller can know if need to call FlushTlb when the page table is in CR3. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Enable non-1:1 mapping in random testDun Tan2023-03-271-4/+4
| | | | | | | | | | | | | | Enable non-1:1 mapping in random test. In previous test, non-1:1 test will fail due to the non-1:1 mapping issue in CpuPageTableLib and invalid Input Mask when creating new page table or mapping not-present range. Now these issue have been fixed. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Modify RandomTest to check Mask/AttrDun Tan2023-03-272-26/+133
| | | | | | | | | | | | | | | | | | | | | Modify RandomTest to check invalid input. When creating new page table or updating exsiting page table: 1.If set [LinearAddress, LinearAddress+Length] to non-present, all other attributes should not be provided. 2.If [LinearAddress, LinearAddress+Length] contain non-present range, the Returnstatus of PageTableMap() should be InvalidParameter when: 2.1Some of attributes are not provided when mapping non-present range to present. 2.2Set any other attribute without setting the non-present range to Present. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiCpuPkg/CpuPageTableLib: Add LastMapEntry pointerDun Tan2023-03-271-8/+10
| | | | | | | | | | | Add LastMapEntry pointer to replace MapEntrys->Maps[MapsIndex] in SingleMapEntryTest () of RandomTest. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Cc: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Modify RandomBoolean() in RandomTestDun Tan2023-03-271-22/+21
| | | | | | | | | | | | | | Add an input parameter to control the probability of returning true. Change RandomBoolean() in RandomTest from 50% chance returning true to returning true with the percentage of input Probability. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add manual test to check Mask and AttrDun Tan2023-03-271-2/+127
| | | | | | | | | | | | | | | | | | | | Add manual test case to check input Mask and Attribute. The check steps are: 1.Create Page table to cover [0, 2G]. All fields of MapMask should be set. 2.Update Page table to set [2G - 8K,2G] from present to non-present. All fields of MapMask except present should not be set. 3.Still set [2G - 8K, 2G] as not present, this case is permitted. But set [2G - 8K, 2G] as RW is not permitted. 4.Update Page table to set [2G - 8K, 2G] as present and RW. All fields of MapMask should be set. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Add check for Mask and AttrDun Tan2023-03-271-1/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | For different usage, check if the combination for Mask and Attr is valid when creating or updating page table. 1.For non-present range 1.1Mask.Present is 0 but some other attributes is provided. This case is invalid. 1.2Mask.Present is 1 and Attr.Present is 0. In this case,all other attributes should not be provided. 1.3Mask.Present is 1 and Attr.Present is 1. In this case,all attributes should be provided to intialize the attribute. 2.For present range 2.1Mask.Present is 1 and Attr.Present is 0.In this case, all other attributes should not be provided. All other usage for present range is permitted. In the mentioned cases, 1.2 and 2.1 can be merged into 1 check. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Fix issue when splitting leaf entryDun Tan2023-03-271-8/+11
| | | | | | | | | | | | | | | | | | When splitting leaf parent entry to smaller granularity, create child page table before modifing parent entry. In previous code logic, when splitting a leaf parent entry, parent entry will point to a null 4k memory before child page table is created in this 4k memory. When the page table to be modified is the page table in CR3, if the executed CpuPageTableLib code is in the range mapped by the modified leaf parent entry, then issue will happen. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Clear PageSize bit(Bit7) for non-leafDun Tan2023-03-271-1/+2
| | | | | | | | | | | | | Clear PageSize bit(Bit7) for non-leaf entry in PageTableLibSetPnle. This function is used to set non-leaf entry attributes so it should make sure that the PageSize bit of the entry should be 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Fix the non-1:1 mapping issueDun Tan2023-03-271-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | In previous code logic, when splitting a leaf parent entry to smaller granularity child page table, if the parent entry Attribute&Mask(without PageTableBaseAddress field) is equal to the input attribute&mask(without PageTableBaseAddress field), the split process won't happen. This may lead to failure in non-1:1 mapping. For example, there is a page table in which [0, 1G] is mapped(Lv4[0] ,Lv3[0,0], a non-leaf level4 entry and a leaf level3 entry). And we want to remap [0, 2M] linear address range to [1G, 1G + 2M] with the same attibute. The expected behaviour should be: split Lv3[0,0] entry into 512 level2 entries and remap the first level2 entry to cover [0, 2M]. But the split won't happen in previous code since PageTableBaseAddress of input Attribute is not checked. So, when checking if a leaf parent entry needs to be splitted, we should also check if PageTableBaseAddress calculated by parent entry is equal to the value caculated by input attribute. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginningDun Tan2023-03-271-9/+12
| | | | | | | | | | | | Move some local variable initialization to the beginning of the function. Also delete duplicated calculation for RegionLength. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Add check for input LengthDun Tan2023-03-271-1/+5
| | | | | | | | | | | | Add check for input Length in PageTableMap (). Return RETURN_SUCCESS when input Length is 0. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib: Remove unneeded 'if' conditionDun Tan2023-03-271-10/+1
| | | | | | | | | | | | | | Remove unneeded 'if' condition in CpuPageTableLib code. The deleted code is in the code branch for present non-leaf parent entry. So the 'if' check for (ParentPagingEntry->Pnle.Bits.Present == 0) is always FALSE. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
* UefiCpuPkg/CpuPageTableLib:Support PAE paging for PageTableParseTan, Dun2022-10-171-2/+1
| | | | | | | | | Support PAE paging for PageTableParse API in CpuPageTableLib. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com>
* UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit testZhiguang Liu2022-08-317-0/+7254
| | | | | | | | | | | | | | | | | | | | | | Add host based unit tests for the CpuPageTableLib services. Unit test focuses on PageTableMap function, containing two kinds of test cases: manual test case and random test case. Manual test case creates some corner case to test function PageTableMap. Random test case generates multiple random memory entries (with random attribute) as the input of function PageTableMap to get the output pagetable. Output pagetable will be validated and be parsed to get output memory entries, and then the input and output memory entries will be compared to verify the functionality. The unit test is not perfect yet. There are options for random test, and some of them control the test coverage, and some option are not ready. Will enhance in the future. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* Revert "UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test"Liming Gao2022-08-287-7254/+0
| | | | | | | | | This reverts commit 2812668bfc121ee792cf3302195176ef4a2ad0bc for tag202208. This feature will be merged after stable tag 202208 is created. Signed-off-by: Liming Gao <gaoliming@byosoft.com.cn> Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com> Acked-by: Ard Biesheuvel <ardb@kernel.org>
* UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit testZhiguang Liu2022-08-167-0/+7254
| | | | | | | | | | | | | | | | | | | | | | Add host based unit tests for the CpuPageTableLib services. Unit test focuses on PageTableMap function, containing two kinds of test cases: manual test case and random test case. Manual test case creates some corner case to test function PageTableMap. Random test case generates multiple random memory entries (with random attribute) as the input of function PageTableMap to get the output pagetable. Output pagetable will be validated and be parsed to get output memory entries, and then the input and output memory entries will be compared to verify the functionality. The unit test is not perfect yet. There are options for random test, and some of them control the test coverage, and some option are not ready. Will enhance in the future. Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* CpuPageTableLib: define IA32_PAGE_LEVEL enum type internallyRay Ni2022-08-092-6/+14
| | | | | | | | The change doesn't change functionality behavior. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Fix bug that wrongly requires extra size for mappingRay Ni2022-08-091-8/+5
| | | | | | | | | | | | | | | | | | | | | | With following paging structure to map [2M-4K, 2M] as P = 1, RW = 0, [2M, 4M] as P = 1, RW = 1: PML4[0] -> PDPTE[0] -> PDE[0](RW = 0) -> PTE[255](P = 0, RW = 0) -> PDE[1](RW = 1) When a new request to map [2M-4K, 2M+4K] as P = 1, RW = 1, CpuPageTableMap() wrongly requests 4K buffer size for the new mapping request. But in fact, for [2M-4K, 2M] request, PTE[255] can be changed in place, for [2M, 2M+4K], no change is needed because PDE[1].RW = 1 already. The change fixes the bug. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Fix a bug to avoid unnecessary changing to page tableRay Ni2022-08-091-9/+32
| | | | | | | | | | | | | | | | | | | | | | | | | With the following paging structure that maps [0, 2G] with ReadWrite bit set. PML4[0] --> PDPTE[0] --> PDE[0-255] \-> PDPTE[1] --> PDE[0-255] If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called to change [0, 2M] as read-only, today's logic unnecessarily changes the paging structure in 2 aspects: 1. When setting PageTableBaseAddress in the entry, the code clears all attributes. 2. Even the ReadWrite bit in parent entry is not set, the code clears the ReadWrite bit in the leaf entry. First change is wrong. It should not change other attributes when setting the PA. Second change is unnecessary. Because the parent entry already declares the whole region as read-only, there is no need to clear ReadWrite bit in the leaf entry again. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Fix parent attributes are not inherited properlyRay Ni2022-08-092-17/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | With the following paging structure that maps [0, 2G] with ReadWrite bit set. PML4[0] --> PDPTE[0] --> PDE[0-255] \-> PDPTE[1] --> PDE[0-255] If ReadWrite bit is cleared in PML4[0] and PageTableMap() is called to change [0, 2M] as writable, today's logic doesn't inherit the parent entry's attributes when determining the child entry's attributes. It just sets the PDPTE[0].PDE[0].ReadWrite bit. But since the PML4[0].ReadWrite is 0, [0, 2M] is still read-only. The change fixes the bug. If the inheritable attributes in ParentPagingEntry conflicts with the requested attributes, let the child entries take the parent attributes and loosen the attribute in the parent entry. E.g.: when PDPTE[0].ReadWrite = 0 but caller wants to map [0-2MB as ReadWrite = 1 (PDE[0].ReadWrite = 1), we need to change PDPTE[0].ReadWrite = 1 and let all PDE[0-255].ReadWrite = 0 first. Then change PDE[0].ReadWrite = 1. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Avoid treating non-leaf entry as leaf oneRay Ni2022-08-091-4/+7
| | | | | | | | | | | | Today's logic wrongly treats the non-leaf entry as leaf entry and updates its paging attributes. The patch fixes the bug to only update paging attributes for non-present entries or leaf entries. Signed-off-by: Ray Ni <ray.ni@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Split the page entry when LA is aligned but PA is notRay Ni2022-08-091-1/+6
| | | | | | | | | | | | | When PageTableMap() is called to create non 1:1 mapping such as [0, 1G) to [8K, 1G+8K), it should split the page entry to the 4K page level, but old logic has a bug that it just uses 1G page entry. The patch fixes the bug. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Refactor the logicRay Ni2022-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The patch replaces LinearAddress + Offset == RegionStart with ((LinearAddress + Offset) & RegionMask) == 0 The replace should not cause any behavior change. Because: 1. In first loop of while when LinearAddress + Offset == RegionStart, because the lower "BitStart" bits of RegionStart are all-zero, all lower "BitStart" bits of (LinearAddress + Offset) are all-zero. Because all lower "BitStart" bits of RegionMask is all-one and bits are all-zero, ((LinearAddress + Offset) & RegionMask) == 0. 2. In following loops of the while, even RegionStart is increased by RegionLength, the lower "BitStart" bits are still all-zero. So the two expressions still semantically equal to each other. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* CpuPageTableLib: Fix a bug when a bit is 1 in Attribute, 0 in MaskRay Ni2022-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To reproduce the issue: UINTN PageTable; VOID *Buffer; UINTN PageTableBufferSize; IA32_MAP_ATTRIBUTE Attribute; IA32_MAP_ATTRIBUTE Mask; RETURN_STATUS Status; Attribute.Uint64 = 0; Mask.Uint64 = 0; PageTableBufferSize = 0; PageTable = 0; Buffer = NULL; Attribute.Bits.Present = 1; Attribute.Bits.Nx = 1; Mask.Bits.Present = 1; Mask.Uint64 = MAX_UINT64; // // Create page table to cover [0, 10M) // Status = PageTableMap ( &PageTable, PagingMode, Buffer, &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask ); ASSERT (Status == RETURN_BUFFER_TOO_SMALL); Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); Status = PageTableMap ( &PageTable, PagingMode, Buffer, &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &Attribute, &Mask ); ASSERT (Status == RETURN_SUCCESS); // // Change the mapping for [0, 4KB) // No change actually. Just clear Nx bit in Mask. // Mask.Bits.Nx = 0; PageTableBufferSize = 0; Status = PageTableMap ( &PageTable, PagingMode, NULL, &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &Attribute, &Mask ); ASSERT (Status == RETURN_SUCCESS); // FAIL!! The root cause is when comparing the existing mapping attributes against the requested one, Mask is not used but it should be used. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CpuPageTableLib: Return error on invalid parametersRay Ni2022-08-091-0/+7
| | | | | | | | | When LinearAddress or Length is not aligned on 4KB, PageTableMap() should return Invalid Parameter. Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg: Create CpuPageTableLib for manipulating X86 paging structsRay Ni2022-08-094-0/+1112
The lib includes two APIs: * PageTableMap It creates/updates mapping from LA to PA. The implementation only supports paging structures used in 64bit mode now. PAE paging structure support will be added in future. * PageTableParse It parses the page table and returns the mapping relations in an array of IA32_MAP_ENTRY. It passed some stress tests. These test code will be upstreamed in other patches following edk2 Unit Test framework. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
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