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* UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic.Dong, Eric2019-08-211-1/+30
| | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action.Dong, Eric2019-08-211-47/+63
| | | | | | Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros.Dong, Eric2019-08-211-3/+41
| | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2040 Add below new micros which test the current value before write the new value. Only write new value when current value not same as new value. CPU_REGISTER_TABLE_TEST_THEN_WRITE32 CPU_REGISTER_TABLE_TEST_THEN_WRITE64 CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD Also add below API: CpuRegisterTableTestThenWrite Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Cc: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Clean up useless ConsoleLogLock spinlock.Eric Dong2019-08-092-2/+0
| | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2060 Remove the useless ConsoleLogLock spinlock. Signed-off-by: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg: Update code to include register definitions from MdePkgNi, Ray2019-08-097-21/+21
| | | | | | | Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabledNi, Ray2019-08-094-2/+32
| | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2008 MpInitLib is the library that's responsible to wake up APs to provide MP PPI and Protocol services. The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57. Without this change, AP may enter to GP fault when BSP's 5-level page table is set to AP during AP wakes up. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Remove debug message.Eric Dong2019-08-061-22/+0
| | | | | | | | | | | | This debug message may be called by BSP and APs. It may caused ASSERT when APs call this debug code. In order to avoid system boot assert, Remove this debug message. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/MpInitLib: don't shadow the microcode patch twice.Eric Dong2019-08-021-29/+33
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1982 MpInitLibInitialize in MpLib.c will be invoked on both PEI and DXE CPU code, MicrocodeDetect would be performed twice and copy Microcode from flash to memory twice as well, which consider as duplicate work to lead longer boot time. This patch just use microcode memory copied in PEI phase if exist. Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Start all processors simultaneously.Eric Dong2019-07-295-23/+53
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 For semaphore type register, it required all processors to do the task at the same time. Current logic begins BSP's task after all APs have finished their tasks. This will caused set semaphore task hang if semaphore has package level type. This patch use new EDKII_PEI_MP_SERVICES2_PPI to start all processors at the same time to fix the potential hang issue. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLibUp: Add MpInitLibStartupAllCPUs API.Eric Dong2019-07-291-0/+35
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Add new MpInitLibStartupAllCPUs API uses to start all processors at the same time. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: Add MpInitLibStartupAllCPUs API.Eric Dong2019-07-294-10/+67
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1973 Add new MpInitLibStartupAllCPUs API uses to start all processors at the same time. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: avoid use dynamic PCD.Dong, Eric2019-07-183-102/+79
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1972 Function in this library may be used by APs. Assert will be trig if AP uses dynamic pcd. This patch enhance the current code, remove the unnecessary usage of dynamic PCD. This change try to avoid report this issue again later. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiServices table.Eric Dong2019-07-182-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1972 AP calls CollectProcessorData() to collect processor info. CollectProcessorData function finally calls PcdGetSize function to get DynamicPCD PcdCpuFeaturesSetting value. PcdGetSize will use PeiServices table which caused below assert info: Processor Info: Package: 1, MaxCore : 4, MaxThread: 1 Package: 0, Valid Core : 4 ASSERT [CpuFeaturesPei] c:\projects\jsl\jsl_v1193\Edk2\MdePkg\Library \PeiServicesTablePointerLibIdt\PeiServicesTablePointer.c(48): PeiServices != ((void *) 0) This change uses saved global pcd size instead of calls PcdGetSize to fix this issue. Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Star Zeng <star.zeng@intel.com> Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
* UefiCpuPkg DxeRegisterCpuFeaturesLib: Fix VS2012 build failureStar Zeng2019-07-181-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1968 The new VS2012 build failure is caused by 7a0df26. xxx\registercpufeatureslib\dxeregistercpufeatureslib.c(258) : warning C4701: potentially uninitialized local variable 'MpEvent' used It is a false positive alarm. MpEvent is assigned at line 238 and will be used at line 258, both lines are controlled by "if (CpuFeaturesData->NumberOfCpus > 1)". This patch initializes MpEvent to suppress incorrect compiler/analyzer warnings. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Dandan Bi <dandan.bi@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg CpuCommonFeaturesLib: Enhance Ppin codeStar Zeng2019-07-163-12/+72
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1961 Enhance Ppin code to enable and unlock for TRUE State, and disable and lock for FALSE State. Note: enable and lock could not be set both. According to SDM, once Enable_PPIN is set, attempt to write 1 to LockOut will cause #GP, and writing 1 to LockOut is permitted only if Enable_PPIN is clear. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg RegisterCpuFeaturesLib: Fix an ASSERTION issueStar Zeng2019-07-113-27/+37
| | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1968 We met assertion like below, it happens when there is only one processor. ASSERT_EFI_ERROR (Status = Not started) ASSERT [CpuFeaturesDxe] X:\XXX\XXX\RegisterCpuFeaturesLib\ DxeRegisterCpuFeaturesLib.c(149): !EFI_ERROR (Status) The code should not call StartupAllAPs when there is only one processor. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: MicrocodeDetect: Ensure checked range is validZhichao Gao2019-06-271-3/+9
| | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1934 0x0 MicrocodeBegin MicrocodeEntry MicrocodeEnd 0xffffffff |--------------|---------------|---------------|---------------| valid TotalSize TotalSize is only valid between 0 and (MicrocodeEnd - MicrocodeEntry). So add '(UINTN)MicrocodeEntryPoint > (MAX_ADDRESS - TotalSize)' before '((UINTN)MicrocodeEntryPoint + TotalSize) > MicrocodeEnd' to make sure ((UINTN)MicrocodeEntryPoint + TotalSize) wouldn't overflow. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Liming Gao <liming.gao@intel.com> Signed-off-by: Zhichao Gao <zhichao.gao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MpInitLib: Decrease NumApsExecuting only for ApInitConfigRay Ni2019-06-101-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch fixes the bug that the memory under 1MB is modified by firmware in S3 boot. Root cause is a racing condition in MpInitLib: 1. BSP: WakeUpByInitSipiSipi is set by NotifyOnS3SmmInitDonePpi() 2. BSP: WakeUpAP() wakes all APs to run certain procedure. 2.1. AllocateResetVector() uses <1MB memory for wake up vector. 2.1. FillExchangeInfoData() resets NumApsExecuting to 0. 2.2. WaitApWakeup() waits AP to clear WAKEUP_AP_SIGNAL. 3. AP: ApWakeupFunction() clears WAKEUP_AP_SIGNAL to inform BSP. 5. BSP: FreeResetVector() restores the <1MB memory 4. AP: ApWakeupFunction() calls the certain procedure. 4.1. NumApsExecuting is decreased. #4.1 happens after the 1MB memory is restored so the result is memory below 1MB is changed by #4.1 It happens only when the AP executes procedure a bit longer. AP returns back to ApWakeupFunction() from procedure after BSP restores the <1MB memory. Since NumApsExecuting is only used when InitFlag == ApInitConfig for counting the processor count. The patch moves the NumApsExecuting decrease to the path when InitFlag == ApInitConfig. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Nandagopal Sathyanarayanan <nandagopal.sathyanarayanan@intel.com>
* UefiCpuPkg/MpInitLib: increase NumApsExecuting only for ApInitConfigRay Ni2019-06-101-7/+7
| | | | | | | | | | | | | | NumApsExecuting is only used when InitFlag == ApInitConfig for counting the processor count. The patch changes Ia32 version of waking up vector assembly code to align to x64 version of waking up vector assembly code. After the change both versions of waking up vector increase NumApsExecuting when InitFlag == ApInitConfig. Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg CpuCommFeaturesLib: Reduce to set MSR_IA32_CLOCK_MODULATIONStar Zeng2019-06-063-26/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1810 This patch covers two problems. 1. Current code gets CPUID_THERMAL_POWER_MANAGEMENT in ClockModulationInitialize() and uses its ECMD bit for all processors. But ClockModulationInitialize() is only executed by BSP, that means the bit is just for BSP. It may have no functionality issue as all processors may have same bit value in a great possibility. But for good practice, the code should get CPUID_THERMAL_POWER_MANAGEMENT in ClockModulationSupport (executed by all processors), and then use them in ClockModulationInitialize() for all processors. We can see that Aesni.c (and others) have used this good practice. 2. Current code uses 3 CPU_REGISTER_TABLE_WRITE_FIELD for MSR_IA32_CLOCK_MODULATION in ClockModulationInitialize(), they can be reduced to 1 CPU_REGISTER_TABLE_WRITE64 by getting MSR_IA32_CLOCK_MODULATION for all processors in ClockModulationSupport() and then update fields for register table write in ClockModulationInitialize(). We may argue that there may be more times of MSR_IA32_CLOCK_MODULATION getting. But actually the times of MSR_IA32_CLOCK_MODULATION getting could be also reduced. The reason is in ProgramProcessorRegister() of CpuFeaturesInitialize.c, AsmMsrBitFieldWrite64 (AsmReadMsr64 + AsmWriteMsr64) will be used for CPU_REGISTER_TABLE_WRITE_FIELD, and AsmWriteMsr64 will be used for CPU_REGISTER_TABLE_WRITE64. The times of MSR accessing could be reduced with this patch. Without the patch: 3 CPU_REGISTER_TABLE_WRITE_FIELD (in ClockModulationInitialize) ==> 3 AsmMsrBitFieldWrite64 ==> 3 AsmReadMsr64 + 3 AsmWriteMsr64 With the patch: 1 AsmReadMsr64 (in ClockModulationSupport) + 1 CPU_REGISTER_TABLE_WRITE64 (in ClockModulationInitialize) ==> 1 AsmWriteMsr64 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg CpuCommFeaturesLib: Fix ASSERT if LMCE is supportedStar Zeng2019-06-062-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1829 There will be ASSERT if LMCE is supported as below. DXE_ASSERT!: [CpuFeaturesDxe] XXX\UefiCpuPkg\Library\CpuCommonFeaturesLib\MachineCheck.c (342): ConfigData != ((void *) 0) The code should get Config Data and FeatureControlGetConfigData could be used. This issue is there since the code was added at the commit below. Revision: 3d6275c1137c9633ce24e31522b71105367bd6a0 Date: 2017/8/4 8:46:41 UefiCpuPkg CpuCommonFeaturesLib: Enable LMCE feature. The commits below are also related to move the code. Revision: 023387144299741d727521b425ef443438aecc1f Date: 2017/9/1 10:12:38 UefiCpuPkg/Lmce.c Remove useless file. Revision: 306a5bcc6b0170d28b0db10bd359817bb4b1db9f Date: 2017/8/17 11:40:38 UefiCpuPkg/CpuCommonFeaturesLib: Merge machine check code to same file. So, the code may not be tested at all on a platform that supports LMCE. BTW: A typo in LmceInitialize is also fixed. The typo is introduced by the commit below. Revision: d28daaddb3e732468e930a809d3d3943a5de9558 Date: 2018/10/17 9:24:05 UefiCpuPkg/CpuCommonFeaturesLib: Register MSR base on scope Info. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg CpuCommFeaturesLib: Fix GP fault issue about ProcTraceStar Zeng2019-06-061-32/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1808 In current code, the values of TopaEntryPtr->Uint64 for TopaTable and the values of OutputBaseReg.Uint64 and OutputMaskPtrsReg.Uint64 to register table write for RTIT_OUTPUT_BASE and RTIT_OUTPUT_MASK_PTRS are not been initialized in whole. For example, the reserved bits in OutputBaseReg.Uint64 are random that will cause GP fault like below when SetProcessorRegister (in CpuFeaturesInitialize.c) sets register based on register table. !!!! X64 Exception Type - 0D(#GP - General Protection) CPU Apic ID - 00000000 !!!! ExceptionData - 0000000000000000 RIP -0000000064D69576, CS -0000000000000038, RFLAGS -0000000000010246 RAX -000000006B9F1001, RCX -0000000000000560, RDX -0000000000000000 RBX -0000000064EECA18, RSP -000000006CB82BA0, RBP -0000000000000008 RSI -0000000080000000, RDI -0000000000000011 R8 -000000006B9493D0, R9 -0000000000000010, R10 -00000000000000FF R11 -000000006CB82A50, R12 -0000000064D70F50, R13 -0000000066547050 R14 -0000000064E3E198, R15 -0000000000000000 DS -0000000000000030, ES -0000000000000030, FS -0000000000000030 GS -0000000000000030, SS -0000000000000030 CR0 -0000000080010013, CR2 -0000000000000000, CR3 -000000006C601000 CR4 -0000000000000628, CR8 -0000000000000000 DR0 -0000000000000000, DR1 -0000000000000000, DR2 -0000000000000000 DR3 -0000000000000000, DR6 -00000000FFFF0FF0, DR7 -0000000000000400 GDTR -000000006B8CCF18 0000000000000047, LDTR -0000000000000000 IDTR -000000006687E018 0000000000000FFF, TR -0000000000000000 FXSAVE_STATE -000000006CB82800 And current code gets MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_OUTPUT_BASE and MSR_IA32_RTIT_OUTPUT_MASK_PTRS in ProcTraceInitialize() and uses their values for all processors. But ProcTraceInitialize() is only executed by BSP, that means the values just for BSP. For good practice, the code should get MSR_IA32_RTIT_CTL, MSR_IA32_RTIT_OUTPUT_BASE and MSR_IA32_RTIT_OUTPUT_MASK_PTRS in ProcTraceSupport (executed by all processors), and then use them in ProcTraceInitialize() for all processors. This can also resolve the issue that the values of OutputBaseReg.Uint64 and OutputMaskPtrsReg.Uint64 are not been initialized in whole. For TopaEntryPtr->Uint64, this patch updates code to initialize it in whole explicitly by TopaEntryPtr->Uint64 = 0 before updating its fields. At the same time, this patch also eliminates the ProcTraceSupported field in PROC_TRACE_PROCESSOR_DATA and the TopaMemArrayCount field in PROC_TRACE_DATA. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg CpuCommFeaturesLib: Disable TraceEn at the beginningStar Zeng2019-06-061-21/+21
| | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1809 Current code disables TraceEn at the end of ProcTraceInitialize(), then there will be much memory allocated even when ProcTrace feature is disabled. This patch updates code to disable TraceEn and return at the beginning of ProcTraceInitialize() when when ProcTrace feature is disabled. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Cc: Kevin Li <kevin.y.li@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg CpuCommonFeaturesLib: Remove CPU generation checkStar Zeng2019-05-181-9/+3
| | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1679 The checking to CpuInfo->CpuIdVersionInfoEcx.Bits.AESNI is enough, the checking to CPU generation could be removed, then the code could be reused by more platforms. Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
* UefiCpuPkg: Remove double \rJoe Richey2019-05-131-1/+1
| | | | | | | | | | These files have \r\n line endings, but a few lines use \r\r\n which is not a valid line ending. These lines were causing problems for git and other tools. Signed-off-by: Joe Richey <joerichey@google.com> Review-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLibUp: Add uniprocessor MpInitLibMichael D Kinney2019-04-303-0/+458
| | | | | | | | | | | | Add a new instance of the MpInitLib that is designed for uniprocessor platforms that require the use of modules that depend on the MP_SERVICES_PROTOCOL for dispatch or to retrieve information about the boot processor. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg: Replace BSD License with BSD+Patent LicenseMichael D Kinney2019-04-0996-670/+100
| | | | | | | | | | | | | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=1373 Replace BSD 2-Clause License with BSD+Patent License. This change is based on the following emails: https://lists.01.org/pipermail/edk2-devel/2019-February/036260.html https://lists.01.org/pipermail/edk2-devel/2018-October/030385.html RFCs with detailed process for the license change: V3: https://lists.01.org/pipermail/edk2-devel/2019-March/038116.html V2: https://lists.01.org/pipermail/edk2-devel/2019-March/037669.html V1: https://lists.01.org/pipermail/edk2-devel/2019-March/037500.html Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/LocalApicLib: Add GetProcessorLocation2ByApicId() APIRay Ni2019-04-082-2/+248
| | | | | | | | | | | GetProcessorLocation2ByApicId() extracts the package/die/tile/module/core/thread ID from the initial APIC ID. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Zhiqiang Qin <zhiqiang.qin@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Correct comments.Eric Dong2019-04-041-2/+2
| | | | | | | | Cc: Ray Ni <Ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Simplify PcdCpuFeaturesSupport.Eric Dong2019-04-043-32/+22
| | | | | | | | | | | | | | | | PcdCpuFeaturesSupport used to specify the platform policy about what CPU features this platform supports. This PCD will be used in IsCpuFeatureSupported only. Now RegisterCpuFeaturesLib use this PCD as an template to Get the pcd size. Update the code logic to replace it with PcdCpuFeaturesSetting. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Optimize PCDEric Dong2019-04-044-66/+24
| | | | | | | | | | | | | | PcdCpuFeaturesUserConfiguration. Merge PcdCpuFeaturesUserConfiguration into PcdCpuFeaturesSetting. Use PcdCpuFeaturesSetting as input for the user input feature setting Use PcdCpuFeaturesSetting as output for the final CPU feature setting BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Remove useless functions.Eric Dong2019-04-041-51/+1
| | | | | | | | | | Remove useless APIs, simplify the code logic. BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=1375 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/MpInitLib: Fix MemTest86 failure.Eric Dong2019-04-041-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V2 changes: Update the commit message and comments in the code. When waking vector buffer allocated by CpuDxe is tested by MemTest86 in MP mode, an error is reported because the same range of memory is modified by both CpuDxe driver and MemTest86. The waking vector buffer is not expected to be tested by MemTest86 if it is allocated out because MemTest86 only tests free memory. But current CpuDxe driver "borrows" buffer instead of allocate buffer for waking vector buffer (through allocate & free to get the buffer pointer, backup the buffer data before using it and restore it after using). With this implementation, if the buffer borrowed is not used by any other drivers, MemTest86 tool will treat it as free memory and test it. In order to fix the above issue, CpuDxe changes to allocate the buffer below 1M instead of borrowing it. But directly allocating memory below 1MB causes LegacyBios driver fails to start. LegacyBios driver allocates memory range from "0xA0000 - PcdEbdaReservedMemorySize" to 0xA0000 as Ebda Reserved Memory. The minimum value for "0xA0000 - PcdEbdaReservedMemorySize" is 0x88000. If LegacyBios driver allocate this range failed, it asserts. LegacyBios also reserves range from 0x60000 to "0x60000 + PcdOpromReservedMemorySize", it will be used as Oprom Reserve Memory. The maximum value for "0x60000 + PcdOpromReservedMemorySize" is 0x88000. LegacyBios driver tries to allocate these range page(4K size) by page. It just reports warning message if some pages are already allocated by others. Base on above investigation, one page in range 0x60000 ~ 0x88000 can be used as the waking vector buffer. LegacyBios driver only reports warning when page allocation in range [0x60000, 0x88000) fails. This library is consumed by CpuDxe driver to produce CPU Arch protocol. LagacyBios driver depends on CPU Arch protocol which guarantees below allocation runs earlier than LegacyBios driver. Cc: Ray Ni <ray.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/CpuExceptionHandlerLib:Remove.S files for IA32 and X64 archShenglei Zhang2019-04-036-1109/+0
| | | | | | | | | | | | | .nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/BaseUefiCpuLib: Remove .S files for IA32 and X64 archShenglei Zhang2019-04-033-132/+0
| | | | | | | | | | | | | .nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/SmmCpuFeaturesLib: Remove .S files for IA32 and X64 archShenglei Zhang2019-04-035-918/+0
| | | | | | | | | | | | | .nasm file has been added for X86 arch. .S assembly code is not required any more. https://bugzilla.tianocore.org/show_bug.cgi?id=1594 Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang <shenglei.zhang@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
* UefiCpuPkg/CpuCommonFeaturesLib: Aesni.c uses BIT0 and BIT1 reversedlyStar Zeng2019-03-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1621 According to Intel SDM as below, the BIT0 should be treated as lock bit, and BIT1 should be treated as disable(1)/enable(0) bit. "11b: AES instructions are not available until next RESET. Otherwise, AES instructions are available. If the configuration is not 01b, AES instructions can be mis-configured if a privileged agent unintentionally writes 11b" Cc: Laszlo Ersek <lersek@redhat.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Chandana Kumar <chandana.c.kumar@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/Microcode.c: Add verification before calculate CheckSum32Chen A Chen2019-03-061-11/+20
| | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1020 Should make sure the TotalSize of Microcode is aligned with 4 bytes before calling CalculateSum32 function. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/Microcode: Fix InComplete CheckSum32 issueChen A Chen2019-03-011-18/+19
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1020 The Microcode region indicated by MicrocodePatchAddress PCD may contain more than one Microcode entry. We should save InCompleteCheckSum32 value for each payload. Move the logic for calculate InCompleteCheckSum32 from the outsize of the do-while loop to the inside. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: restore strict page attributes via #DB in nonstop mode onlyJian J Wang2019-03-012-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1576 The root cause of this issue is that non-stop mode of Heap Guard and NULL Detection set TF bit (single-step) in EFLAG unconditionally in the common handler in CpuExceptionLib. If PcdCpuSmmStaticPageTable is FALSE, the SMM will only create page table for memory below 4G. If SMM tries to access memory beyond 4G, a page fault exception will be triggered and the memory to access will be added to page table so that SMM code can continue the access. Because of above issue, the TF bit is set after the page fault is handled and then fall into another DEBUG exception. Since non-stop mode of Heap Guard and NULL Detection are not enabled, no special DEBUG exception handler is registered. The default handler just prints exception context and go into dead loop. Actually EFLAGS can be changed in any standard exception handler. There's no need to do single-step setup in assembly code. So the fix is to move the logic to C code part of page fault exception handler so that we can fully validate the configuration and prevent TF bit from being set unexpectedly. Fixes: dcc026217fdc363f55c217039fc43d344f69fed6 16b918bbaf51211a32ae04d9d8a5ba6ccca25a6a Test: - Pass special test of accessing memory beyond 4G in SMM mode - Boot to OS with Qemu emulator platform (Fedora27, Ubuntu18.04, Windows7, Windows10) Cc: Eric Dong <eric.dong@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Jian J Wang <jian.j.wang@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/ExceptionLib: Add CET support.Jiewen Yao2019-02-284-8/+12
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1521 Add information dump for Control Protection exception. Cc: Eric Dong <eric.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/Microcode: Fix incorrect checksum issue for extended tableChen A Chen2019-02-211-9/+73
| | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1020 The following Microcode payload format is define in SDM spec. Payload: |MicrocodeHeader|MicrocodeBinary|ExtendedHeader|ExtendedTable|. When we verify the CheckSum32 with ExtendedTable, we should use the fields of ExtendedTable to replace corresponding fields in MicrocodeHeader, and then calculate the CheckSum32 with MicrocodeHeader+MicrocodeBinary. This patch already verified on ICL platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chen A Chen <chen.a.chen@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Cc: Zhang Chao B <chao.b.zhang@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/MtrrLib: Fix a bug that may wrongly set memory <1MB to UCRuiyu Ni2019-02-191-41/+18
| | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1481 Today's MtrrLib contains a bug, for example: when the original cache setting is WB for [0xF_0000, 0xF_8000) and, a new request to set [0xF_0000, 0xF_4000) to WP, the cache setting for [0xF_4000, 0xF_8000) is reset to UC. The reason is when MtrrLibSetBelow1MBMemoryAttribute() is called the WorkingFixedSettings doesn't contain the actual MSR value stored in hardware, but when writing the fixed MTRRs, the code logic assumes WorkingFixedSettings contains the actual MSR value. The new fix is to change MtrrLibSetBelow1MBMemoryAttribute() to calculate the correct ClearMasks[] and OrMasks[], and use them directly when writing the fixed MTRRs. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ray Ni <ray.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Replace AcquireSpinLock.Eric Dong2019-01-151-2/+7
| | | | | | | | | | | | | | | In AcquireSpinLock function, it may call GetPerformanceCounter which final calls PeiService table. This code may also been used by AP but AP should not calls PeiService. This patch update code to avoid use AcquireSpinLock function. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Cc: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Avoid AP calls PeiService.Eric Dong2019-01-144-78/+99
| | | | | | | | | | | | | | | | | | | | | | | | | V3: Define union to specify the ppi or protocol. V2: 1. Initialize CpuFeaturesData->MpService in CpuInitDataInitialize and make this function been called at the begin of the initialization. 2. let all other functions use CpuFeaturesData->MpService install of locate the protocol itself. V1: GetProcessorIndex function calls GetMpPpi to get the MP Ppi. Ap will calls GetProcessorIndex function which final let AP calls PeiService. This patch avoid GetProcessorIndex call PeiService. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Enhance debug message.Eric Dong2019-01-141-6/+11
| | | | | | | | | | Enhance debug message format to let them easy to read. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1411 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
* UefiCpuPkg: Merge StuffRsb.inc files into one in UefiCpuPkg/IncludeHao Wu2019-01-026-114/+4
| | | | | | | | | | | | | | | | | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=1091 Previously, when compiling NASM source files, BaseTools did not support including files outside of the NASM source file directory. As a result, we duplicated multiple copies of "StuffRsb.inc" files in UefiCpuPkg. Those INC files contain the common logic to stuff the Return Stack Buffer and are identical. After the fix of BZ 1085: https://bugzilla.tianocore.org/show_bug.cgi?id=1085 The above support was introduced. Thus, this commit will merge all the StuffRsb.inc files in UefiCpuPkg into one file. The merged file will be named 'StuffRsbNasm.inc' and be placed under folder UefiCpuPkg/Include/. Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
* UefiCpuPkg/CpuExceptionHandlerLib: Fix spelling issueMike Maslenkin2018-12-215-5/+5
| | | | | | | | | | *Excpetion* should be *Exception* Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Mike Maslenkin <mike.maslenkin@gmail.com> CC: Eric Dong <eric.dong@intel.com> CC: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
* UefiCpuPkg/CommonFeature: Always set FEATURE_CONTROL.Lockedk2-stable201811Ruiyu Ni2018-11-141-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1305 The patch reverts commit 1ed6498c4a0210204bf4b95cc0c0cd6623ad6a0b * UefiCpuPkg/CommonFeature: Skip locking when the feature is disabled FEATURE_CONTROL.Lock bit is controlled by feature CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER. The commit 1ed649 fixes a bug that when the feature is disabled, the Lock bit is cleared. But it's a security hole if the bit is cleared when booting OS. We can argue that platform needs to make sure the value of PcdCpuFeaturesUserConfiguration should be set properly to make sure feature CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER is enabled. But it's better to guarantee this in the generic core code. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif.lindholm@linaro.org> Cc: Michael D Kinney <michael.d.kinney@intel.com>
* UefiCpuPkg/RegisterCpuFeaturesLib: Separate semaphore container.Eric Dong2018-11-112-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current implementation, core and package level sync uses same semaphores. Sharing the semaphore may cause wrong execution order. For example: 1. Feature A has CPU_FEATURE_CORE_BEFORE dependency with Feature B. 2. Feature C has CPU_FEATURE_PACKAGE_AFTER dependency with Feature B. The expected feature initialization order is A B C: A ---- (Core Depends) ----> B ---- (Package Depends) ----> C For a CPU has 1 package, 2 cores and 4 threads. The feature initialization order may like below: Thread#1 Thread#2 Thread#3 Thread#4 [A.Init] [A.Init] [A.Init] Release(S1, S2) Release(S1, S2) Release(S3, S4) Wait(S1) * 2 Wait(S2) * 2 <------------------------------- Core sync [B.Init] [B.Init] Release (S1,S2,S3,S4) Wait (S1) * 4 <----------------------------------------------------- Package sync Wait(S4 * 2) <- Core sync [B.Init] In above case, for thread#4, when it syncs in core level, Wait(S4) * 2 isn't blocked and [B.Init] runs. But [A.Init] hasn't run in thread#3. It's wrong! Thread#4 should execute [B.Init] after thread#3 executes [A.Init] because B core level depends on A. The reason of the wrong execution order is that S4 is released in thread#1 by calling Release (S1, S2, S3, S4) and in thread #4 by calling Release (S3, S4). To fix this issue, core level sync and package level sync should use separate semaphores. In above example, the S4 released in Release (S1, S2, S3, S4) should not be the same semaphore as that in Release (S3, S4). Related BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1311 Cc: Laszlo Ersek <lersek@redhat.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong <eric.dong@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com> Acked-by: Laszlo Ersek <lersek@redhat.com>
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