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* UefiPayloadPkg: Parse PCI RB Segment info when its available in FDTAjan Zhong2025-03-131-36/+38
| | | | | | | | | | | | | When FDT based DTB is parsed, variables mPciRootBridgeInfo and mUplPciSegmentInfoHob are always dereferenced. If there is no PCI RB Bridge info or RB Segment info provided in FDT, it leads to NULL pointer dereferenced. To address this issue, parse PCI RB and Segment information only when they are available at FDT. If they are unavailable, skip it and allow the PciBusDxe and PciHostBridgeDxe to handle them. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg: Add AARCH64 supportAmos Bu2025-02-242-0/+5
| | | | | | | | | | | | | | | | | | | Add basic support for FIT image on the AARCH64 architecture, reuse exsitting DSC and FDF files for IA32, X64 and AARCH64 architectures. Introduce new PCD: PcdUseUniversalPayloadSerialPort to indicate which serial port module is used due to some serial port parameters are fixed for ARM SoC and Platform. Please use following command to build AARCH64 UPL FIT image: " export GCC5_AARCH64_PREFIX=aarch64-linux-gnu- python UefiPayloadPkg/UniversalPayloadBuild.py -a AARCH64 -t GCC5 -b DEBUG --Fit " Signed-off-by: Amos Bu <amos.bu@newfw.com> Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadpkg Add Missing part backLinus Liu2024-12-301-0/+8
| | | | | | Add back reg attribute of pcirootbridge Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg ：Update RetrieveMultiSegmentInfoFromHobLinus Liu2024-12-301-13/+66
| | | | | | | | | Merge the PCI root bridge with the same segment address within one. PciSegment element. UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAcpiBoardInfo.c Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Align base address for ACPI regionAjan Zhong2024-12-251-1/+8
| | | | | | | | | | | | In platform which support ACPI 2.0 only, the base address of ACPI region is not page aligned. This unalinged base address leads to failure at BuildMemoryAllocationHob when parsing ACPI node in FdtParserLib, before building gUniversalPayloadAcpiTableGuid GUID HOB. Align base address of ACPI region down to EFI_PAGE_SIZE to make sure base address always aligned. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg: Set PixelsPerScanLine property in GraphicInfo HOBAjan Zhong2024-12-241-0/+3
| | | | | | | | | | | | PixelsPerScanLine is required in some UEFI capable OS distribution. To align with simple-framebuffer definition in kernel Documentation: devicetree/bindings/display/simple-framebuffer.txt, no property node will be introduced for PixelsPerScanLine. Set value of PixelsPerScanLine to HorizontalResolution, as they are identical in most cases. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg: Fix the issue detected by UncrustifyGuo Dong2024-12-191-44/+48
| | | | Signed-off-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Enhance Universal payload serial port nodeGuo Dong2024-12-191-33/+77
| | | | | | | | | | Current implementation only supports serial port sub-node under PCI root bridge node. This enhancement support serial port node regardless it is under root node or PCI root bridge node using a single FDT passing function. Signed-off-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Update FDT parser logic for unaligned data accessAjan Zhong2024-12-092-10/+10
| | | | | | | | If alignment check is enabled in AARCH64 platform, FDT parser might dereference non-aligned 64-bit address to fetch 64-bit data. Use unaligned data read to avoid triggering unaligned data access. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg: Add AARCH64 support on FdtParserLibAjan Zhong2024-12-091-2/+2
| | | | | | Add AARCH64 support on FdtParserLib. Signed-off-by: Ajan Zhong <ajan.zhong@newfw.com>
* UefiPayloadPkg ：ACPI memory nodeLinus Liu2024-10-311-1/+22
| | | | | | | | | There are couples of gUniversalPayloadAcpiTableGuid in payload , only build one gUniversalPayloadAcpiTableGuid hob and acpi memory hob. when the reserved memory address matched the rsdp. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg：Add SMBIOS node.Linus Liu2024-10-314-25/+54
| | | | | | | Per other platform request , need to add SMBIOS device node into FDT. In the current phase(1) , only supporting SM3EntryPoint structure. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Modify PCI root reg .Linus Liu2024-10-311-4/+14
| | | | | | | Per Spec updated , update DMA Reg property filed with each root bridge bus base and its bus limit. Signed-off-by: Linus Liu <linus.liu@intel.com>
* MdePkg: consistently use "Property" in BaseFdtLibLeif Lindholm2024-10-021-52/+52
| | | | | | | | | | | There is currently a mix on functions named as Prop or Property. The latter is in majority, and the better fit for tianocore coding style, so rename FdtNodeOffsetByPropValue () and FdtSetProp () for consistency. To avoid breaking bisect, change existing users in UefiPayloadPkg. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
* MdePkg,UefiPayloadPkg: improve BaseFdtLib memreserve helper styleLeif Lindholm2024-10-021-2/+2
| | | | | | | | | | | | | | | | | | FdtNumRsv and FdtGetMemRsv were added for the benefit of UefiPayloadPkg, but their naming matches neither upstream libfdt nor tianocore coding style rules. And there was scope for improvement of the doxygen descriptions as well. These functions currently have only one in-tree user, UefiPayloadPkg FdtParserLib. So rename them more conformant FdtGetNumberOfReserveMapEntries and FdtGetReserveMapEntry and update the description comment blocks, at the same time as updating the existing user. Continuous-integration-options: PatchCheck.ignore-multi-package Signed-off-by: Leif Lindholm <quic_llindhol@quicinc.com>
* UefiPayloadPkg: Move FADT check to consumer coode.Chasel Chiu2024-09-162-0/+7
| | | | | | | | | | | | | | | | | | | ACPI FADT HW register interface fields are optional but current UPL common entry code made it as mandatory which caused compatibility issue on some platforms. Solution is to move those FADT HW register fields check code to consumer code so only ASSERT when those fields are consumed with error. Currently only AcpiTimerLib and ResetSystemLib consuming those register fields so if platforms configured UPL to different library instances the FADT HW register fields are not consumed thus will not cause ASSERT. Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiPayloadPkg: Handle simple reserved ranges from DTDhaval2024-09-141-0/+13
| | | | | | | DT has a way to provide reserved images in a simpler tabular manner. UPL should be able to support that. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Add support for Root bridge parserDhaval2024-09-144-41/+276
| | | | | | | | | | | | | | | | | | | | | In order to properly enable multisegment RB, we need to grab ecam data from the FDT for each bridge. Current UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES struct from MdeModulePkg does not include definition for ecam. In order to maintain backward compatibility and also avoid diverging too much from core, we are going to define a new HOB for UPL segment information and pass it to GetPciSegmentInfo function. Ths function then grabs specifically ecam info from the segment hob along with other rb specific information to create final RB info required by multi segment PCI driver. Additionally we would like to support legacy implementations which rely on ACPIBoard HOB to fill up segment info. So if UplSegmentInfo Hob is not found we try and look for other hob. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com> Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
* UefiPayloadPkg: Add support for Special Purpose memoryDhaval2024-09-141-0/+5
| | | | | | | | | We need to let UEFI know that there are cetain memory types which are special purpose (CXL/HBM) etc and we may want to avoid using them for UEFI purposes. Hence UPL needs to know about such memory types. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UniversalPayload: Add RISC-V support for UPL PCDsDhaval2024-09-142-2/+2
| | | | | | Expose UPL required PCDs for RISC-V Arch Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Parse fdt and create smbios tableDhaval2024-09-141-11/+23
| | | | Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Bugfix: Do not parse NULL nodesDhaval2024-09-141-0/+2
| | | | | | | Not every node has compatible property; avoid parsing nodes which return NULL. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Handle ordering issue with option nodeDhaval2024-09-141-3/+6
| | | | | | | | | | Option node provides info that is to be consumed by during metadata creation for other nodes like root bridge; pci-enum-done etc. Handle that dependency by storing option values in a variable and then apply it during post processing. Ideally such cross node dependency should be avoided in design. Scope for futher improvements. Signed-off-by: Dhaval Sharma <dhaval@rivosinc.com>
* UefiPayloadPkg: Add FDT Paser relative LIBs.Linus Liu2024-08-2810-0/+2621
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Add FDTParser and CustomFdtNodePaser to retrive all FDT node and create the relate hobs. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: Support Debug function when Hob was not available.Linus Liu2024-08-287-6/+95
| | | | | | | | | REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4786 Initialize mUartInfo with PCD for debug message when Hob was not available. Signed-off-by: Linus Liu <linus.liu@intel.com>
* UefiPayloadPkg: CbParseLib: Fix integer overflowPatrick Rudolph2024-01-221-1/+1
| | | | | | | | | | | | | | | | | | The IMD entry uses the 32bit start field as relative offset to root. On Ia32X64 this works fine as UINTN is also 32 bit and negative relative offsets are properly calculated due to an integer overflow. On X64 this doesn't work as UINTN is 64 bit and the offset is no longer subtracted, but it's added to the root. Fix that by sign extending the start field to 64 bit. Test: Booting UefiPayloadPkg still works on Ia32X64 and now also works on X64. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
* UefiPayloadPkg/Hob: Integer Overflow in CreateHob()Gua Guo2024-01-161-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4166 Fix integer overflow in various CreateHob instances. Fixes: CVE-2022-36765 The CreateHob() function aligns the requested size to 8 performing the following operation: ``` HobLength = (UINT16)((HobLength + 0x7) & (~0x7)); ``` No checks are performed to ensure this value doesn't overflow, and could lead to CreateHob() returning a smaller HOB than requested, which could lead to OOB HOB accesses. Reported-by: Marc Beatove <mbeatove@google.com> Cc: Guo Dong <guo.dong@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Cc: John Mathew <john.mathews@intel.com> Authored-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Gua Guo <gua.guo@intel.com>
* UefiPayloadPkg: Integrate UiApp and BootManagerMenuApp into MultiFvMarsX Lin2023-07-112-59/+0
| | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4347 To put UiApp.inf and BootManagerMenuApp.inf to proper FV(BDSFV) Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: MarsX Lin <marsx.lin@intel.com>
* UefiPayloadPkg: Fix boot shell issue for universal UEFI payloadGuo Dong2023-05-152-9/+78
| | | | | | | | | | | | | | | | | After moving BDS driver to a new FV for universal UEFI payload, the shell boot option path is not correct since it used the BDS FV instead of DXE FV in its device path. This patch would find the correct FV by reading shell file. It also removed PcdShellFile by using gUefiShellFileGuid. Signed-off-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: Mike Maslenkin <mike.maslenkin@gmail.com>
* UefiPayloadPkg: Fix issues when MULTIPLE_DEBUG_PORT_SUPPORT is truePaytonX Hsieh2023-05-023-1/+111
| | | | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4427 1. Since UART speed is slower than CPU, BIOS need to check the write buffer is empty, to avoid overwrite the buffer content. 2. LPSS UART might disable MMIO space for Windows debug usage during ExitBootServices event. BIOS need to avoid access the MMIO space after ExitBootServices. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: PaytonX Hsieh <paytonx.hsieh@intel.com>
* UefiPayloadPkg: Update code to be more C11 compliant by using __func__Rebecca Cran2023-04-101-2/+2
| | | | | | | | | | | | | | __FUNCTION__ is a pre-standard extension that gcc and Visual C++ among others support, while __func__ was standardized in C99. Since it's more standard, replace __FUNCTION__ with __func__ throughout UefiPayloadPkg. Signed-off-by: Rebecca Cran <rebecca@bsdio.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Gua Guo <gua.guo@intel.com> Reviewed-by: James Lu <james.lu@intel.com>
* UefiPayloadPkg: remove the change that get platform specific logicMarsX Lin2023-02-232-28/+0
| | | | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4241 Since UefiPayloadPkg had supported multiple firmware volume, remove the platform specific logic via protocol Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: Gua Guo <gua.guo@intel.com> Reviewed-by: James Lu <james.lu@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Signed-off-by: MarsX Lin <marsx.lin@intel.com>
* UefiPayloadPkg: Fix debug print error level hob not save correctNing Feng2023-01-101-1/+1
| | | | | | | | | | | | | REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4264 Fix debug print error level hob not save correct DebugPrintErrorlevel Should cover the case: Header.Length == UNIVERSAL_PAYLOAD_SIZEOF_THROUGH_FIELD () Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Cc: Gua Guo <gua.guo@intel.com> Signed-off-by: Ning Feng <ning.feng@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com>
* UefiPayloadPkg/SerialPortLib: Enhance multi port behaviourKavya2022-12-201-6/+35
| | | | | | | | | | | | | | Add condition to return success if mUartCount is greater than zero in SerialPortInitialize() to avoid filling mUartInfo with the same hob data when SerialPortInitialize() is called multiple times. Also add proper conditions in SerialPortRead function to read the data properly from multiple UART's. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: Kavya <k.kavyax.sravanthi@intel.com>
* UefiPayloadPkg: Implement a new SerialPortLib instanceKavya2022-09-072-0/+854
| | | | | | | | | | | | | Add new Serial port library instance that consumes the HOB defined in MdeModulePkg/Include/UniversalPayload/SerialPortInfo.h to support multiple UART's. Reviewed-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Cc: James Lu <james.lu@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: Kavya <k.kavyax.sravanthi@intel.com>
* UefiPayloadPkg: Fix Coverity report defectJames Lu2022-08-231-2/+2
| | | | | | | | | | https://bugzilla.tianocore.org/show_bug.cgi?id=4018 Coverity report FORWARD_NULL and OVERFLOW_BEFORE_WIDEN potential defect in UefiPayloadPkg. Signed-off-by: Gregx Yeh <gregx.yeh@intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Reviewed-by: James Lu <james.lu@intel.com>
* UefiPayloadPkg: Return PciRootBridges instead of NULLKavya2022-08-231-2/+2
| | | | | | | | | | Return PciRootBridges instead of NULL and set PcdPciDisableBusEnumeration to FALSE when root bridge count is zero. Reviewed-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Gua Guo <gua.guo@intel.com> Signed-off-by: Kavya <k.kavyax.sravanthi@intel.com>
* UefiPayloadPkg: Add a Macro to enable Boot LogoSean Rhodes2022-08-032-0/+10
| | | | | | | | | Add a macro called BOOTSPLASH_IMAGE, which when enabled, will display a logo at boot time. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems>
* UefiPayloadPkg/PlatformBootManagerLib: Correct spacing in boot promptSean Rhodes2022-08-031-1/+1
| | | | | | | | Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems>
* UefiPayloadPkg: Add support for logging to CBMEM consoleBenjamin Doron2022-07-272-0/+293
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Writes TianoCore debug logs into the CBMEM console ringbuffer, from where the user can retrieve them with the `cbmem` userspace utility. The intention is to aid in debugging non-fatal issues even in release builds, or simply make TianoCore's logs available to those interested. Consequently, MDEPKG_NDEBUG must be masked. As an in-memory debug logging library, ASSERTs must be non-fatal to be seen, so they neither dead-loop nor create a breakpoint. It is assumed that ASSERT() neither enforces fatal conditions nor security integrity, as release builds do not call DebugAssert() from the ASSERT macro. More detailed debug logs are produced with the DEBUG_CODE macro, but this guards other debug-related code throughout the codebase. To avoid changing behaviour on release builds, this is only set for debug builds. Tested on QEMU, dumping the appropriate memory region in the UEFI shell shows the TianoCore log. An improved revision of the debug library used in several coreboot-related EDK2 forks, including MrChromebox's. Previous revisions also tested on an Acer Aspire VN7-572G laptop. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
* UefiPayloadPkg/PlatformBootManagerLib: Evenly space boot promptSean Rhodes2022-07-161-4/+4
| | | | | | | | | | | | | Add 4 spaces before the boot prompt "F2 or Down..." so that the spacing is equadistant from the top, which is spaced with a `\n`, and the left. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Connect all root bridge in PlatformBootManagerBeforeConsoleLiu, Zhiguang2022-05-132-35/+15
| | | | | | | | | | | | Some ConIn or ConOut device may not in the first root bridge, so connect all root bridge before detect ConIn and ConOut device. Reviewed-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Add Serial IO device path according to related protocolLiu, Zhiguang2022-05-133-107/+41
| | | | | | | | | | | | | | Current code follow some rules to check if the PCI device connected to a serial port device, but some platform or hardware doesn't follow such rule. By locating gEfiSerialIoProtocolGuid protocol, we can find the related device path. Reviewed-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Simplify code logicLiu, Zhiguang2022-05-132-73/+25
| | | | | | | | | | | | | | | A little overdesign about VisitAllPciInstances function, since there are two call back functions. Simplify the code logic by combining the two call back functions, and unused parameters. Change the PROTOCOL_INSTANCE_CALLBACK to SIMPLE_PROTOCOL_INSTANCE_CALLBACK because the former is also defined in OvmfPkg. Rename it to avoid confusion. Reviewed-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
* UefiPayloadPkg: Fix PciHostBridgeLibLean Sheng Tan2022-04-101-4/+9
| | | | | | | | | | | | | | | | | | | | | Don't assume a 64bit register always holds an address greater than 4GB. Check the value in the register and decide which Aperature it should be assigned to. Fixes assertion "ASSERT [PciHostBridgeDxe] Bridge->MemAbove4G.Base >= 0x0000000100000000ULL". Tested with coreboot as bootloader on platforms that have PCI resource above 4GiB and on platforms that don't have resource above 4GiB. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by Sean Rhodes <sean@starlabs.systems> Reviewed-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Add a new DebugPrintErrorLevelLib instanceXie, Yuanhao2022-04-032-0/+119
| | | | | | | | | | | | | | It consumes the HOB defined in UefiPayloadPkg/Include/Guid/DebugPrintErrorLevel.h, and allow bootloader to config DebugPrintErrorLevel. Cc: Guo Dong <guo.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Cc: Sean Rhodes <sean@starlabs.systems> Signed-off-by: Yuanhao Xie <yuanhao.xie@intel.com>
* UefiPayloadPkg/Library/PlatformBootManagerLib: Remove broken VGA detectionPatrick Rudolph2022-03-291-9/+9
| | | | | | | | | | | | | | | | | This fixes an issue where the framebuffer provided by coreboot or slimbootloader will only work on the primary VGA device. If the framebuffer corresponds to a different device the screen will stay black. In addition, the code doesn't work for multiple graphic cards, has reference to non existing functions, and is a duplication of common code. Call EfiBootManagerConnectVideoController on every display device found, not only the legacy VGA device. This is the same as OvmfPkg does. Allows to display output on the framebuffer set up by firmware, which might not be the VGA device. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Fix PciHostBridgeLibPatrick Rudolph2022-03-291-119/+18
| | | | | | | | | | | | | | | | | | | | | | | | On modern platforms with TBT devices the coreboot resource allocator opens large PCI bridge MMIO windows above 4GiB to place hotplugable PCI BARs there as they won't fit below 4GiB. In addition modern GPGPU devices have very big PCI bars that doesn't fit below 4GiB. The PciHostBridgeLib made lots of assumptions about the coreboot resource allocator that were not verified at runtime and are no longer true. Remove all of the 'coreboot specific' code and implement the same logic as OvmfPkg's ScanForRootBridges. Fixes assertion "ASSERT [PciHostBridgeDxe] Bridge->Mem.Limit < 0x0000000100000000ULL". Tested with coreboot as bootloader on platforms that have PCI resources above 4GiB and on platforms that don't have resources above 4GiB. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Guo Dong <guo.dong@intel.com> Reviewed-by: Maurice Ma <maurice.ma@intel.com>
* UefiPayloadPkg: Make Boot Manager Key configurableSean Rhodes2022-03-072-13/+32
| | | | | | | | | | | | | Provide a build option to use [Esc] instead of [F2] for devices such as Chromebooks that don't have F-keys. Cc: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Ray Ni <ray.ni@Intel.com> Reviewed-by: Guo Dong <guo.dong@intel.com>
* UefiPayloadPkg: Add missing Guid gUefiAcpiBoardInfoGuidLiu, Zhiguang2021-12-081-0/+3
| | | | | | | | | | The library PciSegmentInfoLibAcpiBoardInfo consumes the Guid gUefiAcpiBoardInfoGuid. Reviewed-by: Guo Dong <guo.dong@intel.com> Cc: Ray Ni <ray.ni@intel.com> Cc: Maurice Ma <maurice.ma@intel.com> Cc: Benjamin You <benjamin.you@intel.com> Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-05 08:11:59 +0000