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* Add support for Winbond W25X05CLJacob Appelbaum2020-07-262-0/+33
| | | | | | | | | | | | | | This commit adds support for the Winbond W25X05CL SPI flash chip. The Winbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors. I have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL flash chip using a test clip. Reading, erasing, and writing all function as expected. Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc Signed-off-by: Jacob Appelbaum <jacob@appelbaum.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* meson: fix compilation under uClibc-ngRosen Penev2020-07-211-1/+1
| | | | | | | | | | | | | | | fileno requires _POSIX_C_SOURCE to only be defined. nanosleep requires _POSIX_C_SOURCE to be defined to 199309L. strndup requires _POSIX_C_SOURCE to be defined to 200809L. Change-Id: Idb80937bb78e173eb03f2a0c0cdd8925fcd7bfa1 Signed-off-by: Rosen Penev <rosenp@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43599 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* endiantest: Fix #if expressionDavid Hendricks2020-07-211-1/+1
| | | | | | | | | | | | | | | | | | Without this, `gcc -E endiantest.c` can fail and return the incorrect endiannes as well as exiting with non-zero. Here is the actual error shown in the output: endiantest.c:2:31: error: #if with no expression #if __FLASHROM_LITTLE_ENDIAN__ I was able to reproduce this using gcc-6.3.0 and clang-4.0.1, but newer compilers didn't have this issue. Change-Id: Iba2febd861471ec821a494336e800c2564984332 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug_spi: add param for a custom reset setupMary Ruthven2020-07-211-12/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GSC firmware asserts EC_RST_L before programming the AP with raiden_debug:target=AP.Some Chromium devices don't power the AP flash when the EC is in reset. These boards can't flash the AP with the current CCD behavior. This change adds a custom_rst raiden_debug param to tell Cr50 not to assert EC_RST_L or touch any reset signals while flashing the AP. Users will need to configure the reset signals before running the flashrom command. BUG=b:154885210 BRANCH=none TEST=manual flashrom -p raiden_debug:target=EC -r ec.bin flashrom -p raiden_debug:target=AP -r ap.bin flashrom -p raiden_debug:target=AP,custom_rst=true -r ap.bin flashrom -p raiden_debug:target=AP,custom_rst=inv -r ap.bin flashrom -p raiden_debug -r base.bin Signed-off-by: Mary Ruthven <mruthven@chromium.org> Change-Id: I2da26469120c5304bc129b5578fcb7ca805fc1d1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43527 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi: add missing USB_SPI requestsMary Ruthven2020-07-211-4/+11
| | | | | | | | | | | | | | | Add the missing USB_SPI requests from platform/cr50 BUG=none BRANCH=none TEST=none Signed-off-by: Mary Ruthven <mruthven@chromium.org> Change-Id: I49c0c28566ed36af6fa03e23a878d19462c55f70 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43525 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Brian Nemec <bnemec@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug_spi.c: Add support for USB SPI protocol V2Brian J. Nemec2020-07-211-12/+672
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the USB SPI V2 protocol and its documentation. The protocol version number uses the bInterfaceProtocol field in USB to identify which device to use, this enables us to support both V1 and V2 with the same host. The USB SPI V2 protocol adds the ability to perform multi-packet USB SPI transfers. This results in fewer USB messages exchanged, larger SPI transfers, and faster flashing speeds. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami with a USB SPI V1 protocol device TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami with a USB SPI V2 protocol device TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Ie356c63b521c0cc11a4946ffac128ec7139f0bec Reviewed-on: https://review.coreboot.org/c/flashrom/+/41533 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Add protocol based configuration to initBrian J. Nemec2020-07-211-28/+105
| | | | | | | | | | | | | | | | | | | | | | Add a configuration stage to the initialization. This enables us to dynamically set the maximum SPI write and read limits based on the device we are connected to and switch the command function. These changes will enable us to have larger SPI transfers in protocol V2 and separate out the logic flow used for the different protocols. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Id404af14e55fa0884e29f28880206aaad4deba66 Reviewed-on: https://review.coreboot.org/c/flashrom/+/41532 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Add USB context states and helper functionsBrian J. Nemec2020-07-201-67/+207
| | | | | | | | | | | | | | | | | | | | | | | | Add context states to handle the USB packets, these allow us to simplify the process of loading data from the transmit buffer into a USB packets' data section and from a USB packet to it's receive buffers. These will also keep track of the size of the USB packet allowing a simpler interface to transmit them. Helper functions have been added to help with copying data between the transmit and receive context states to and from the USB packets. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Id7b598b39923b4b8c1b6905e5d5c5a2be4078f96 Reviewed-on: https://review.coreboot.org/c/flashrom/+/43550 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* raiden_debug_spi.c: Add transfer context statesBrian J. Nemec2020-07-201-32/+67
| | | | | | | | | | | | | | | | | | | | Add context states to handle the read and write buffers as transmit and receive states. These are used to keep track of the number of bytes transmitted and received allowing future support of multi-packet messages in the v2 protocol and easier integration with a unified USB packet context. BUG=b:139058552 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: Ic6eea82ffc604ec56278f7aaa0deafe0cf75973c Reviewed-on: https://review.coreboot.org/c/flashrom/+/41608 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Clean up the USB SPI protocolBrian J. Nemec2020-07-201-64/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Perform some clean up the USB SPI protocol 1 prior to adding protocol 2 to improve consistency and correct minor issues. * Minor clean up the comments descriptor for the protocol. This adds the location of another relevant file, corrects the omission of one of the protocol modes, makes the direction of the packets explicit, and minor formatting changes. * Fix typos in constants associated with the retry mechanism. * Clean declarations to match the EC code formats. * Updates the error message formatting so protocol V1 closely matches the V2 protocol for consistency. * Minor changes to the structure, moving validation of the arguments earlier in the transfer. Overall to keep V1 and V2 closer aligned and reduce future changes in the V1 code. BUG=b:139058552 BRANCH=none TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: I17e62dabee2724eecf8d5a1a7827f06f0c7514df Reviewed-on: https://review.coreboot.org/c/flashrom/+/41597 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Rename Protocol V1 specific fieldsBrian J. Nemec2020-07-201-20/+24
| | | | | | | | | | | | | | | Rename the structures from the USB SPI which are specific to the V1 protocol. BUG=b:139058552 BRANCH=none TEST=Builds Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Change-Id: I70b43af50d872d850dae287d99bcd768107a1cad Reviewed-on: https://review.coreboot.org/c/flashrom/+/41596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* ichspi.c: Make ich_init_spi() parameteric on spibarEdward O'Callaghan2020-07-161-27/+27
| | | | | | | | | | | | The ich_init_spi() function takes spibar as a parameter and sets the global ich_spibar with it but then uses the global symbol instead of using the parameter directly. Change-Id: Id809c33d8a4074acbee8e1cd8e3b7b00ce0cb3ec Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make pprinters parametric on ich_generationEdward O'Callaghan2020-07-161-16/+17
| | | | | | | | | | | | | | | Make the two prettyprint functions pure by taking the ich_generation value as a function parameter over a global variable: * prettyprint_ich9_reg_hsfs() * prettyprint_ich9_reg_hsfc() Change-Id: I5d4fb012c6b9b843ac30c1fe2ea6fe754c545a43 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43501 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ichspi.c: Make ich_set_bbar() parameteric on ich_generationEdward O'Callaghan2020-07-161-5/+5
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_set_bbar() function pure. Change-Id: I6da6dccb413cbafa2fbaca213574f22c7a258139 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43500 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make ich_init_opcodes() parameteric on ich_generationEdward O'Callaghan2020-07-161-13/+13
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_init_opcodes() function pure. Change-Id: I68cc078cc8bc1c772f52ca3e5e12559991180210 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43499 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* ichspi.c: Make ich_init_spi() parametric on ich_generationEdward O'Callaghan2020-07-161-5/+5
| | | | | | | | | | | Work towards dropping ich_generation global usage and make the ich_init_spi() function more pure. Change-Id: I5293e7ae6f20a2299577172655c2926861091f5a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Install the man file when using meson as a buildsystemRichard Hughes2020-07-152-1/+12
| | | | | | | | | | | | This fixes a regression with the Fedora package. Change-Id: I881bd5002a842072ce9dadea033c51a2668f9e7c Signed-off-by: Richard Hughes <richard@hughsie.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38939 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: add PCI ID for APL-I (Broxton)Jan Samek2020-07-101-0/+1
| | | | | | | | | | Change-Id: I48dba541b5893551f47f3d5ed422eb1dc36f5324 Signed-off-by: Jan Samek <jan.samek@siemens.com> Signed-off-by: Henning Schild <henning.schild@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* serial: Fix file read/write error handling for WindowsDavid Hendricks2020-07-071-8/+22
| | | | | | | | | | | | | | | | | | | File read/write semantics are different between POSIX and Windows. In particular Windows file read/write functions return a boolean type to indicate success or failure, while the POSIX equivalents return a signed integer indicating number of bytes read if successful or -1 if not. This attempts to correct some error handling paths for Windows and avoid invalid comparisons that were causing compilation issues. Reported on https://github.com/flashrom/flashrom/issues/149 Change-Id: Ib179d51ede2dbd38f54f3641bfe90340a6a87e31 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43051 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* dediprog: Correct REQTYPE_OTHER_OUT macroDavid Hendricks2020-06-241-1/+1
| | | | | | | | | | | It's not used anywhere, but it should be correct if we continue to keep it in. Change-Id: I8a6941c2906dda2c5aac5e0af3364fd2ac5773f3 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tree: Remove unneeded semicolons after loopsDavid Hendricks2020-06-242-2/+2
| | | | | | | | | | Trivial cleanup Change-Id: Id93a019a39b765c70b1a4eaeb25d9b582c3e4141 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* mysteries_intel: Add a section for software vs hardware sequencingDavid Hendricks2020-06-201-0/+42
| | | | | | | | | | | This attempts to explain software sequencing, hardware sequencing, and the "Opaque flash chip". Change-Id: I2445e926aad96060f26d0bc55dd7642c1a404296 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42485 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests/spi25.c: Add unit-test coverage of spi95.cEdward O'Callaghan2020-06-173-0/+21
| | | | | | | | | | | | | | Add spi95.c unit-tests to spi25.c to avoid some clutter. BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I6de59451b82131b58114b268ff6dd0b18cd5952b Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests/: Add helper.c unit testsEdward O'Callaghan2020-06-174-0/+85
| | | | | | | | | | | | BUG=b:157280555 BRANCH=none TEST=builds Change-Id: If4a1fe7c499f51bb9d7cd48ef26caf9dfae3c1fa Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* tests/: Add flashrom.c unit testsEdward O'Callaghan2020-06-174-0/+45
| | | | | | | | | | | | BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I2d9213f98c6c9639f2417466ba4895117e8d600a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add W25Q256.Wel-coderon2020-06-162-0/+42
| | | | | | | | | | | | Nicklas Lennert wrote me via the flashrom mailing list that he successfully ran read, write and verify cmd. Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Change-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b Reviewed-on: https://review.coreboot.org/c/flashrom/+/40855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* tests/: Add spi25.c unit testsEdward O'Callaghan2020-06-164-0/+196
| | | | | | | | | | | | BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I47112952835ce2c4c773a9d90379ff8ceefaaf9a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* tests/: Add CMocka unit-test infrastructureEdward O'Callaghan2020-06-166-0/+105
| | | | | | | | | | | | | | | | This adds the CMocka unit-testing infrastructure into the meson build system which we will latter follow up with unit-tests for flashrom's core logic. BUG=b:157280555 BRANCH=none TEST=builds Change-Id: I66665f56627b3d99049176bfbebbd771b080370a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libflashrom.c: Fix indentation of a braceAngel Pons2020-05-281-1/+1
| | | | | | | | | | | | It was indented with two spaces instead of one tab. Fix it. Change-Id: I18051ae4433b267b9552a034a67d7830b9206c20 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
* libflashrom.c: Use casts on enum conversionsAngel Pons2020-05-281-2/+4
| | | | | | | | | | This allows flashrom to build with GCC 10. Change-Id: I2166cdf3681452631ef8e980face2924e9a6c81a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* Add board enable for ASUS P3B-FKeith Hui2020-05-192-1/+48
| | | | | | | | | | | With this change flashrom can detect, enable and flash on this board both under vendor BIOS and coreboot. Change-Id: I395ff50fbcda8ecdaa26033f0d99b2b0eb42f7ff Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* 82802ab.c: Remove duplicated checkAngel Pons2020-05-131-3/+3
| | | | | | | | | | Change-Id: I5d511d7ec254bdbd9926e6d8efc308fb2339cb81 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38661 Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi25: Debug flashrom crash when Write Protect is ONYuji Sasaki2020-05-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When hardware write protect is applied, flashrom crashed and generate coredump. spi_disable_blockprotect_generic() calls flash->chip->printlock() method when disable was failed, but this method is optional, can be NULL depends on type of flashrom chip. NULL pointer check before call is added to avoid crash. BRANCH=none BUG=b:129083894 TEST=Run on Mistral P2 (On CR50 console, run "wp disable") flashrom --wp-range 0 0x400000 flashrom --wp-enable (On CR50 console, run "wp enable") flashrom -r /tmp/test.bin Verify "Block protection could not be disabled!" is shown, but flash read completes. Signed-off-by: Yuji Sasaki <sasakiy@chromium.org> Change-Id: I81094ab5f16a85871fc9869a2e285eddbbbdec4e Reviewed-on: https://chromium-review.googlesource.com/1535140 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: SANTHOSH JANARDHANA HASSAN <sahassan@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40468 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* raiden_debug_spi.c: Enables USB retry for invalid write countBrian J. Nemec2020-05-081-3/+7
| | | | | | | | | | | | | | | | | | | | Enables the USB SPI transfer retry mechanism when the error code USB_SPI_WRITE_COUNT_INVALID is returned. This error code can indicate a recoverable USB transfer failure. BUG=b:153887087 BRANCH=none TEST=Manual testing of ServoMicro and Flashrom when performing reads, writes, and verification of the EC firmware on Nami. TEST=Modified ServoMicro to randomly corrupt USB packets when reading the packet length to replicate bad packets and the verify recovery is successful. Change-Id: I9e6b2ccec0b06aab0d6920f1bddf108058e5d6b1 Signed-off-by: Brian J. Nemec <bnemec@chromium.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41152 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Remove dead codeEdward O'Callaghan2020-05-071-33/+0
| | | | | | | | | | | | | | | Turns out the MST likely doesn't need these so-called defaults to be written for the purposes of spi flashing. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: Ieb938cf0805b22692d61db23795208c9be962b60 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix cmd timeout issueEdward O'Callaghan2020-05-071-8/+12
| | | | | | | | | | | | | | | | | | | | | Chip erasures take much longer than sector and bank erasures. Allow the wait loop helper to multiply the max timeout in this very specific case while quickly timeout for other ops that are expected to be shorter. V.2: Fix nonsense fall though warn-err BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -w foo (cycle).. Change-Id: I4a36aa3101827e69eb244775d25bbb476d4bb780 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix _spi_write256() as documentedEdward O'Callaghan2020-05-061-22/+50
| | | | | | | | | | | | | | | | | | | | | | | | | Turns out broken erasures highlighted some of the issues in the write256 implementation. After a fair amount of time deciphering scarce documentation details a correct implementation was finally derived. V.2: Rename 'start_program() -> execute_write()' to clarify the intention and not to overload the term 'program' since the MST actually runs a 'program' itself. BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -w foo && flashrom -p realtek_mst_i2c_spi:bus=8 -r foo && hexdump -C foo Change-Id: If61ff95697f886d3301a907b76283322c39ef5c7 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* realtek_mst_i2c_spi.c: Fix _spi_send_command cb for erasuresEdward O'Callaghan2020-05-061-9/+40
| | | | | | | | | | | | | | | | | | | | Before issuing SPI opcodes into 0x61 the top three BITS of 0x60 need to be carefully crafted. Correctly craft these in the case of SPI erasures and document this registers expectations. Clean up remaining debug comments while we are here. BUG=b:152558985,b:148745673 BRANCH=none TEST=flashrom -p realtek_mst_i2c_spi:bus=8 -E && flashrom -p realtek_mst_i2c_spi:bus=8 -r foo && hexdump -C foo Change-Id: Ib11ba8f63b11a1c5ebaa68deb7971648de8c2ecd Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* raiden_debug_spi: Fix memleakPatrick Georgi2020-05-051-1/+3
| | | | | | | | | Change-Id: Ib9d99fefda812d20265db47be353c844f8b77129 Found-by: Coverity Scan #1420204 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* spi95: Check for success before using send_command's returned dataPatrick Georgi2020-05-051-1/+4
| | | | | | | | | | | If the transfer failed, the data might be invalid. Change-Id: I3ad9daa00a54e2a3954983cec91b6685f1a98880 Found-By: Coverity Scan #1405870 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug_spi.c: Clean up global stateEdward O'Callaghan2020-05-051-15/+42
| | | | | | | | | | | | | | | | | | | | | | The Chromium flashrom fork has very poor dispatch logic whereas upstream has proper inversion of control with a generic 'data' void * member to stuff long-lived state in. Leverage the member to store the USB descriptor state in during the life-time of the spi master. V.2: Remove unnecessary indirection as is the case in commit a25c13cdb601f9d43b0f8edad96f9489efcb4b37. BUG=b:140394053 BRANCH=none TEST=builds && detects flashchip name. Change-Id: Ida9dce97fef2c6dfd68a278c879917fdd3ff7fef Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40105 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* realtek_mst_i2c_spi.c: Define some register namesEdward O'Callaghan2020-05-051-6/+14
| | | | | | | | | | | | | | | | Try to document some of the register magics with plausible names for readability. BUG=b:152558985,b:148745673 BRANCH=none TEST=builds Change-Id: I97313f6f14438e4cbfc62faa7242cf6fc271f387 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Makefile: Remove 'NEED_LIBUSB1' from lspcon requirementsEdward O'Callaghan2020-05-041-1/+0
| | | | | | | | | | | Since lspcon talks over i2c I doubt libusb is a build requirement, remove it. Change-Id: Ic4d71c10d2d8c0c881aa5732daed35c20d905a5e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/41020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* Initial Realtek MST i2c_spi supportEdward O'Callaghan2020-05-046-0/+487
| | | | | | | | | | | | | | | | | | | | | This spi master allows for programming of a Realtek RTD2142 MST with external SPI flash chip routed via its internal i2c transport mechanism. BUG=b:152558985,b:148745673 BRANCH=none TEST=echo "00000000:0004ffff fw" > layout && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* libflashrom.c: Use correct type for sizeofAngel Pons2020-05-031-1/+1
| | | | | | | | | | | | | | | As we want to allocate an array of `flashrom_board_info` structs, use that type in sizeof. This did not cause problems as `board_info` was at least as big as `flashrom_board_info`, but nothing guarantees it. Change-Id: I66e875d54c9a7cc59898b072b052282b0b5cbb2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39973 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: Spell `BIOS` in uppercaseAngel Pons2020-05-031-1/+1
| | | | | | | | | | | | Intel document #336067 uses `BIOS Control` to refer to this register. Change-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Revert "flashchips: port S25FS(128S) chip from chromiumos"Nico Huber2020-05-018-415/+6
| | | | | | | | | | | | | | | | | | | | | This reverts commit a3519561bd0fb44153bb376322b799000657576f. Breaks support for most SPI flash chips. It's too big and too invasive to be reviewed as a single commit. The changes to `spi_poll_wip():spi25.c` were not noticed in the original review that were from the similarly named function and file `s25f_poll_status():s25f.c` in the downstream Chromium fork. V.2: Rebase and rephrase commit msg to reflect how the issue slipped in. Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* lspcon_i2c_spi.c: Prefix with fn name instead of just 'Error:'Shiyu Sun2020-05-011-8/+12
| | | | | | | | | | | | | | | | | Replace log lines with the prefix formatter '%s: ..' and pass '__func__' to the printers so that errors are prefixed with the function from which they originated. BUG=b:154285774 BRANCH=none TEST=build success Change-Id: If3205d8e453cfcd37f725b4fd135fe1221c913c0 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40901 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-3026-53/+53
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* ft2232_spi.c: Improve handling of static bufferAngel Pons2020-04-251-3/+3
| | | | | | | | | | | | | | | If `buf` became NULL because of an error, subsequent calls to the `ft2232_spi_send_command` function with a smaller buffer size will result in a null pointer dereference. Add an additional null check before using `buf` to prevent that. Moreover, use `size_t` for the `bufsize` and `oldbufsize` variables, as it's what `realloc` uses. Change-Id: Idc4237ddca94c42ce2a930e6d00fd2d14e4f125c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39975 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-28 12:21:02 +0000