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* chipset_enable.c: Add Intel pch7 did=0x1e4{1,2,3} supportEdward O'Callaghan2020-11-141-0/+3
| | | | | | | | | | | | | | | | Modified to be pch7 over pch6 as per-coreboot and review comments. BUG=none BRANCH=none TEST=none Change-Id: Ic69dc024e9af0c43d6b3a8213a5dc5d2f898c447 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47090 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: check return value from rphysmap() callEdward O'Callaghan2020-10-271-0/+2
| | | | | | | | | | | Port from the ChromiumOS fork of flashrom. Change-Id: I8075fe5f80ac0da5280d2f0de6829ed3a2496476 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/46444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-0/+9
| | | | | | | | | | | | | | | | Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* chipset_enable: Mark Intel Q77 as DEPJacob Garber2020-08-291-1/+1
| | | | | | | | | | | Tested reading and writing internal flash on Dell Optiplex 9010 SFF. Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: I4717959be1b79aa986f1276589d01ce7475bda8f Reviewed-on: https://review.coreboot.org/c/flashrom/+/44910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* add PCI IDs for additional c620 series PCH chipsJonathan Zhang2020-08-271-0/+3
| | | | | | | | | | Add PCI IDs for C621A, C627A and C629A. Change-Id: I636becd9f08bdf604c6af81ce396049655353b04 Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Add support for Intel C620 Series Chipset SPI ControllerLuka Kovacic2020-08-251-0/+1
| | | | | | | | | | | | | | | | | | Support for the Intel C620 Series Chipset SPI Controller (rev 04) is added to enable SPI flash access on the following platform: - Intel Xeon D-2187NT Support for this controller was shortly tested on the platform above. The flash is recognized, some regions of the flash are locked. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Tested-by: Jakov Petrina <jakov.petrina@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: If39d9bb1acd4029f802a44a2940dd23f66ba09b1 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable: add PCI ID for APL-I (Broxton)Jan Samek2020-07-101-0/+1
| | | | | | | | | | Change-Id: I48dba541b5893551f47f3d5ed422eb1dc36f5324 Signed-off-by: Jan Samek <jan.samek@siemens.com> Signed-off-by: Henning Schild <henning.schild@siemens.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42805 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Spell `BIOS` in uppercaseAngel Pons2020-05-031-1/+1
| | | | | | | | | | | | Intel document #336067 uses `BIOS Control` to refer to this register. Change-Id: Ib66547b2b5d77658ab1925e4ad3acfe44e14843c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40857 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marcello Sylvester Bauer <sylv@sylv.io> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable.c: Disable SPI on ICH7 if booted from LPCAngel Pons2020-04-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | Commit 92d6a86 ("Refactor Intel Chipset Enables") eliminated a check to disable SPI when ICH7 has booted from LPC, as the hardware does not support it. Therefore, when flashrom probes the SPI bus, it times out waiting for the hardware to react, for each and every SPI flash chip. This results in very long delays and countless instances of the error: Error: SCIP never cleared! To prevent this, bring back part of the lost check. Probing for LPC and FWH when booted from SPI does not seem to cause any problems on desktop mainboards with ICH7, so don't disable LPC nor FWH if that is the case. Tested on ECS 945G-M4 (ICH7, boots from LPC), works without errors. Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
* chipset_enable.c: Add more Lewisburg PCH IDsAngel Pons2020-03-271-0/+8
| | | | | | | | Change-Id: I7ba768abfa6f19f23379e5f47a6bc099fc01d3da Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable: Mark Intel HM75 as DEPEvgeny Zinoviev2020-03-191-1/+1
| | | | | | | | | | Tested reading and writing on a Samsung laptop (see CB:39388). Change-Id: Idbb9c719a6f794a35293bb3b167cc1491d24d4fa Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Mark Skylake U Premium as DEPAngel Pons2020-03-191-1/+1
| | | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an Acer Aspire ES1-572 laptop with an Intel i3-6006U. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: Ib8ee9b5e811df74d2f48bd409806c72fe862bc24 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable.c: Add Ice Lake U to known and tested systemsJohanna Schander2020-02-091-0/+1
| | | | | | | | | | | | | | | | | Intel Ice Lake systems use an 495 Series Chipset that behaves compatible to pch300 chips but chip names are undocumented at this point. This change was tested in read/write/erase on the Razer Blade Stealth (late 2019) with intel 1065G7 CPU and "Ice Lake U Premium PCH". Change-Id: I6227d32f4476420cf1aeec37ebd4b7648e0b3d15 Signed-off-by: Johanna Schander <git@mimoja.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christoph Pomaska <github@slrie.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable: Add Kaby Lake U Prem. to known and tested systemsWim Vervoorn2020-01-221-1/+1
| | | | | | | | | | | | | | | | | Intel Kaby Lake U (with the 9d4e device id) support is available but marked not tested. Tested reading, writing and erasing both internal flash chips on the Facebook Monolith system with the Intel i3 7100U SoC. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Change-Id: Ie35cc896e29baffa63fe9e37c14770001b54e7ec Reviewed-on: https://review.coreboot.org/c/flashrom/+/38481 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Mark Intel HM76 as DEPAngel Pons2019-12-211-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using a Samsung NP530U3C laptop with an Intel HM76 PCH. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I1097c5fcf782e7ecf52f05c571ad188456307d00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/37803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* chipset_enable.c: Mark Intel Q75 as DEPAngel Pons2019-10-081-1/+1
| | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP Pro 6300 SFF mainboard with an Intel Q75 PCH. However, since ME-enabled chipsets are marked as DEP instead of OK, this one shall also be. Change-Id: I273af0eb33e74b31bc4fdc95362527bba080c5a0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable: Mark Intel CM236 and CM246 as DEPNico Huber2019-08-081-2/+2
| | | | | | | | | | | | | | | The usual ME-lock limitations apply, so this is DEP instead of OK. Tested on Kontron/bSL6 (SKL) and Siemens/Field PG M6 (CFL) and also regression tested on Apollo Lake. Flashrom works fine, and logs and descriptor dumps look good. Also, register and descriptor output agree on the flash layout and permissions. Change-Id: I40db4773f127bec63e377e1d2ab402b47edf9a61 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable: Add support for Cannon Lake U PremiumMatt DeVillier2019-08-081-0/+1
| | | | | | | | | | | | | Add support for Cannon Lake U Premium (CFL-U/WHL-U). Same as discrete 300-series CNP PCH. Tested on a WHL-U laptop w/unlocked IFD. Change-Id: I8a318d63cf408a3b2cec436a3fa6e26cf8552ead Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* ichspi: Add support for discrete Cannon Lake PCHsNico Huber2019-08-081-10/+10
| | | | | | | | | | | | | | | | Only minor differences in the Firmware Descriptor, compared to their predecessors. We extend our check on the `ICCRIBA` field in the descriptor to dis- tinguish it from older generation. Alas, the `freq_read` field was repurposed, so we can't use it as sanity check any more. Change-Id: I1c2d1e8916cecd756e7ac1f0ba221d7cc361ba02 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
* chipset_enable: Add support for discrete Cannon Lake PCHsThomas Heijligen2019-08-081-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted. [1] Intel(R) 300 Series and Intel(R) C240 Series Chipset Family Platform Controller Hub Datasheet - Volume 1 of 2 Revison 4 (Dec 2018) Document Number 337347 [2] Intel(R) 300 Series Chipset Families Platform Controller Hub Datasheet - Volume 2 of 2 Revision 2? (Oct 2018) Document Number 337348 Change-Id: If0b54799d5b93169ee660409bad57ae14677340c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Jeremy Soller <jackpot51@gmail.com>
* chipset_enable: Fix recent -Wmissing-field-initializer troubleNico Huber2019-07-311-14/+14
| | | | | | | | Change-Id: Idb2ec4a767bdc8fdfab6a78b6448e76ea3388a32 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34551 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* ichspi: Add Apollo Lake supportNico Huber2019-07-061-1/+1
| | | | | | | | | | | | | | | It's almost identical to 100 series PCHs and later. There are some additional FREGs (12..15). To not clutter the `if` conditions further, make more use of `switch` statements. Tested on Kontron mAL10. Mark it as DEP as usually the last sector is not covered by the descriptor layout and can't be read. Change-Id: I1c464b5b3d151e6d28d5db96495fe874a0a45718 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30995 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable: Add Apollo LakeNico Huber2019-07-061-4/+20
| | | | | | | | | | | | It works the same as 100 series PCHs and on. The SPI device is at 0:0d.2, though. Mark as BAD until `ichspi` is revised. Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Rework internal bus handling and laptop bail-outNico Huber2019-06-061-377/+440
| | | | | | | | | | | | | | | | | | | | | | We used to bail out on any unknown laptop. However, modern systems with SPI flashes don't suffer from the original problem. Even if a flash chip is shared with the EC, the latter has to expect the host to send regular JEDEC SPI commands any time. So instead of bailing out, we limit the set of buses to probe. If we suspect to be running on a laptop, we only allow probing of SPI and opaque programmers. The user can still use the existing force options to probe all buses. This will obsolete some board-enables that could be moved to `print.c` in follow-up commits. Change-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/28716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* chipset_enable: Mark Intel QS77 as DEPEvgeny Zinoviev2019-06-031-1/+1
| | | | | | | | | | | Tested reading and writing with `-p internal` on MacBook Air 5,2 with Intel QS77. Change-Id: I508b6379507c2881c976d6baf7348b1161449cfe Signed-off-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove trailing whitespaceElyes HAOUAS2019-03-041-1/+1
| | | | | | | | | Change-Id: I1ff9418bcf150558ce7c97fafa3a68e5fa59f11e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/31227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Mark Intel C224 as DEPTristan Corrick2018-12-221-1/+1
| | | | | | | | | | | | Tested on a Supermicro X10SLM+-F. The flash chip has been read, written, and erased many times without issue. Most boards with this chipset will have the ME region locked, hence the selection of DEP. Change-Id: I25126b94e691289a7b29dd81d5c864854a4e0245 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* chipset_enable.c: Mark Intel PM55 as DEPAngel Pons2018-11-031-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP Pavilion dv6-2125ef laptop with an Intel PM55 chipset. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I667ea970be11a35b480e0e7c69a1fdf9afa08762 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/29437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel H81 as DEPTristan Corrick2018-11-011-1/+1
| | | | | | | | | | | | Tested on an ASRock H81M-HDS. The flash chip has been read, written, and erased many times without issue. Most boards with this chipset will have the ME region locked, hence the selection of DEP. Change-Id: I30aae956b2851c741e59403f5e49b80b5ba7c5e4 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/29391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel HM65 as DEPAngel Pons2018-10-081-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using a Toshiba L755 laptop with an Intel HM65. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: I3fd62c3b4ee17a403cc3937422f3d850fd2878a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28955 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove unneeded whitespaceElyes HAOUAS2018-10-051-1/+1
| | | | | | | | Change-Id: I0e72e3e3736a39685b7f166c5e6b06cc241b26be Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Broadwell U Premium as DEPAngel Pons2018-10-031-1/+1
| | | | | | | | | | | | As per Laurent Grimaud on the mailing list. I also have said chipset. Since all ME-enable chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: Ie195e8ec9ea1a2393e31bebdaede4fd3c3301a17 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable.c: Mark Intel HM55 as DEPAngel Pons2018-08-221-1/+1
| | | | | | | | | | | | | Tested reading, writing and erasing the internal flash chip using an HP 630 laptop with an Intel HM55. However, since all ME-enabled chipsets are marked as DEP instead of OK, this one shall follow suit as well. Change-Id: Iaedd5bdc34dfff9b8588a3f4e1ad46460077fdf9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Remove unneeded white spacesElyes HAOUAS2018-06-241-2/+2
| | | | | | | | | Change-Id: I90f171924790ced74a62ca344fee8607607aa480 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/26652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable: Add PCI IDs for discrete Kaby Lake PCHsNico Huber2018-06-041-0/+7
| | | | | | | | | | | | | | | | | | | | | | | The Kaby Lake "200 Series" PCHs [1,2] share the register layout of their Skylake "100 Series" siblings. [1] Intel® 200 Series (including X299) and Intel® Z370 Series Chipset Families Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 003 Document Number 335192 [2] Intel® 200 Series (including X299) Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 003 Document Number 335193 Change-Id: Ida545d69ec998a5d3ae4dc88e76adbb13952bceb Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Fix whitespace errorsElyes HAOUAS2018-04-241-1/+1
| | | | | | | | Change-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable: Mark VX855 as testedLubomir Rintel2018-01-261-1/+1
| | | | | | | | | | | | I can confirm a successful reading and writing of SST49LF080A (LPC) on a Wyse Cx0 Thin Client (Phoenix BIOS 1.0G). Change-Id: I8f48b49ccb760f69d676ec6cbb233e532b12fbe8 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/23158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable: Mark VX900 as testedLubomir Rintel2018-01-021-1/+1
| | | | | | | | | | | I can confirm a successful reading and writing of MX25L8005 (SPI) on a HP t5550 Thin Client (AMI BIOS 786R9 v1.04). Change-Id: I190253b0c1920747b710ed7155e78191cce139eb Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/23030 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* vt_vx: check whether the chipset's MMIO range is configuredLubomir Rintel2018-01-021-0/+8
| | | | | | | | | | | | Avoid attempting to read the SPI bases from the location 0x00000000, all zeroes mean that the chipset's MMIO area is not enabled. Change-Id: I5d3a1ba695153e854e0979ae634f8ed97e6b6293 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/23029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable: Mark SiS 630 as tested OKNico Huber2017-11-211-1/+1
| | | | | | | | | | | | | Tested on an Elitegroup P6STMT with an SST39SF020A parallel flash [1]. [1] https://mail.coreboot.org/pipermail/flashrom/2017-November/015193.html Change-Id: If8cc2af262e392bfba326a62c1a48c658c7d6ce8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* sb600spi: Add support for Merlin Falcon ChipsetRicardo Ribalda Delgado2017-09-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has been tested on a board similar to AMD Bettong. 00:14.0 SMBus [0c05]: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller [1022:790b] (rev 4a) 00:14.3 ISA bridge [0601]: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge [1022:790e] (rev 11) root@qt5022-fglrx:~# ./flashrom -p internal -w kk.rom flashrom v0.9.9-unknown on Linux 4.10.0-qtec-standard (x86_64) flashrom is free software, get the source code at https://flashrom.org Calibrating delay loop... OK. coreboot table found at 0x9ffd6000. Found chipset "AMD FP4". Enabling flash write... OK. Found Micron/Numonyx/ST flash chip "N25Q128..1E" (16384 kB, SPI) mapped at physical address 0x00000000ff000000. Reading old flash chip contents... done. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. Change-Id: I66a240ebc8382cc7e5156686045aee1a9d03fe6d Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-on: https://review.coreboot.org/21429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable: Add support for C620-series Lewisburg PCHDavid Hendricks2017-09-011-2/+27
| | | | | | | | | | | | | | | | This adds PCI IDs for C620-series PCHs and adds CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum. Lewisburg is very similar to Sunrise Point for Flashrom's purposes, however one important difference is the way the "number of masters" is interpreted from the flash descriptor (0-based vs. 1-based). There are also new flash regions defined. Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/20922 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: Mark Braswell as testedDavid Hendricks2017-08-191-1/+1
| | | | | | | | | | | | Reported by Uwe Vieweg: https://mail.coreboot.org/pipermail/flashrom/2017-August/015059.html Change-Id: Iaf7558af8737af36401f577ca7aba9fd7114a3df Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/20923 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* rpci: Use pci_dev struct pointer to avoid API breaksYouness Alaoui2017-08-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | The pci_dev structure is never meant to be used as is, but always as a pointer. By using the struct itself in undo_pci_write_data, we are risking data corruption, or buffer overflows if the structure size changes. This is especially apparent on my system where flashrom segfaults because I compile it with pciutils 3.3.0 and I run it on a system with pciutils 3.5.2. The struture size is different and causes a struct with the wrong size to be sent to the library, with invalid internal field values. This has been discovered and discussed in Change ID 18925 [1] [1] https://review.coreboot.org/#/c/18925/ Change-Id: Icde2e587992ba964d4ff92c33aa659850ba06298 Signed-off-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net> Reviewed-on: https://review.coreboot.org/20784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable: Set 100 series chipsets to NTNico Huber2017-07-281-30/+30
| | | | | | | | | Change-Id: I9376a0c180b7e73751fbd3c8c37b693d358cbfb8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19047 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: Add support for Intel Skylake / KabylakeNico Huber2017-07-281-7/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All publicly known Skylake / Kabylake / Sunrise Point PCH variants share the same register interface [1..6]. Although all SPI configu- ration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hid- den. To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device. This handles SPI flashes only. While booting from LPC is still sup- ported, it seems nobody uses it any more. Some additional PCI IDs were gathered from driveridentifier.com. TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings. [1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995 [2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996 [3] 7th Generation Intel® Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002 Document Number 334658 [4] 7th Generation Intel® Processor Families I/O for U/Y Platforms Datasheet - Volume 2 of 2 Revision 002 Document Number 334659 [5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690 [6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691 Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18925 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* ichspi: Drop `dev` parameter from init functionsNico Huber2017-06-201-4/+4
| | | | | | | | | | | | It's never used and has no clear contract (e.g. will the pointer stay valid beyond the call?). Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Handle Intel Wildcat Point *LP* like Lynx Point LPNico Huber2017-06-201-8/+16
| | | | | | | | | | | | | | | | | | | | | | | The subtle difference was ignored when adding these chipsets. The integrated Wildcat Point LP PCH is documented in [1]. I'm not sure how to account for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct. [1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O, Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet Revision 004 Document Number: 330837 Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18883 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move register decodes into enable_flash_ich_handle_gcs()Nico Huber2017-04-251-4/+18
| | | | | | | | | | | | | | | | | | GCS was decoded partly inside, partly outside this function. The decoding of `top_swap` was off, since passing a `uint8_t` as `bool` doesn't magically check bit0 only. While we are at it, rename this void function to enable_flash_ich_ report_gcs() as it's not doing anything. Beside debug output it doesn't have any side effects. Change-Id: I40addec98cb6840763adad30f9d0e27dadce6d1e Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18882 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-17 08:11:14 +0000