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* flashchips.c: Mark MT25QL256 as testedSimon Buhrow2021-06-101-1/+1
| | | | | | | | | | As mentioned in mail from Bernd.Stoeferle@elbitsystems-de.com on 22.12.2020. Change-Id: Ie49332333f49a40f7bd8f3b5e42a8e2ad6995618 Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/50720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: change chip name from 'W25Q64JW' to 'W25Q64JW...M'Nikolai Artemiev2021-06-101-2/+2
| | | | | | | | | | | | | | | | | | | | According to the W25Q64JW datasheet rev. E, only devices ending with the letter 'M' have a device ID of 8017h. There are other variants with different device IDs. This patch makes the 'W25Q64JW...M' definition consistent with the 'W25Q32JW...M' definition. The device ID macro defined in flashchips.h has also been renamed from WINBOND_NEX_W25Q64JW to WINBOND_NEX_W25Q64JW_M. BUG=b:166294558 BRANCH=none TEST=builds Change-Id: Ib0dc914da286a191d22e666332b1063b88db4251 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: add support for W25Q32JW...MNikolai Artemiev2021-06-101-0/+38
| | | | | | | | | | | | | | | | | | | | | The chip was added to cros flashrom in `commit 1fc77dd1ee27a5d6e58a82c6ed6ed390a15372d7`. Quoting from the commit message: > We have varied the correct chip name is reported as well as > write and read 16MBytes of random data and verified the checksum's match. > Further, --wp-list appears to report the correct ranges. > > BUG=b:130199963 > BRANCH=none > TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum matched. Change-Id: I7425e12658dd69c4ec8d3309dd591d09a935bb4d Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/53946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Fix 4BA advertisement for dummy chipNico Huber2021-05-121-1/+1
| | | | | | | | | | | | The dummyflasher only supports the native 4BA read and write commands, so only advertise these. Change-Id: Ia7340835ce1680d197f250bdb5990ab2ffe3671f Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/54068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add MX25L3233FNico Huber2021-04-251-2/+2
| | | | | | | | | | | | Only mattering difference to the MX25L3273E seems to be the voltage range (starting at 2.65V instead of 2.7V). I don't think that would justify yet another entry. Change-Id: I73402dddedf360ab84caed4c019efe27b477d4c2 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52570 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Correct OTP comment for MX25L3273ENico Huber2021-04-251-1/+1
| | | | | | | | | | The datasheet says 4K bits, maybe just a copy-paste error. Change-Id: I42b10aa09c969e5c5e7102b1e8ab496f52bd27bb Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add support for Boya/BoHong Microelectronics B_25D16AChristian Kudera2021-04-241-0/+38
| | | | | | | | | | Read tested on CH341A Change-Id: I25b776204affda94cc7e753e7671ef9d3d9508f1 Signed-off-by: Christian Kudera <coreboot@kudera.at> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Adapt IDs for Boya MicroelectronicsAngel Pons2021-04-241-4/+4
| | | | | | | | | | | | Looks like BoHong Microelectronics has the same vendor ID and makes very similar chips. For instance, Boya BY25Q128AS and BoHong BH25Q128AS have the same specifications and their datasheets are mostly identical. Change-Id: I8d6951797daeeecca6af200c995297c0394adefd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/52550 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: mark MX25U25635F as TESTED_OK_PREWNikolai Artemiev2021-03-241-1/+1
| | | | | | | | | | | | | | | The chip was marked as TESTED_OK_PREW in the cros tree by `commit 419e32ae457cc36b03757b89471a7ce3770e9611`. Quoting from the original commit message: > TEST=Tested writes using Servo Change-Id: Id7f44a41d6b2c397f1ce2e345f8ab44e95e4cfa2 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51736 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: mark GD25Q256D as TESTED_OK_PREWNikolai Artemiev2021-03-241-1/+1
| | | | | | | | | | | Tested read/write/erase/verify with FT232H programmer. Change-Id: Ia7d52b69eb571113fe3c60ec9a139ee67180509b Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51735 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: mark EN25S64 as TESTED_OK_PREWNikolai Artemiev2021-03-241-1/+1
| | | | | | | | | | | | | | | The chip was marked as TESTED_OK_PREW in the cros tree by `commit b2f900273aac329b82089e4dbc5a8ba3d032fff0`. Quoting from the original commit message: > TEST=read and write BIOS on glimmer with Eon device. Change-Id: I13dc3e6bde9e4581fdd5856a412918784b913fbc Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51734 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* CHROMIUM: flashrom: update .tested field for EN25QH128Tim Chen2021-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | update .tested field from TEST_UNTESTED to TEST_OK_PREW BUG=b:159768722 BRANCH=none TEST=Flash Duffy bios pass on running `flashrom_tester /usr/sbin/flashrom host` Original-Change-Id: I9467588988c2cab0987737c53ace0832144ef169 Original-Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/2281508 Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Original-Commit-Queue: Edward O'Callaghan <quasisec@chromium.org> (cherry picked from commit 045e05eb92e3dd826e8ce61973c0d1004195a3ff) Change-Id: Ic111f1a9cc5c7b5b5100ddda362c11c91e8a4165 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add support for Adesto AT25SF128AEdward O'Callaghan2021-02-281-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following adds support for the Adesto AT25SF128A-SHB-T part. We have varied the correct chip name is reported as well as write and read 16MBytes of random data and verified the checksum's match. Further, --wp-list appears to report the correct ranges. BUG=None BRANCH=none TEST=Ran flashrom with a Dediprog SF100, RW random data and checksum matched. Original-Change-Id: Ic22ca588f33753fdf492e8445324bcc0a809d3e2 Original-Signed-off-by: Edward O'Callaghan <quasisec@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/1593201 Original-Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Original-Tested-by: Martin Roth <martinroth@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@chromium.org> (cherry picked from commit 1fa87e058b72a2de1e9127a45e9978361de48479) Note: this does not include the changes made to writeprotect.c in the original patch, as they depend on a large amount of additional writeprotect code that is currently only present in the cros tree, and the intention here is just to reduce the diff in flashchips.c. The `.wp` field has also been removed. Change-Id: I1ce2a6699a1f0116306f668123673a1ba9c932d2 Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/51097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Mark Macronix MX25L1635D as testedAngel Pons2021-02-071-1/+1
| | | | | | | | | | Tested probe, read, erase and write with a FTDI FT2232H successfully. Change-Id: I7421b7e36e687ea2ffff494c00157976db73ac43 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49489 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Mark GD25LQ128C/D as TEST_OK_PREWAlan Green2021-01-151-1/+1
| | | | | | | | | | | | I have successfully probed/read/erased/written a GD25LQ128D, so marking this entry as tested. Signed-off-by: Alan Green <avg@google.com> Change-Id: Ic5329ebe81b6c1eabfb594f7f7affb3fd460db6b Reviewed-on: https://review.coreboot.org/c/flashrom/+/49229 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips.c: Add support for XMC new SPI flash typesluke he2021-01-021-0/+238
| | | | | | | | | | | | | | | | | | | | Adds initial support for the follow SPI flash chips: XM25QU64C XM25QU128C XM25QU256C XM25QH64C XM25QH128C XM25QH256C BUG=none TEST=builds Signed-off-by: Luke He <sixuerain@qq.com> Change-Id: I15c51b0f1ed789bcb2cabe33bc830f8d5d916969 Reviewed-on: https://review.coreboot.org/c/flashrom/+/48949 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Mark Intel 25F640S33B8 as TESTED_PREWZoltan HERPAI2020-12-111-1/+1
| | | | | | | | | | Tested with ch341a_spi from an Atheros AP81 reference board. Change-Id: I67b5962a1ae26fd1bc7e3889f1616def28b599ef Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips.c: add Spansion chipsNikolai Artemiev2020-12-031-0/+180
| | | | | | | | | | | | | | | | | | | | | Adds support for the following chips: - S25FL128S - S25FL129P - S25FL256S - S25FS128S - {F,S,V}29C51001B Chips imported from cros flashrom at `9c4c9a56b6a0370b383df9c75d71b3bd469e672d`. BUG=b:153800073 TEST=builds Signed-off-by: Nikolai Artemiev <nartemiev@google.com> Change-Id: If6b23ad2e65258143e0045133828d9db119fb665 Reviewed-on: https://review.coreboot.org/c/flashrom/+/46064 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Boya Microelectronics BY25Q128ASJack Olsen2020-11-201-0/+38
| | | | | | | | | | | Tested on Buspirate. Signed-off-by: Jack Olsen <omegasec@tutanota.com> Change-Id: I881ba86cfaa82e43c73360135d47c74d896cc191 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44308 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Fudan SPI flash chipsJakob Petersson2020-10-231-0/+272
| | | | | | | | | | | Signed-off-by: Jakob Petersson <github@jakobpetersson.se> Change-Id: I8045ecb8778fd6111fcccc075e69928f131a926a Reviewed-on: https://review.coreboot.org/c/flashrom/+/46513 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* support 4-byte address format for VARIABLE_SIZE dummy flash deviceNamyoon Woo2020-09-071-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a support of 4-byte address format for VARIABLE_SIZE dummy flash device, so that it can emulate an flash size larger than 16 MBytes. - assigned a feature bits FEATURE_4BA to VARIABLE_SIZE flash config. - added codes handling two commands, JEDEC_READ_4BA and JEDEC_BYTE_PROGRAM_4BA. - changed blockeraser to use Chip-Erase command so that it can be free from flash address byte format. TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=33554432, \ emulate=VARIABLE_SIZE -w ${IMG_32MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG_16MB} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=8388608, \ emulate=VARIABLE_SIZE -w ${IMG_8MB} -V -f Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Ia59eecfcbe798d50f8dacea98c3c508edf8ec77e Reviewed-on: https://review.coreboot.org/c/flashrom/+/44881 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* support variable-size SPI chip for dummy programmerNamyoon Woo2020-09-071-0/+21
| | | | | | | | | | | | | | | | | | | This is designed for firmware updater to pack firmware image preserving some specific partitions in any size. BUG=none TEST=ran the command line below: $ flashrom -p dummy:image=${TMP_FILE},size=16777216, \ emulate=VARIABLE_SIZE -w ${IMG} -V -f $ flashrom -p dummy:image=${TMP_FILE},size=auto, \ emulate=VARIABLE_SIZE -w ${IMG} -V -f Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Iff266e151459561b126ecfd1c47420b385be1db2 Reviewed-on: https://review.coreboot.org/c/flashrom/+/44879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add W25Q256JW_DTRDavid Hendricks2020-08-191-0/+47
| | | | | | | | | | | | | | | | | | | | | | W25Q256JW currently has two variants, the W25Q256JW with device ID 0x6019 added in commit be4682d and the W25Q256JW_DTR (aka W25Q256JW-IM) with device ID 0x8019 added by this patch. Winbond W25Q256-series chips have a few device IDs: 0x4019: W25Q256FV 0x6019: W25Q256JW 0x7019: W25Q256JV 0x8019: W25Q256JW_DTR Hence we need to be more specific with naming than usual to avoid a false positive with wildcards. Change-Id: I50a6de2c915f9201c458378fcc49130ead73d8c4 Signed-off-by: David Hendricks <david.hendricks@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/42386 Reviewed-by: Simon Buhrow Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add support for Macronix MX25L5121ESteve Markgraf2020-08-041-0/+38
| | | | | | | | | | Tested with ch341a_spi. Change-Id: I881e2cda938083ba271b2ee0c457d2bbd8e1a766 Signed-off-by: Steve Markgraf <steve@steve-m.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43416 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for Winbond W25X05CLJacob Appelbaum2020-07-261-0/+32
| | | | | | | | | | | | | | This commit adds support for the Winbond W25X05CL SPI flash chip. The Winbond W25X05CL is a 512Kib (64 KiB) SPI flash chip with 4KiB sectors. I have tested this patch with a Bus Pirate (v3b) and an in-circuit W25X05CL flash chip using a test clip. Reading, erasing, and writing all function as expected. Change-Id: I19c33c7da374f0263f30577a10a0f0f1afa4febc Signed-off-by: Jacob Appelbaum <jacob@appelbaum.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/43573 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add W25Q256.Wel-coderon2020-06-161-0/+41
| | | | | | | | | | | | Nicklas Lennert wrote me via the flashrom mailing list that he successfully ran read, write and verify cmd. Signed-off-by: Simon Buhrow <simon.buhrow@posteo.de> Change-Id: I3608945a38b5ed42b8b2b9b2b388cdea97141d7b Reviewed-on: https://review.coreboot.org/c/flashrom/+/40855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Revert "flashchips: port S25FS(128S) chip from chromiumos"Nico Huber2020-05-011-64/+0
| | | | | | | | | | | | | | | | | | | | | This reverts commit a3519561bd0fb44153bb376322b799000657576f. Breaks support for most SPI flash chips. It's too big and too invasive to be reviewed as a single commit. The changes to `spi_poll_wip():spi25.c` were not noticed in the original review that were from the similarly named function and file `s25f_poll_status():s25f.c` in the downstream Chromium fork. V.2: Rebase and rephrase commit msg to reflect how the issue slipped in. Change-Id: Id2a4593bdb654f8a26957d69d52189ce61621d93 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40626 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: port S25FS(128S) chip from chromiumossibradzic2020-04-221-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This may seem too big just to support yet another flash chip, but in reality it brings support for whole new family of S25FS Spansion/Cypress flash chips. These chips require handling of some special status registers for erasing or writing, with very specific timing checks in place. For example, WIP status bit will remain being set to 1 if erase or programming errors occur, and in that case chip 'software reset' has to be performed otherwise the chip will remain unresponsive to all further commands. Also, special CR3NV register (Configuration Register 3 Nonvolatile) status bits needs to be read and set by using RDAR (ReaD Any Register) and WRAR (WRite Any Register) OP commands, and these states are needed to determine which type of reset feature is enabled at the time (legacy or S25FS type) in the first place, determine whether Uniform or Hybrid sector architecture is used at the time, or set programming buffer address wrap point (256 or 512 bytes). Furthermore, S25FS chip status register has to be restored to its original state (hence that ugly CHIP_RESTORE_CALLBACK) following erasing or writing, failing to do so may result in host being unable to access data on the chip at all. Finally, although this brings support for the whole family of chips, I only have one such chip to do the actual testing, S25FS128S (Small Sectors), which I had fully tested on ch341a and FT4232H programmers, with confirmed working probe, read, erase and write. Full summary of changes are here: flashchips: add new flashchip sctructure property: .reset add chip definitions: S25FS128S Large Sectors S25FS128S Small Sectors flash: add macro (chip_restore_func_data call-back): CHIP_RESTORE_CALLBACK flashrom: add struct: chip_restore_func_data add call-back function: register_chip_restore spi: add OP codes: CMD_RDAR, CMD_WRAR, CMD_WRAR_LEN, CMD_RSTEN, CMD_RST add register bit function definitions: CR3NV_ADDR, CR3NV_20H_NV add timers: T_W, T_RPH, T_SE spi25: refactor (based on chromiumos implementation) function: spi_poll_wip port these functions from chromiumos: probe_spi_big_spansion s25fs_software_reset s25f_legacy_software_reset s25fs_block_erase_d8 spi25_statusreg: port these functions from chromiumos: spi_restore_status s25fs_read_cr s25fs_write_cr s25fs_restore_cr3nv Most of the ported functions are originally from s25f.c found at https://chromium.googlesource.com/chromiumos/third_party/flashrom with exception of spi_restore_status which is defined in spi25_statusreg.c. The rest of macros and OP codes are defined in same files as in this commit. Change-Id: If659290874a4b9db6e71256bdef382d31b288e72 Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add support for Winbond W25Q64JWScott Chao2020-04-091-0/+40
| | | | | | | | | | | | | | BUG=b:153515968 BRANCH=kukui TEST=flash coreboot on kakadu and get successful result. Change-Id: I8637129421a3b0f96bd8dffa4f50783ea6931967 Signed-off-by: Scott Chao <scott.chao@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40275 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add W25Q512JVJoel Stanley2020-04-081-0/+44
| | | | | | | | | | | | | https://www.winbond.com/resource-files/W25Q512JV%20DTR%20RevB%2006132019%20133.pdf Tested with dediprog SF100. Change-Id: I8d16f0918785795cc49500435a03641b87d706e9 Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: add support for GigaDevice GD25WQ80EDino Li2020-03-251-0/+38
| | | | | | | | | | | | | | Support GD25WQ80E, which is the internal flash of IT81202. TEST=Building flashrom and flashing FW image into IT81202 successfully. Change-Id: Ib5feaa6ecc7b11b2218e5f02c087b4331388bef8 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add Macronix MX25R3235Fsibradzic2020-03-241-0/+39
| | | | | | | | | | | | | | | | | 32Mbit (4MiB) [x1/x2/x4] Wide Voltage Range (VCC 1.65V-3.6V). It is similar to the already-supported MX25R6435F, but the total size is halved. Tested on ch341a, FT4232H and FT2232H (PicoTAP) programmers, confirmed working probe, read, erase and write. Fixes: https://github.com/flashrom/flashrom/issues/43 Change-Id: I6e79115adba17d13d24bc85d78707d53fd4a0be5 Signed-off-by: Samir Ibradzic <sibradzic@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* flashchips: Add Spansion S25FL512Sv1.2Bernhard Urban-Forster2020-02-091-0/+33
| | | | | | | | | | | | | | | As found on the Tesla AP2.5 board. Based on https://mail.coreboot.org/pipermail/flashrom/2013-June/011066.html Tested with: flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 -r content.bin Signed-off-by: Bernhard Urban-Forster <lewurm@gmail.com> Change-Id: Ifa9b7615951125b6bbc1f051370ef54896bf506c Reviewed-on: https://review.coreboot.org/c/flashrom/+/38596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add AT25SF321darkarnium2019-12-141-0/+38
| | | | | | | | | | | | | | | This commit adds support for the Adesto AT25SF321 SPI flash chip. Probe and read operations have been tested via FT2232H interface, but writes have not been verified. Datasheet is available at the following URL: https://www.adestotech.com/wp-content/uploads/DS-AT25SF321_047.pdf Change-Id: I7410815e063ffe154a97d7ea5881c8eb82025f56 Signed-off-by: Peter Adkins <pete@kernelpicnic.net> Reviewed-on: https://review.coreboot.org/c/flashrom/+/36904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* flashchips: Add W25Q128JW_DTRPeichao Wang2019-11-131-0/+38
| | | | | | | | | | | | | Port the code from chromeos flashrom BUG=b:144297264 TEST=Tested using W25Q128JWDTR in SPI mode Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ifc28878b17dc10da2cfd8f82fffbd57adb22799e Reviewed-on: https://review.coreboot.org/c/flashrom/+/36717 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* flashchips: Add missing N25Q/MT25Q variantsJacob Creedon2019-11-111-3/+525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds missing voltage and capacity variants for N25Q and MT25Q series devices. This also fixes a typo in some model numbers where the last letter should have been a G instead of an E. Added devices include: N25Q256..1E N25Q512..1G N25Q00A..1G N25Q00A..3G MT25QU128 MT25QL128 MT25QU256 MT25QU512 tested by Jacob Creedon <jcreedon@google.com> MT25QL01G tested by Konstantin Grudnev <grudnevkv@gmail.com> MT25QU01G MT25QL02G MT25QU02G Two have been tested as indicated, all other variants added are marked untested. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: I85630e4f6c0aa3b261f9871b7d363dad278b997e Reviewed-on: https://review.coreboot.org/c/flashrom/+/34491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add missing block erasers for GD25Q256DNico Huber2019-10-051-0/+9
| | | | | | | | Change-Id: I7e49e468c7f1eaf0ddd5fc08d6cc6569274faf94 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/35798 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add support for M95M02-A125Konstantin Grudnev2019-10-041-0/+27
| | | | | | | | | | | | Automotive 2 Mbit (256KiB) serial SPI bus EEPROM PREW tested successfully with use of ch341a programmer on Linux host 5.2.0-1-MANJARO x86_64 Signed-off-by: Konstantin Grudnev <grudnevkv@gmail.com> Change-Id: Ic29cd9051c7eac4822d620c299834134f987f01b Reviewed-on: https://review.coreboot.org/c/flashrom/+/34496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: Add W25Q128.V..M printlock attributeAlan Green2019-09-241-0/+1
| | | | | | | | | | | | Add a printlock attribute for the Winbond W25Q128.V..M chip. The printlock attributes matches the ChromiumOS repo's definition of this chip. Signed-off-by: Alan Green <avg@google.com> Change-Id: I775d5d40677593dcb2d05750f8bbc62871b0e551 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35549 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Mark W25Q40EW as TESTED_PREWAlan Green2019-09-241-1/+1
| | | | | | | | | | | | | | Mark Winbond W25Q40EW as TESTED_PREW. The Winbond W25Q40EW has been marked TESTED_PREW in the ChromiumOS repository. ChromiumOS has the same defintion for this chip as this repo, except that ChromiumOS does not have FEATURE_OTP. Signed-off-by: Alan Green <avg@google.com> Change-Id: I4be5b2e1069a3f735f0dc6ec92d5f4c8946fbb02 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Add GD25Q256D from downstreamAlan Green2019-09-241-0/+38
| | | | | | | | | | | | | Take definition of GD25Q256D from ChromiumOS repository. This chip was added in `commit 0c38355c` by dlaurie@google.com 2019-03-17. Signed-off-by: Alan Green <avg@google.com> Change-Id: I79d4ed48aa9126a8a6ce455a9564451346195b8f Reviewed-on: https://review.coreboot.org/c/flashrom/+/35480 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Mark EN29F002(A)(N)B as tested +EWAlan Green2019-09-181-1/+1
| | | | | | | | | | | | | | | Mark EN29F002(A)(N)B as tested for erase and write. This chip was marked tested in the Chromium (downstream) repo change 98d917cfba55b68516cdf64c754d2f36c8c26722 "Add a bunch of new/tested stuff and various small changes 8" TEST=Build and run flashrom -L Signed-off-by: Alan Green <avg@google.com> Change-Id: Idd26187905f389fc858eea5b13915af88e40afe9 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Identify MX25L25645G partAlan Green2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | Apply downstream patch d978051c2e7da88088ec4ef19827c04873a5479d, "flashrom: Identify MX25L25645G part" from chris_zhou@compal.corp-partner.google.com 2019-04-13. Change description was: """ MX25L25635F and MX25L25645G have the same chips identify. Add MX25L25645G to the name of the part so that it doesn't confused people. """ Signed-off-by: Alan Green <avg@google.com> Change-Id: I317345b4753cfc46fdca8f673a0591e33b62138b Reviewed-on: https://review.coreboot.org/c/flashrom/+/35091 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add GD25Q127C name to the GD25Q128C entryAlan Green2019-09-171-1/+1
| | | | | | | | | | | | | | | | | | | Renamed GigaDevice GD25Q128 to GD25Q127C/GD25Q128. According to downstream (ChromiumOS) change 4216ba3d0fbd1804a71002b9c17e0b04029a03f1 "flashchips: Add GD25Q127C name to the GD25Q128C entry", the 127C chip is replacement for the 128C chip. I have confirmed that 127C is newer and that 128C does not appear to be documented on Gigadevice's website or available from Digikey. TEST=Ran flashrom -L Signed-off-by: Alan Green <avg@google.com> Change-Id: I3366e5904eff2443fda90552f7f5e31a8785d8b3 Reviewed-on: https://review.coreboot.org/c/flashrom/+/35089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips.c: Put SFDP-capable chip back into positionAlan Green2019-09-171-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | Put entry for Unknown SFDP-capable chip back into place at end of file. Change 1f9cc7d89992114c70f7a0545ad9f98701bebe56 "flashchips.c: Sort file by vendor and model" reordered many entries in flashchips.c, including this one. However, the entry for Unknown, SFDP-capable chip should not have been moved before any specific chip entries. As reported by Angel Pons <th3fanbus@gmail.com> at https://review.coreboot.org/c/flashrom/+/33931: """ Oops, this introduced a bug: the SFDP entry is no longer at the end of flashchips.c, so probing on a SFDP-capable Winbond chip results in added noise (flashrom says things about an unknown chip, and then has two definitions for the same chip). """ Signed-off-by: Alan Green <avg@google.com> Change-Id: I5955020456dbcd5e7db280a459b668a743e464dc Reviewed-on: https://review.coreboot.org/c/flashrom/+/35037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: upstream changes to GD25LQ128Alan Green2019-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | Change name of GD25LQ128 to GD25LQ128CD. This is an upstreaming of the change from the chromium flashrom repo SHA 6c957d745f5d3dcadd1035734a5cf1b804bd0f2f (Also visible at https://chromium-review.googlesource.com/c/chromiumos/third_party/flashrom/+/1181175) The rationale from that change was: The GD25LQ128C part is EOL. It's replacement is GD25LQ128D, but both chips identify in the same manner. Add GD25LQ128D to the name of the part so that it doesn't confused people. Making this name consistent will simplify further merging from the chromium fork. Change-Id: I57804f1a33170668e029a7b08ac050d9a3bd6dbb Reviewed-on: https://review.coreboot.org/c/flashrom/+/34735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* flashchips: Add missing MT25Q erase commandsJacob Creedon2019-08-051-0/+18
| | | | | | | | | | | This adds additional 32KiB subsector erase commands 0x5c and 0x52 and an additional bulk erase command of 0x60. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: I5307c4b96cbd62203f5bad0c94737180fda621aa Reviewed-on: https://review.coreboot.org/c/flashrom/+/34490 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Fix N25Q512 bulk eraseJacob Creedon2019-08-051-2/+2
| | | | | | | | | | | The N25Q is a stacked device, so it requires 0xC4 to perform a die erase. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: Ib408fbe5633abd8b657e3907142b997e88b33f84 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips: Split MT25Q from N25QJacob Creedon2019-08-051-2/+82
| | | | | | | | | | | | | | | The MT25Q is the successor to the N25Q from Micron/Numonyx/ST. The MT25Q is almost entirely backwards compatible with the N25Q series, however, the MT25Q has additional subsector erase commands available, and there are differences in stacked devices in the higher capacity variants. The N25Q devices are left with "Micron/Numonyx/ST" as the vendor and MT25Q devices are set with "Micron" as the vendor. Signed-off-by: Jacob Creedon <jcreedon@google.com> Change-Id: I9d79978544b19cf9acd5f3ea6196cf6f3b3435ef Reviewed-on: https://review.coreboot.org/c/flashrom/+/34488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* flashchips.c: Mark AMD Am29F010A/B as TEST_OK_PREAlan Green2019-08-031-1/+1
| | | | | | | | | | | | | | | | The AMD Am29F010 was marked TEST_OK_PRE in chromium repo change SHA d217d1219ccaa43a01cd75475409183bd5714410. There are no other differences in the definition of this chip. This is the only change from the Chromium repo to be upstreamed for AMD chips. Signed-off-by: Alan Green <avg@google.com> Change-Id: I7fa10d33b42c09d035c611535a54592083c4eaa0 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34534 Tested-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-29 10:19:46 +0000