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* tree/: Drop const from opaque data ptr in master definitions [alt]Edward O'Callaghan2021-01-171-3/+3
| | | | | | | | | | | | | | | | | | The opaque data pointer need not necessarily have constant data for the life-time of the specific master. This is because the data field purpose is for the master to use as it sees fit for managing its own internal state and therefore we should not constrain this as being RO data at init time. BUG=none BRANCH=none TEST=builds Change-Id: I686c3c79547e35d48f3fd0b524fc98c176dcea6e Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/49131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* flashrom.c: Correct "raiden_debug_spi" drv nameEdward O'Callaghan2020-11-301-1/+1
| | | | | | | | | | | | | | | Unfortunately raiden_debug was upstreamed with a slightly incorrect name of "raiden_debug" whereas in ChromiumOS it is known as "raiden_debug_spi" and so correct this to align. This avoids confusion and divergence for a unified future. Change-Id: I0eca35863403c5d4adbe19b31801e8dfa072006f Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* raiden_debug: Rename with '_DEBUG_SPI' suffixEdward O'Callaghan2020-11-281-2/+2
| | | | | | | | | | | | Unfortantly raiden_debug was upstreamed with a misnaming of the CONFIG_ make param that introduces unnecessary divergence. Rename to 'CONFIG_RAIDEN_DEBUG_SPI' as-is downstream. Change-Id: I07c03647c329286bb223e4dae4665704e508db2c Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/48105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* programmer.h,c: Drop dead noop_chip_writeb() fnEdward O'Callaghan2020-11-241-1/+0
| | | | | | | | | | | | | | Drop dead code. BUG=none BRANCH=none TEST=`git grep noop_chip_writeb` Change-Id: I160406df903b3b0a49a5ff3ec78a030e10fa60a0 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
* programmer.h: Reorder MEC1308 and ENE_LPC enumeratorsEdward O'Callaghan2020-11-091-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | Programmer enumerators and their corresponding programmer_table entries need to be aligned. This was not the case for MEC1308 and ENE_LPC. Their configs were not enabled by default until commit 26fde5b0b067 ("ene_lpc,mec1308: Fix entry-points to be explicit")/CL:2488823, allowing this issue to go unnoticed. The particular symptom of the mismatch was internal_init() trying to init linux_mtd instead of linux_spi. BUG=b:172668501 TEST=flashrom -p host on gale BRANCH=None Original-Change-Id: I2e9d3df6a6fd6d5d8e3a5a13ee56f5997b10ea52 Original-Signed-off-by: Sam McNally <sammc@chromium.org> Change-Id: I8e7a57b7c30e2dd2306d6fe7268eee8bb9d0c8a5 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47353 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Victor Ding <victording@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for Comet Lake-U/400-series PCHMatt DeVillier2020-09-241-0/+1
| | | | | | | | | | | | | | | | Add enum CHIPSET_400_SERIES_COMET_POINT and treat it identically to CHIPSET_300_SERIES_CANNON_POINT. Add PCI IDs for Comet Lake, CML-U Premium and classify as CHIPSET_400_SERIES_COMET_POINT. Test: read/write unlocked CML-U board Change-Id: I43b4ad1eecfed16fec59863e46d4e997fbe45f1b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/44420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
* Add MEC1308 EC programmerVictor Ding2020-08-201-0/+8
| | | | | | | | | | | | | Initial support of Microchip MEC1308 Embedded Controller. BUG=b:156144893 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I2d51b4bdc0b38b6e488e71b9e774eb6232a2069e Reviewed-on: https://review.coreboot.org/c/flashrom/+/44541 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Add ENE LPC programmerVictor Ding2020-08-201-0/+8
| | | | | | | | | | | | | | Initial support of ENE LPC interface keyboard controller. BUG=b:156140422 BRANCH=none Signed-off-by: Victor Ding <victording@google.com> Change-Id: I970afd8c1bd92c159c60e09f22e2f18c0433729d Reviewed-on: https://review.coreboot.org/c/flashrom/+/44580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Initial Realtek MST i2c_spi supportEdward O'Callaghan2020-05-041-0/+8
| | | | | | | | | | | | | | | | | | | | | This spi master allows for programming of a Realtek RTD2142 MST with external SPI flash chip routed via its internal i2c transport mechanism. BUG=b:152558985,b:148745673 BRANCH=none TEST=echo "00000000:0004ffff fw" > layout && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -r && \ flashrom -p realtek_mst_i2c_spi:bus=8 -l layout -i fw:dump.bin -w && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-size && \ flashrom -p realtek_mst_i2c_spi:bus=8 --flash-name Change-Id: I892e0be776fe605e69fb39c77abf3016591d7123 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40667 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shiyu Sun <sshiyu@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* const'ify flashctx to align signatures with cros flashromEdward O'Callaghan2020-04-301-4/+4
| | | | | | | | | | | | | | | | The ChromiumOS flashrom fork has since const'ify flashctx in a few places. This aligns the function signatures to match with downstream to ease forward porting patches out of downstream back into mainline flashrom. This patch is minimum viable alignment and so feedback is welcome. Change-Id: Iff6dbda13cb0d941481c0d204b9c30895630fbd1 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/40324 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* lspcon_i2c_spi.c: Add SPI-master support for PS17{5,6}Shiyu Sun2020-04-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | This adds support for the Parade lspcon usb-c to HDMI protocol translater part that is i2c-controlled. The support allows the host to reach the SPI ROM that hangs off the part where it stores its firmware. Usage is as follows: flashrom -p lspcon_i2c_spi:bus=X where X is the bus number. BUG=b:148746232 BRANCH=none TEST=tested with following commands, read/write/erase works good. flashrom -p lspcon_i2c_spi:bus=7 -r /tmp/foo; flashrom -p lspcon_i2c_spi:bus=7 -E; flashrom -p lspcon_i2c_spi:bus=7 -w /tmp/foo; Change-Id: I039e683252cfaf1ffef8694a3e8081b1b6b944f7 Signed-off-by: Shiyu Sun <sshiyu@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
* Fix segfault when running `flashrom -L`Angel Pons2020-03-261-0/+1
| | | | | | | | | | | | | | | | | | | | The raiden_debug programmer is of type USB. However, it does not set the field `devs.dev`, which will result in a segfault when trying to print the devices of the non-existing table. Fix that by replacing `devs.note` with `devs.dev` and adding an empty device table. Since Device IDs are not used to match programmers, nothing could be added to the table. TEST=Running `flashrom -L` no longer segfaults and returns normally. Change-Id: Ie4171a11384c34abb102d1aadf86aa1b8829fc04 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/39826 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* raiden_debug: Upstream ChromiumOS servo debug board progEdward O'Callaghan2020-03-031-0/+8
| | | | | | | | | | | | | | | | | | Initial check-in of the Raiden debugger programmer. Squash in, raiden_debug: Add missing .write_aai cb fn raiden_debug: greatly improve protocol documentation BUG=b:143389556 BRANCH=none TEST=builds Change-Id: Ifad273a708acea4de797a0808be58960635a8864 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/38209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Add support for STLINK V3 debugger/programmer via its SPI bridgeMiklós Márton2019-12-311-0/+9
| | | | | | | | Change-Id: Icffab87ac8f2c570187ed753ec70f054541873a4 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* Add support for National Instruments USB-845x devicesMiklós Márton2019-11-141-0/+8
| | | | | | | | Change-Id: I9477b6f0193bfdf20bbe63421a7fb97b597ec549 Signed-off-by: Miklós Márton <martonmiklosqdev@gmail.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/25683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* internal: Fix board vendor and model memory leaksJacob Garber2019-09-241-1/+1
| | | | | | | | | | | | | The board vendor and model are sometimes specified as arguments during an internal flash, so make sure they are freed at the end of initialization. Change-Id: I9f43708f3b075896be67acec114bc6f390f8c6ca Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1230664, 1230665 Reviewed-on: https://review.coreboot.org/c/flashrom/+/34846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* chipset_enable: Add support for discrete Cannon Lake PCHsThomas Heijligen2019-08-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The Cannon Lake "300 Series" PCHs [1,2] share the register layout of the Skylake "100 Series". Mark them as BAD until `ichspi.c` is adapted. [1] Intel(R) 300 Series and Intel(R) C240 Series Chipset Family Platform Controller Hub Datasheet - Volume 1 of 2 Revison 4 (Dec 2018) Document Number 337347 [2] Intel(R) 300 Series Chipset Families Platform Controller Hub Datasheet - Volume 2 of 2 Revision 2? (Oct 2018) Document Number 337348 Change-Id: If0b54799d5b93169ee660409bad57ae14677340c Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/34071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Jeremy Soller <jackpot51@gmail.com>
* Fix -Wsign-compare troubleNico Huber2019-07-311-1/+1
| | | | | | | | | | | Mostly by changing to `unsigned` types where applicable, sometimes `signed` types, and casting as a last resort. Change-Id: I08895543ffb7a48058bcf91ef6500ca113f2d305 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30409 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
* chipset_enable: Add Apollo LakeNico Huber2019-07-061-0/+1
| | | | | | | | | | | | It works the same as 100 series PCHs and on. The SPI device is at 0:0d.2, though. Mark as BAD until `ichspi` is revised. Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* spi: Drop spi_controller typeNico Huber2019-06-271-59/+0
| | | | | | | | | | Not needed anymore. Drop it fast before it encourages anyone to violate layers again! Change-Id: I8eda93b429e3ebaef79e22aba76be62987e496f4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33651 Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* bitbang_spi: Drop bitbang_spi_master_typeNico Huber2019-06-231-26/+0
| | | | | | | | | | | It only existed to make maintenance harder and waste our time. Change-Id: I7a3b5d9ff1e99d2d4f873c6f19fb318f93762037 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/33638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
* Rework internal bus handling and laptop bail-outNico Huber2019-06-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | We used to bail out on any unknown laptop. However, modern systems with SPI flashes don't suffer from the original problem. Even if a flash chip is shared with the EC, the latter has to expect the host to send regular JEDEC SPI commands any time. So instead of bailing out, we limit the set of buses to probe. If we suspect to be running on a laptop, we only allow probing of SPI and opaque programmers. The user can still use the existing force options to probe all buses. This will obsolete some board-enables that could be moved to `print.c` in follow-up commits. Change-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/28716 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Thomas Heijligen <src@posteo.de>
* dediprog: Disable 4BA completelyv1.1-rc1Nico Huber2019-04-021-0/+7
| | | | | | | | | | | This is an interim solution. We'll have to enable 4BA step-by-step for each dediprog protocol version. Change-Id: I08efcbb09ab3499ef6902a698e9ce3d6232237c4 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/flashrom/+/30386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Add initial J-Link SPI programmerMarc Schink2019-01-051-0/+11
| | | | | | | | | | Tested with SEGGER J-Link EDU, Flasher ARM and flash chip W25Q16.V. Change-Id: Ie03a054a75457ec9e1cab36ea124bb53b10e8d7e Signed-off-by: Marc Schink <flashrom-dev@marcschink.de> Reviewed-on: https://review.coreboot.org/c/28087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* usbdev: Extract libusb1 device discovery into a separate fileDaniel Thompson2018-08-301-0/+8
| | | | | | | | | | | | Currently there is a TODO-like comment in the dediprog driver: "Might be useful for other USB devices as well". Act on this comment by collecting all the device discovery code for libusb1 devices into a separate file. Change-Id: Idfcc79371241c2c1dea97faf5e532aa971546a79 Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-on: https://review.coreboot.org/27443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* programmer: Add Developerbox/CP2104 bit bang driverDaniel Thompson2018-08-171-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | The 96Boards Developerbox (a.k.a. Synquacer E-series) provides a CP2102 debug UART with its GPIO pins hooked up to the SPI NOR FLASH. The circuit is intended to provide emergency recovery functions without requiring any additional tools (such as a JTAG or SPI programmer). This was expected to be very slow (and it is) but CP2102 is much cheaper than a full dual channel USB comms chip. Read performance is roughly on par with a 2400 baud modem (between 60 and 70 minutes per megabyte if you prefer) and write performance is 50% slower still. The full recovery process, with backup and verification of 4MB data written takes between 14 and 15 hours. Thus it is only really practical as an emergency recovery tool, firmware developers will need to use an alternative programmer. Change-Id: I2547a96c1a2259ad0d52cd4b6ef42261b37cccf3 Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/26948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* bitbang_spi: Add functions to optimize xfersDaniel Thompson2018-08-171-0/+3
| | | | | | | | | | | | | | | | | | | | On systems where the overhead of getting/setting pins is much greater than the half period (for example, USB bit banging) it significantly boosts performance if we can bang more than one bit at the same time. Add support for setting sck at the same time as mosi or miso activity. The speed up varies depending on how much the overhead of getting/setting pins dominates execution time. For a USB bit bang driver running on a 7th generation Core i5, the time to probe drops from ~9.2 seconds to ~7.7 seconds when set_clk_set_mosi() is implemented. Change-Id: Ic3430a9df34844cdfa82e109456be788eaa1789a Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Reviewed-on: https://review.coreboot.org/26946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
* digilent_spi: add a driver for the iCEblink40 development boardLubomir Rintel2018-06-261-0/+12
| | | | | | | | | | | | | | | This is driver that supports the Lattice iCE40 evaluation kits. On the board is a SPI flash memory chip labeled ST 25P10VP. Tested to work read/write/erase with "-p digilent_spi -c M25P10" or with a patch that resets the part beforehands (in which case it gets detected as a M25P10-A and is way faster due to paged writes). Change-Id: I7ffcd9a2db4395816f0e8b6ce6c3b0d8e930c9e6 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/23338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* linux_mtd: Import driver from ChromiumOSDavid Hendricks2018-05-171-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This imports a series of patches from chromiumos for MTD support. The patches are squashed to ease review and original Change-Ids have been removed to avoid confusing Gerrit. There are a few changes to integrate the code: - Conflict resolution - Makefile changes - Remove file library usage from linux_mtd. We may revisit this and use it for other Linux interfaces later on. - Switch to using file stream functions for reads and writes. This consolidated patch is Signed-off-by: David Hendricks <dhendricks@fb.com> The first commit's message is: Initial MTD support This adds MTD support to flashrom so that we can read, erase, and write content on a NOR flash chip via MTD. BUG=chrome-os-partner:40208 BRANCH=none TEST=read, write, and erase works on Oak Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/272983 Reviewed-by: Shawn N <shawnn@chromium.org> This is the 2nd commit message: linux_mtd: Fix compilation errors This fixes compilation errors from the initial import patch. Signed-off-by: David Hendricks <dhendricks@fb.com> This is the 3rd commit message: linux_mtd: Suppress message if NOR device not found This just suppresses a message that might cause confusion for unsuspecting users. BUG=none BRANCH=none TEST=ran on veyron_mickey, "NOR type device not found" message no longer appears under normal circumstances. Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302145 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> This is the 4th commit message: linux_mtd: Support for NO_ERASE type devices Some mtd devices have the MTD_NO_ERASE flag set. This means these devices don't require an erase to write and might not have implemented an erase function. We should be conservative and skip erasing altogether, falling back to performing writes over the whole flash. BUG=b:35104688 TESTED=Zaius flash is now written correctly for the 0xff regions. Signed-off-by: William A. Kennington III <wak@google.com> Reviewed-on: https://chromium-review.googlesource.com/472128 Commit-Ready: William Kennington <wak@google.com> Tested-by: William Kennington <wak@google.com> Reviewed-by: Brian Norris <briannorris@chromium.org> This is the 5th commit message: linux_mtd: do reads in eraseblock-sized chunks It's probably not the best idea to try to do an 8MB read in one syscall. Theoretically, this should work; but MTD just relies on the SPI driver to deliver the whole read in one transfer, and many SPI drivers haven't been tested well with large transfer sizes. I'd consider this a workaround, but it's still good to have IMO. BUG=chrome-os-partner:53215 TEST=boot kevin; `flashrom --read ...` TEST=check for performance regression on oak BRANCH=none Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/344006 Reviewed-by: David Hendricks <dhendrix@chromium.org> This is the 6th commit message: linux_mtd: make read/write loop chunks consistent, and documented Theoretically, there should be no maximum size for the read() and write() syscalls on an MTD (well, except for the size of the entire device). But practical concerns (i.e., bugs) have meant we don't quite do this. For reads: Bug https://b/35573113 shows that some SPI-based MTD drivers don't yet handle very large transactions. So we artificially limit this to block-sized chunks. For writes: It's not clear there is a hard limit. Some drivers will already split large writes into smaller chunks automatically. Others don't do any splitting. At any rate, using *small* chunks can actually be a problem for some devices (b:35104688), as they get worse performance (doing an internal read/modify/write). This could be fixed in other ways by advertizing their true "write chunk size" to user space somehow, but this isn't so easy. As a simpler fix, we can just increase the loop increment to match the read loop. Per David, the original implementation (looping over page chunks) was just being paranoid. So this patch: * clarifies comments in linux_mtd_read(), to note that the chunking is somewhat of a hack that ideally can be fixed (with bug reference) * simplifies the linux_mtd_write() looping to match the structure in linux_mtd_read(), including dropping several unnecessary seeks, and correcting the error messages (they referred to "reads" and had the wrong parameters) * change linux_mtd_write() to align its chunks to eraseblocks, not page sizes Note that the "->page_size" parameter is still somewhat ill-defined, and only set by the upper layers for "opaque" flash. And it's not actually used in this driver now. If we could figure out what we really want to use it for, then we could try to set it appropriately. BRANCH=none BUG=b:35104688 TEST=various flashrom tests on Kevin TEST=Reading and writing to flash works on our zaius machines over mtd Change-Id: I3d6bb282863a5cf69909e28a1fc752b35f1b9599 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/505409 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-by: William Kennington <wak@google.com> Reviewed-on: https://review.coreboot.org/25706 Tested-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
* Remove address from GPLv2 headersElyes HAOUAS2018-04-241-4/+0
| | | | | | | | Change-Id: I7bfc339673cbf5ee2d2ff7564c4db04ca088d0a4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/25381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* buspirate_spi: Add support for variable serial speedsShawn Anastasio2018-01-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch sets the default baud rate for communication between the host device and the Bus Pirate for hardware versions 3.0 and greater to 2M baud. It also introduces the ability to manually set the baud rate via the added 'serialspeed' programmer parameter. This is done in two parts. Firstly, the requested serial speed is looked up in a table to determine the appropriate clock divisor and the divisor is sent to the bus pirate. Then, the system's baud rate for the selected serial port is set using serial.c's 'serialport_config'. This function's prototype had to be added to programmer.h. In testing, using the 2M baud rate was able to significantly decrease flash times (down from 20+ minutes to less than 2 minutes for an 8MB flash). Change-Id: I3706f17a94fdf056063f2ad4a5f0a219665cdcbf Signed-off-by: Shawn Anastasio <shawnanastasio@yahoo.com> Reviewed-on: https://review.coreboot.org/23057 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* spi_master: Introduce SPI_MASTER_4BA feature flagNico Huber2018-01-021-0/+13
| | | | | | | | | | | | | | | Add a feature flag SPI_MASTER_4BA to `struct spi_master` that advertises programmer-side support for 4-byte addresses in generic commands (and read/write commands if the master uses the default implementations). Set it for all masters that handle commands address-agnostic. Don't prefer native 4BA instructions if the master doesn't support them. Change-Id: Ife66e3fc49b9716f9c99cad957095b528135ec2c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* spi: Move ICH BBAR quirk out of the wayNico Huber2017-12-281-1/+0
| | | | | | | | | | | | | | | | | | | | | Get rid of the layering violations around ICH's BBAR. Move all the weird address handling into (surprise, surprise) `ichspi.c`. Might fix writes for the `BBAR != 0` case by accident. Background: Some ICHs have a BBAR (BIOS Base Address Configuration Register) that, if set, limits the valid address range to [BBAR, 2^24). Current code lifted addresses for REMS, RES and READ operations by BBAR, now we do it for all addresses in ichspi. Special care has to be taken if the BBAR is not aligned by the flash chip's size. In this case, the lower part of the chip (from BBAR aligned down, up to BBAR) is inacces- sible (this seems to be the original intend behind BBAR) and has to be left out in the address offset calculation. Change-Id: Icbac513c5339e8aff624870252133284ef85ab73 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/22396 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* chipset_enable: Add support for C620-series Lewisburg PCHDavid Hendricks2017-09-011-0/+1
| | | | | | | | | | | | | | | | This adds PCI IDs for C620-series PCHs and adds CHIPSET_C620_SERIES_LEWISBURG as a new entry in the ich_chipset enum. Lewisburg is very similar to Sunrise Point for Flashrom's purposes, however one important difference is the way the "number of masters" is interpreted from the flash descriptor (0-based vs. 1-based). There are also new flash regions defined. Change-Id: I96c89bc28bdfcd953229c17679f2c28f8b874d0b Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/20922 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* rpci: Use pci_dev struct pointer to avoid API breaksYouness Alaoui2017-08-101-0/+5
| | | | | | | | | | | | | | | | | | | | | | The pci_dev structure is never meant to be used as is, but always as a pointer. By using the struct itself in undo_pci_write_data, we are risking data corruption, or buffer overflows if the structure size changes. This is especially apparent on my system where flashrom segfaults because I compile it with pciutils 3.3.0 and I run it on a system with pciutils 3.5.2. The struture size is different and causes a struct with the wrong size to be sent to the library, with invalid internal field values. This has been discovered and discussed in Change ID 18925 [1] [1] https://review.coreboot.org/#/c/18925/ Change-Id: Icde2e587992ba964d4ff92c33aa659850ba06298 Signed-off-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net> Reviewed-on: https://review.coreboot.org/20784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
* chipset_enable: Add support for Intel Skylake / KabylakeNico Huber2017-07-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All publicly known Skylake / Kabylake / Sunrise Point PCH variants share the same register interface [1..6]. Although all SPI configu- ration is now done through the SPI PCI device 1f.5, we can't probe for it directly since its PCI vendor and device IDs are usually hid- den. To work around the hidden IDs, we use another PCI accessor that doesn't rely on the OS seeing the PCI device. This handles SPI flashes only. While booting from LPC is still sup- ported, it seems nobody uses it any more. Some additional PCI IDs were gathered from driveridentifier.com. TEST=Compiled with B150 set to NT (instead of BAD) and checked for sane register readings. [1] 6th Generation Intel® Core(TM) Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002EN Document Number 332995 [2] 6th Generation Intel® Processor I/O Datasheet for U/Y Platforms Volume 2 of 2 Revision 001EN Document Number 332996 [3] 7th Generation Intel® Processor Families I/O Platform Datasheet - Volume 1 of 2 Revision 002 Document Number 334658 [4] 7th Generation Intel® Processor Families I/O for U/Y Platforms Datasheet - Volume 2 of 2 Revision 002 Document Number 334659 [5] Intel® 100 Series and Intel® C230 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 1 of 2 Revision 004EN Document Number 332690 [6] Intel® 100 Series Chipset Family Platform Controller Hub (PCH) Datasheet - Volume 2 of 2 Revision 001EN Document Number 332691 Change-Id: I000819aff25fbe9764f33df85f040093b82cd948 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18925 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
* ichspi: Drop `dev` parameter from init functionsNico Huber2017-06-201-2/+2
| | | | | | | | | | | | It's never used and has no clear contract (e.g. will the pointer stay valid beyond the call?). Change-Id: I0d4e7cc731364e86eff214b9022b842a577f9ef4 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/19460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Handle Intel Wildcat Point *LP* like Lynx Point LPNico Huber2017-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | The subtle difference was ignored when adding these chipsets. The integrated Wildcat Point LP PCH is documented in [1]. I'm not sure how to account for "Broadwell H" which seems not publicly documented. Maybe it's an unreleased HM9*, in which case the non-LP path should be correct. [1] Mobile 5th Generation Intel® Core(TM) Processor Family I/O, Intel® Core(TM) M Processor Family I/O, Mobile Intel® Pentium® Processor Family I/O, and Mobile Intel® Celeron® Processor Family I/O Datasheet Revision 004 Document Number: 330837 Change-Id: I6b7ca3c0bde111b04ed7c745ed76d28d3d05f01c Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18883 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* hwaccess: Constify `addr` argument of MMIO read functionsNico Huber2017-04-251-7/+7
| | | | | | | | | | Change-Id: I1419241a8332b74103b3921df2c615bdf91346a7 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/18881 Tested-by: build bot (Jenkins) Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
* Make image parameter of cb_check_image constNico Huber2017-01-131-1/+1
| | | | | | | | | Change-Id: I811b3d6f1710154e055b03d5f27b1a8d9b3c0a43 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/17943 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* dediprog: use ordinary USB devs arrayStefan Tauner2016-02-221-0/+1
| | | | | | | | | | Even though there is currently only one USB device ID in the wild using our standard way to define the devices creates nicer output for -L and -z. Corresponding to flashrom svn r1942. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* pickit2_spi: use ordinary USB devs arrayStefan Tauner2016-02-221-0/+1
| | | | | | | | | | Even though there is currently only one USB device ID in the wild using our standard way to define the devices creates nicer output for -L and -z. Corresponding to flashrom svn r1941. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
* Add support for WCH CH341A as an SPI programmerUrja Rannikko2016-01-311-0/+13
| | | | | | | | Corresponding to flashrom svn r1921. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Urja Rannikko <urjaman@gmail.com>
* Add a bunch of new/tested stuff and various small changes 24Stefan Tauner2016-01-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - ASRock G31M-GS Reported by Александр Трубицын - ASRock G41M-VS3 Reported by Александр Трубицын - ASRock N68C-S UCC Reported by Alexey Belyaev - ASRock AMCP7AION-HT (ION 330HT(-BD)) Reported by Stefan Tauner - ASUS P5K SE Reported by Александр Трубицын - ASUS P5KPL-VM Reported by Marin Vlah - ASUS RAMPAGE III GENE Reported by stevessss on IRC - GIGABYTE GA-945GM-S2 Reported by Александр Трубицын - GIGABYTE GA-945GCM-S2 (rev. 3.0) Reported by Александр Трубицын - GIGABYTE GA-965P-S3 Reported by Александр Трубицын - GIGABYTE GA-EG43M-S2H Reported by Александр Трубицын - GIGABYTE GA-EP31-DS3L (rev. 1.0) Reported by Александр Трубицын - GIGABYTE GA-G33M-S2 Reported by Александр Трубицын - GIGABYTE GA-G33M-S2L Reported by Александр Трубицын - GIGABYTE GA-H55M-S2 Reported by Александр Трубицын - GIGABYTE GA-J1900N-D3V Reported by Marcos Truchado and Guillermo von Hünefeld - GIGABYTE GA-K8NS Reported by nicolae788 - GIGABYTE GA-M56S-S3 Reported by Estevo Paz Freire - GIGABYTE GA-P31-DS3L Reported by Александр Трубицын - GIGABYTE GA-P31-S3G Reported by Александр Трубицын - MSI MS-7336 Reported by Benjamin Bellec - MSI X79A-GD45 (8D) (MS-7760)" Reported by mortehu on IRC - Supermicro A1SAi-2550F Reported by Bernard Grymonpon - Supermicro X7DWT Reported by Steven Stremciuc Laptop: - ASUS U38N Reported by Ultra on IRC - Dell Latitude D630 Reported by Márton Miklós - Fujitsu Amilo Xi 3650 Reported by Elmar Stellnberger - Lenovo T400 (whitelisting only) Chipsets: - Mark 8086:1f38 (Intel Avoton/Rangeley) as tested Reported by Jeremy Porter and Bernard Grymonpon - Add Intel Sunrise Point IDs but no support yet. Flash chips: - Atmel AT45DB321D to PREW (+PREW) Reported by The Raven - Eon EN25QH32 to PREW (+PREW) Reported by Josua Mayer - Eon EN25QH64 to PREW (+EW) Reported by David s. Alessio - GigaDevice GD25LQ64(B) to PREW (+PREW) Reported by Greg Tippit - Intel 28F001BN/BX-T to PREW (+EW) Reported by Lu Xie - Micron M25P10-A to PREW (+W) Reported by the Raven - Micron M25PE40 Reported by David Wood - Micron N25Q128..3E to PREW (+PREW) Reported by Miklós Márton - Macronix MX25L3273E to PREW (+PREW) Reported by Roklobsta on IRC - Macronix MX23L6454 to PR (+PR) Reported by Steven Honeyman - Macronix MX25U6435E/F to PREW (+PREW) Reported by Marcos Truchado and Guillermo von Hünefeld - PMC Pm25LQ032C to PREW (+EW) Reported by Dirk Knop - Spansion S25FL016A to PREW (+EW) Reported by Márton Miklós - Spansion S25FL128S......0 to PREW (+PREW) Reported by Jim Houston - Spansion S25FL204K to PR (+PR) Reported by Thomas Debrunner - SST SST49LF016C to PREW (+EW) Reported by Steven Stremciuc - SST SST39VF040 to PREW (+PREW) Reported by Xavier Bourgeois - SST SST49LF040B to PREW (+EW) Reported by Rikard Åhlund - ST M25P10-A to PREW (+W) Reported by Martijn Schiedon - Winbond W39V040FA to PREW (+EW) Reported by Евгений Черкашин - Winbond W39V080FA to PREW (+EW) Reported by protagonist0 on IRC - Winbond W25Q80.W to PREW (+PREW) Reported by Miklós Márton - Winbond W25X64 to PREW (+REW) Reported by Johannes Krampf and Manuel Dejonghe - Fix ID of AMIC A25LQ64 Reported by Roman Titov - Fix page size of Spansion S25FL129P......1 Copy and paste error from the 128S uniform 256kB variant, probably. - Add Micron/Numonyx phase-change memory IDs Miscellaneous: - Detect Android target OS. No changes are required to build flashrom (excluding programmers with NEED_PCI) on Android. - Update rayerspi (spipgm) URL - Fix max_data_write handling of at45db. - Minor refinement of the README - Mark board enable for the GA-K8NS variants as tested. Tested by "nicolae788" on a board with socket 754. - Mark "Multi-system" chassis as non-laptop case. - Remove W836xx log requests. We got enough (and no one is looking at them for the time being anyway). - serprog: improve invalid reply error message, contributed by Urja Rannikko. - Remove default include paths for MinGW. - Disable implicit rules in the Makefile because we don't need them and they just make the build (imperceptibly) slower. - Enable our own strnlen() implementation not only on DJGPP but also if HAVE_STRNLEN is not defined. This is needed to get older BSDs (e.g. NetBSD 6.0, FreeBSD < 8.0) to work. - Tiny other stuff. Corresponding to flashrom svn r1917. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add atapromise programmerJoseph C. Lehner2016-01-161-0/+10
| | | | | | | | | | | | | | | | | | Supported controllers are Promise PDC20262 (FastTrak66/Ultra66), PDC20265 (FastTrak100 Lite/Ultra100), PDC20267 (FastTrak100/Ultra100). At least the Ultra100 only has address lines A0-A14 wired up, limiting addressable chip size to 32 kB. The flash chips mounted on those controllers usually is 128 kB, i.e. parts of the flash chip are inaccessible. As a workaround, the driver implicitly truncates the size of all flash chips to 32 kB. Works well for the factory installed flash. Do NOT use as a generic programmer for chips >32 kB. Corresponding to flashrom svn r1916. Signed-off-by: Joseph C. Lehner <joseph.c.lehner@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Urja Rannikko <urjaman@gmail.com>
* serprog: allow to omit specifying a baud rateStefan Tauner2016-01-041-3/+1
| | | | | | | | | | | On USB-based serial connections (VCP) the requested baud rate usually does not matter (much). Remove the arbitrary restriction and use whatever default values the OS/hardware provides. Corresponding to flashrom svn r1907. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Urja Rannikko <urjaman@gmail.com>
* serprog: Fix FWH/LPC by implementing serprog_mapUrja Rannikko2015-06-291-0/+1
| | | | | | | | | | | | | The serprog protocol does only transmit 24 bit-wide address and ignores the top 8 bit. This is fine as long as the underlying hardware ignores the latter anyway (which is the case for parallel chips that even lack the respective pins). FWH/LPC chips, however, operate on a full 32-bit (LPC) or 28-bit (FWH) address space and would fail with the fallback mapping to NULL. Corresponding to flashrom svn r1895. Signed-off-by: Urja Rannikko <urjaman@gmail.com> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add support for the Microchip PICkit2 as an SPI programmerJustin Chevrier2015-02-081-0/+11
| | | | | | | | | | | | | | | This patch was inspired by the code in AVRDude (open source Atmel AVR programmer) to support the PICkit2 written by Doug Brown [1]. The Dediprog code in flashrom was used as the template for this code with some reference to the ft2232 code as well. [1] - https://github.com/steve-m/avrdude/blob/master/pickit2.c Corresponding to flashrom svn r1881. Signed-off-by: Justin Chevrier <jchevrier@gmail.com> Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Add a bunch of new/tested stuff and various small changes 22Stefan Tauner2015-02-081-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tested mainboards: OK: - AOpen UK79G-1394 (used in EZ18 barebones) Reported by Lawrence Gough - ASUS M4N78 SE Reported by Dima Veselov - ASUS P5LD2-VM Mark board enable as tested (reported by Dima Veselov) - GIGABYTE GA-970A-UD3P (rev. 2.0) Reported by trucmar on IRC - GIGABYTE GA-990FXA-UD3 (rev. 4.0) Reported by ROKO__ on IRC - GIGABYTE GA-H77-DS3H (rev. 1.1) Reported by Evgeniy Edigarev - GIGABYTE GA-P55-USB3 (rev. 2.0) Reported by Måns Thörnqvist - MSI MS-7817 (H81M-E33) Reported by Igor Kolker Chipsets: - Marked Intel Bay Trail (0x0f1c) as tested OK Reported by Antonio Ospite - Refine Intel IDs * Add IDs for Braswell * Add IDs for 9 Series PCHs (e.g. H97, Z97) * Rename Wellsburg devices slightly Flash chips: - Atmel AT25DF041A to PREW (+PREW) Reported by Tai-hwa Liang - Atmel AT26DF161 to PREW (+EW) Reported by Steve Shenton - Atmel AT45DB011D to PREW (+PREW) Reported by The Raven - Atmel AT45DB642D to PREW (+PREW) Reported by Mahesh Mokal - Eon EN25F32 to PREW (+PREW) Reported by Arman Khodabande - Eon EN25F40 to PREW (+REW) Reported by Jerrad Pierce - Eon EN25QH16 to PREW (+EW) Reported by Ben Johnson - GigaDevice GD25Q20(B) to PREW (+PREW) Reported by Gilles Aurejac - Macronix MX25U6435E/F to PR (+PR) Reported by Matt Taggart - PMC Pm25LV512(A) to PREW (+PREW) Reported by The Raven - SST SST39VF020 to PREW (+PREW) Reported by Urja Rannikko - Winbond W25Q40.V to PREW (+EW) Reported by Torben Nielsen - Add E variants of MX25Lx006 (MX25L2006E, MX25L4006E, MX25L8006E). - Add MX25L6465E variant. - There was never a MX25L12805 AFAICT. - Split MX25L12805 from models with the same ID but an additional 32 kB eraser: MX25L12835F/MX25L12845E/MX25L12865E. - Add a bunch of ST parallel NOR flash chip IDs. Miscellaneous: - Whitelist ThinkPad X200. - Constify master parameter of register_master(). - Remove FEATURE_BYTEWRITES because it was never used at all. - Refine hwseq messages and make them less prominent. - Fix the yet unused PRIxCHIPADDR format string thingy. - Fix copy&paste error in spi_prettyprint_status_register_bp(). Spotted by Pablo Cases. - Add an additional SMBus controller revision to identify another Yangtze model. Thanks to Dan Christensen for reporting this issue. - dediprog: add missing include for stdlib.h. This fixes (at least) building on FreeBSD and DragonflyBSD with gcc. - Remove references to struct pci_filter from programmer.h. It is only needed in internal.c where it has a complete type. Having it in programmer.h provokes a warning by some old versions of gcc. - Tiny other stuff. Corresponding to flashrom svn r1879. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
* Unify target OS and CPU architecture checksStefan Tauner2015-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | We do CPU architecture checks once for the makefile in arch.h and once for HW access abstraction in hwaccess.c. This patch unifies related files so that they can share the checks to improve maintainability and reduce the chance of inconsistencies. Furthermore, it refines some of the definitions, which - adds "support" for AARCH64 and PPC64, - adds big-endian handling on arm as well as LE handling on PPC64, - fixes compilation of internal.c on AARCH64 and PPC64. Additionally, this patch continues to unify all OS checks in flashrom by adding a new helper macro IS_WINDOWS. The old header file for architecture checking is renamed to platform.h to reflect its broader scope and all new macros are add in there. Corresponding to flashrom svn r1864. Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at> Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
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