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| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-07-20 18:51:29 +0800 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-07-20 12:09:21 +0100 |
| commit | 0858ed035a85c3ae79553200d2d818797cf849f5 (patch) | |
| tree | 5f3d1a3411d43dedad1543aab611a73b5817dad4 /arch/mips | |
| parent | 023087324000ae704cf3cfd0abf1fc30c6e0e8d5 (diff) | |
| download | linux-stable-0858ed035a85c3ae79553200d2d818797cf849f5.tar.gz linux-stable-0858ed035a85c3ae79553200d2d818797cf849f5.tar.bz2 linux-stable-0858ed035a85c3ae79553200d2d818797cf849f5.zip | |
irqchip/loongson-liointc: Add ACPI init support
LIOINTC stands for "Legacy I/O Interrupts" that described in Section
11.1 of "Loongson 3A5000 Processor Reference Manual". For more
information please refer Documentation/loongarch/irq-chip-model.rst.
Co-developed-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Jianmin Lv <lvjianmin@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/1658314292-35346-11-git-send-email-lvjianmin@loongson.cn
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/include/asm/mach-loongson64/irq.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-loongson64/irq.h b/arch/mips/include/asm/mach-loongson64/irq.h index 55e0dee12cb0..67c15f320f93 100644 --- a/arch/mips/include/asm/mach-loongson64/irq.h +++ b/arch/mips/include/asm/mach-loongson64/irq.h @@ -9,6 +9,7 @@ #define NR_IRQS (NR_IRQS_LEGACY + NR_MIPS_CPU_IRQS + NR_MAX_CHAINED_IRQS + 256) #define MAX_IO_PICS 1 #define MIPS_CPU_IRQ_BASE NR_IRQS_LEGACY +#define GSI_MIN_CPU_IRQ 0 #include <asm/mach-generic/irq.h> |