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| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-06-01 11:39:08 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-06-13 16:15:04 -0700 |
| commit | e88c533d8a2a0fe84bb54cff1569bd079ad3512c (patch) | |
| tree | 5027561d0cdc7836511ba76338dd05140085976a /drivers/clk | |
| parent | 501624339466a7896bb8a1f048cf8dcfd54b174e (diff) | |
| download | linux-stable-e88c533d8a2a0fe84bb54cff1569bd079ad3512c.tar.gz linux-stable-e88c533d8a2a0fe84bb54cff1569bd079ad3512c.tar.bz2 linux-stable-e88c533d8a2a0fe84bb54cff1569bd079ad3512c.zip | |
clk: qcom: gcc-sm6115: Add missing PLL config properties
When the driver was ported upstream, PLL ctl register values were omitted.
Add them to ensure the PLLs are fully configured like we expect them to.
Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Iskren Chernev <me@iskren.info>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230601-topic-alpha_ctl-v1-2-b6a932dfcf68@linaro.org
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/gcc-sm6115.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/qcom/gcc-sm6115.c b/drivers/clk/qcom/gcc-sm6115.c index 5f09aefa7fb9..033e308ff865 100644 --- a/drivers/clk/qcom/gcc-sm6115.c +++ b/drivers/clk/qcom/gcc-sm6115.c @@ -119,6 +119,8 @@ static const struct alpha_pll_config gpll10_config = { .vco_mask = GENMASK(21, 20), .main_output_mask = BIT(0), .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, + .test_ctl_hi_mask = 0x1, }; static struct clk_alpha_pll gpll10 = { @@ -170,6 +172,8 @@ static const struct alpha_pll_config gpll11_config = { .vco_val = 0x2 << 20, .vco_mask = GENMASK(21, 20), .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, + .test_ctl_hi_mask = 0x1, }; static struct clk_alpha_pll gpll11 = { @@ -362,6 +366,8 @@ static const struct alpha_pll_config gpll8_config = { .post_div_val = 0x1 << 8, .post_div_mask = GENMASK(11, 8), .config_ctl_val = 0x4001055b, + .test_ctl_hi1_val = 0x1, + .test_ctl_hi_mask = 0x1, }; static struct clk_alpha_pll gpll8 = { @@ -413,6 +419,8 @@ static const struct alpha_pll_config gpll9_config = { .post_div_mask = GENMASK(9, 8), .main_output_mask = BIT(0), .config_ctl_val = 0x00004289, + .test_ctl_mask = GENMASK(31, 0), + .test_ctl_val = 0x08000000, }; static struct clk_alpha_pll gpll9 = { |