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| author | Oleksij Rempel <o.rempel@pengutronix.de> | 2023-01-31 09:46:38 +0100 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@linaro.org> | 2023-01-31 14:45:16 +0200 |
| commit | 5f82bfced6118450cb9ea3f12316568f6fac10ab (patch) | |
| tree | bed899bfa9b1228d9e80300fa0b59c5667cfeb8b /include/dt-bindings/clock | |
| parent | 7757731053406dd00ad39fd136092ff05ec6fffe (diff) | |
| download | linux-stable-5f82bfced6118450cb9ea3f12316568f6fac10ab.tar.gz linux-stable-5f82bfced6118450cb9ea3f12316568f6fac10ab.tar.bz2 linux-stable-5f82bfced6118450cb9ea3f12316568f6fac10ab.zip | |
clk: imx6ul: fix enet1 gate configuration
According to the "i.MX 6UltraLite Applications Processor Reference Manual,
Rev. 2, 03/2017", BIT(13) is ENET1_125M_EN which is not controlling root
of PLL6. It is controlling ENET1 separately.
So, instead of this picture (implementation before this patch):
fec1 <- enet_ref (divider) <---------------------------,
|- pll6_enet (gate)
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
we should have this one (after this patch):
fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-,
|- pll6_enet
fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´
With this fix, the RMII reference clock will be turned off, after
setting network interface down on each separate interface
(ip l s dev eth0 down). Which was not working before, on system with both
FECs enabled.
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230131084642.709385-16-o.rempel@pengutronix.de
Diffstat (limited to 'include/dt-bindings/clock')
| -rw-r--r-- | include/dt-bindings/clock/imx6ul-clock.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/dt-bindings/clock/imx6ul-clock.h b/include/dt-bindings/clock/imx6ul-clock.h index 79094338e6f1..b44920f1edb0 100644 --- a/include/dt-bindings/clock/imx6ul-clock.h +++ b/include/dt-bindings/clock/imx6ul-clock.h @@ -256,7 +256,8 @@ #define IMX6UL_CLK_GPIO4 247 #define IMX6UL_CLK_GPIO5 248 #define IMX6UL_CLK_MMDC_P1_IPG 249 +#define IMX6UL_CLK_ENET1_REF_125M 250 -#define IMX6UL_CLK_END 250 +#define IMX6UL_CLK_END 251 #endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ |