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author | Felipe Balbi <felipe.balbi@linux.intel.com> | 2018-09-07 09:16:51 +0300 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2018-09-28 12:47:34 -0500 |
commit | d6112f8def514e019658bcc9b57d53acdb71ca3f (patch) | |
tree | 1d2666a9f462e87b0d27038a2c8e15d4a8f8e2dd /include/linux/pci.h | |
parent | bad7dcd94f3956bcfc0a69ef71fdf0fcca3de4a8 (diff) | |
download | linux-stable-d6112f8def514e019658bcc9b57d53acdb71ca3f.tar.gz linux-stable-d6112f8def514e019658bcc9b57d53acdb71ca3f.tar.bz2 linux-stable-d6112f8def514e019658bcc9b57d53acdb71ca3f.zip |
PCI: Add support for Immediate Readiness
PCIe r4.0, sec 7.5.1.1.4 defines a new bit in the Status Register:
Immediate Readiness – This optional bit, when Set, indicates the Function
is guaranteed to be ready to successfully complete valid configuration
accesses at any time following any reset that the host is capable of
issuing Configuration Requests to this Function.
When this bit is Set, for accesses to this Function, software is exempt
from all requirements to delay configuration accesses following any type
of reset, including but not limited to the timing requirements defined in
Section 6.6.
This means that all delays after a Conventional or Function Reset can be
skipped.
This patch reads such bit and caches its value in a flag inside struct
pci_dev to be checked later if we should delay or can skip delays after a
reset. While at that, also move the explicit msleep(100) call from
pcie_flr() and pci_af_flr() to pci_dev_wait().
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
[bhelgaas: rename PCI_STATUS_IMMEDIATE to PCI_STATUS_IMM_READY]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'include/linux/pci.h')
-rw-r--r-- | include/linux/pci.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/pci.h b/include/linux/pci.h index 6925828f9f25..60da5d7d4310 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -325,6 +325,7 @@ struct pci_dev { pci_power_t current_state; /* Current operating state. In ACPI, this is D0-D3, D0 being fully functional, and D3 being off. */ + unsigned int imm_ready:1; /* Supports Immediate Readiness */ u8 pm_cap; /* PM capability offset */ unsigned int pme_support:5; /* Bitmask of states from which PME# can be generated */ |