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| * | | riscv: errata: Add StarFive JH7100 errataEmil Renner Berthing2023-12-131-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This not really an errata, but since the JH7100 was made before the standard Zicbom extension it needs the DMA_GLOBAL_POOL and RISCV_NONSTANDARD_CACHE_OPS enabled to work correctly. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | soc: sifive: ccache: Add StarFive JH7100 supportEmil Renner Berthing2023-11-221-2/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the StarFive JH7100 SoC which also features this SiFive cache controller. The JH7100 has non-coherent DMAs but predate the standard RISC-V Zicbom exension, so instead we need to use this cache controller for non-standard cache management operations. Unfortunately the interrupt for uncorrected data is broken on the JH7100 and fires continuously, so add a quirk to not register a handler for it. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatibleEmil Renner Berthing2023-11-221-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cache controller is also used on the StarFive JH7100 SoC. Unfortunately it needs a quirk to work properly, so add dedicated compatible string to be able to match it. Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | soc: sifive: shunt ccache driver to drivers/cacheConor Dooley2023-11-228-23/+15
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the ccache driver over to drivers/cache, out of the drivers/soc dumping ground, to this new collection point for cache controller drivers. Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Tested-by: Samuel Holland <samuel.holland@sifive.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* | | Merge tag 'riscv-soc-drivers-for-v6.8' of ↵Arnd Bergmann2023-12-2213-3/+559
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/drivers RISC-V SoC drivers for v6.8 There's only one set of changes here, the addition of "Auto Update" support for PolarFire SoC. Auto Update is one of the ways that the FPGA bitstream can be updated, and the only one suitable for use from Linux as it does not immediately initiate a reboot when started. The driver was not accepted in the FPGA manager subsystem as the update only occurs after a reboot and makes no use of the FPGA manager framework. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-soc-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: MAINTAINERS: add auto-update driver to mpfs entry firmware: microchip: Replace of_device.h with explicit include firmware: microchip: add PolarFire SoC Auto Update support soc: microchip: mpfs: add auto-update subdev to system controller soc: microchip: mpfs: print service status in warning message soc: microchip: mpfs: enable access to the system controller's flash dt-bindings: soc: microchip: add a property for system controller flash firmware_loader: Expand Firmware upload error codes with firmware invalid error Link: https://lore.kernel.org/r/20231221-droop-unblock-81e4fe14acee@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | MAINTAINERS: add auto-update driver to mpfs entryConor Dooley2023-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rob's scripts were broken by the lack of a maintainer for this file, while trying to fix an integration issue in linux-next. Add it to the existing entry for PolarFire SoC drivers so that when the next bug is found the contributor knows where to send it. Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | firmware: microchip: Replace of_device.h with explicit includeRob Herring2023-12-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. Soon the implicit includes are going to be removed. of_device.h isn't needed, but platform_device.h is. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | firmware: microchip: add PolarFire SoC Auto Update supportConor Dooley2023-12-065-0/+511
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Auto Update reprogramming of the FPGA fabric on PolarFire SoC, using the fw_upload mechanism a la the intel-m10-bmc-sec-update driver. This driver only writes the image to the spi flash & performs validation on it, as the entire FPGA becomes unusable during the actual reprogramming of a bitstream. To initiate the reprogramming itself, a device reset is required. The SBI SRST extension's "cold reboot" can trigger such a device reset, provided corresponding support has been enabled in the HSS (Hart Software Services), the provider of SBI runtime services on PolarFire SoC. While this is a driver responsible for the reprogramming of an FPGA, there is no dynamic discovery of devices involved, as runtime reconfiguration is not possible due to the device reset requirements. Therefore FPGA manager subsystem is not used by this driver and the FPGA subsystem maintainers were unwilling to accept it there. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | soc: microchip: mpfs: add auto-update subdev to system controllerConor Dooley2023-12-061-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PolarFire SoC's system controller offers the ability to re-program the FPGA from a user application via two, related, mechanisms. In-Application Programming (IAP) is not ideal for use in Linux, as it will immediately take down the system when requested. Auto Update is preferred, as it will only take affect at device power up*, allowing the OS (and potential applications in AMP) to be shut down gracefully. * Auto Update occurs at device initialisation, which can also be triggered by device reset - possible with the v2023.02 version of the Hart Software Services (HSS) and reference design. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | soc: microchip: mpfs: print service status in warning messageConor Dooley2023-12-061-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that resp_status is set for failed services, print the status in the error path's warning. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | soc: microchip: mpfs: enable access to the system controller's flashConor Dooley2023-12-063-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The system controller has a flash that contains images used to reprogram the FPGA using IAP (In-Application Programming). Introduce a function that allows a driver with a reference to the system controller to get one to a flash device attached to it. Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | dt-bindings: soc: microchip: add a property for system controller flashConor Dooley2023-12-061-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The system controller "shares" a SPI flash device with a QSPI controller in the MSS. This flash is used to store FPGA bitstreams & other metadata. IAP and Auto Upgrade both write images to this flash that the System Controller will use to re-program the FPGA. Add a phandle property signifying which flash device is connected to the system controller. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
| * | | firmware_loader: Expand Firmware upload error codes with firmware invalid errorKory Maincent2023-11-243-0/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No error code are available to signal an invalid firmware content. Drivers that can check the firmware content validity can not return this specific failure to the user-space Expand the firmware error code with an additional code: - "firmware invalid" code which can be used when the provided firmware is invalid Sync lib/test_firmware.c file accordingly. Acked-by: Luis Chamberlain <mcgrof@kernel.org> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Simon Horman <horms@kernel.org> Link: https://lore.kernel.org/r/20231122-feature_firmware_error_code-v3-1-04ec753afb71@bootlin.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
* | | Merge tag 'amlogic-drivers-for-v6.8' of ↵Arnd Bergmann2023-12-221-11/+8
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux into soc/drivers Amlogic drivers changes for v6.8: - meson-sm: unmap out_base shmem in error path - meson-sm: use dev_groups attrs for sysfs entries * tag 'amlogic-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux: firmware: meson-sm: unmap out_base shmem in error path firmware: meson_sm: refactor serial sysfs entry via dev_groups attrs Link: https://lore.kernel.org/r/a987f881-1c23-4528-9cb1-e5a875b7e7a8@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | firmware: meson-sm: unmap out_base shmem in error pathEvgeny Bachinin2023-11-271-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When SM driver was introduced in [1], the code flow did not require to unmap out_base shmem in case of errors inside probe(). During [2], the additional error path appeared, which requires unmap. Patch adds iounmap() missed. Links: [1] https://lore.kernel.org/linux-amlogic/1466339944-602-2-git-send-email-carlo@caione.org/ [2] https://lore.kernel.org/linux-amlogic/1532613556-5398-1-git-send-email-narmstrong@baylibre.com/ Fixes: 0789724f86a5 ("firmware: meson_sm: Add serial number sysfs entry") Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231108125604.162383-3-EABachinin@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
| * | | firmware: meson_sm: refactor serial sysfs entry via dev_groups attrsEvgeny Bachinin2023-11-271-8/+3
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce just another way to register sysfs serial entry: the less code, the better in the absence of extra error-paths Signed-off-by: Evgeny Bachinin <EABachinin@salutedevices.com> Acked-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20231108125604.162383-2-EABachinin@salutedevices.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
* | | Merge tag 'mvebu-drivers-6.8-1' of ↵Arnd Bergmann2023-12-221-1/+8
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/drivers mvebu drivers for 6.8 (part 1) moxtet bus fixes * tag 'mvebu-drivers-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: bus: moxtet: Add spi device table bus: moxtet: Mark the irq as shared Link: https://lore.kernel.org/r/87il4sbym0.fsf@BL-laptop Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | bus: moxtet: Add spi device tableSjoerd Simons2023-12-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The moxtet module fails to auto-load on. Add a SPI id table to allow it to do so. Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Cc: <stable@vger.kernel.org> Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
| * | | bus: moxtet: Mark the irq as sharedSjoerd Simons2023-12-151-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Turris Mox shares the moxtet IRQ with various devices on the board, so mark the IRQ as shared in the driver as well. Without this loading the module will fail with: genirq: Flags mismatch irq 40. 00002002 (moxtet) vs. 00002080 (mcp7940x) Signed-off-by: Sjoerd Simons <sjoerd@collabora.com> Cc: <stable@vger.kernel.org> # v6.2+ Reviewed-by: Marek Behún <kabel@kernel.org> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* | | Merge tag 'samsung-drivers-6.8' of ↵Arnd Bergmann2023-12-2225-68/+3285
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers Samsung SoC driver changes for v6.8 1. Add support for Google GS101 SoC to different drivers: clock controller, serial and watchdog. The clock driver changes depend on few bindings headers, which I put in a topic branch with the bindings refactoring and GS101 support, therefore this this pull request includes that bindings topic branch. The rest of the bindings topic branch is not necessary here, however keeping everything together makes it easier to share between branches. The bindings topic branch is mostly refactoring all the compatibles to add SoC-specific compatible followed by fallback. 2. Exynos ChipID: recognize ExynosAutov920. * tag 'samsung-drivers-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (40 commits) dt-bindings: clock: google,gs101: rename CMU_TOP gate defines watchdog: s3c2410_wdt: Add support for Google gs101 SoC watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support clk: samsung: clk-pll: Add support for pll_{0516,0517,518} dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffix dt-bindings: soc: samsung: usi: add google,gs101-usi compatible dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property dt-bindings: serial: samsung: Add google-gs101-uart compatible dt-bindings: watchdog: Document Google gs101 watchdog bindings dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enum dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101 dt-bindings: clock: Add Google gs101 clock management unit bindings dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible dt-bindings: watchdog: samsung: add specific compatible for Tesla FSD dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSD dt-bindings: serial: samsung: add specific compatible for Tesla FSD dt-bindings: pwm: samsung: add specific compatible for Tesla FSD ... Link: https://lore.kernel.org/r/20231220084722.22149-1-krzysztof.kozlowski@linaro.org Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | dt-bindings: clock: google,gs101: rename CMU_TOP gate definesTudor Ambarus2023-12-182-152/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gs101 clock defines from the bindings header are derived from the clock register names found in the datasheet under some certain rules. The CMU TOP gate clock defines missed to include the required "CMU" differentiator which will cause collisions with the gate clock defines of other clock units. Rename the TOP gate clock defines to include "CMU". Update the clock driver to use the new defines in order to not break compilation and bisect-ability. There are no device trees that use the previous defines. Fixes: 0a910f160638 ("dt-bindings: clock: Add Google gs101 clock management unit bindings") Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231218064333.479885-1-tudor.ambarus@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| * | | watchdog: s3c2410_wdt: Add support for Google gs101 SoCPeter Griffin2023-12-131-4/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the compatibles and drvdata for the Google gs101 SoC found in Pixel 6, Pixel 6a & Pixel 6 pro phones. Similar to Exynos850 it has two watchdog instances, one for each cluster and has some control bits in PMU registers. gs101 also has the dbgack_mask bit in wtcon register, so we also enable QUIRK_HAS_DBGACK_BIT. Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20231211162331.435900-13-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| * | | watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macroPeter Griffin2023-12-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the remaining QUIRK macros to use the BIT macro. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-12-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| * | | watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bitPeter Griffin2023-12-131-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The WDT uses the CPU core signal DBGACK to determine whether the SoC is running in debug mode or not. If the DBGACK signal is asserted and DBGACK_MASK bit is enabled, then WDT output and interrupt is masked (disabled). Presence of the DBGACK_MASK bit is determined by adding a new QUIRK_HAS_DBGACK_BIT quirk. Also update to use BIT macro to avoid checkpatch --strict warnings. Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-11-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| * | | tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_dataPeter Griffin2023-12-121-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add serial driver data for Google Tensor gs101 SoC and a common fifoszdt_serial_drv_data that can be used by platforms that specify the samsung,uart-fifosize DT property. A corresponding dt-bindings patch updates the yaml to ensure samsung,uart-fifosize is a required property. Tested-by: Will McVicker <willmcvicker@google.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-14-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| * | | clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm supportPeter Griffin2023-12-122-0/+2512
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cmu_top is the top level clock management unit which contains PLLs, muxes, dividers and gates that feed the other clock management units. cmu_misc clocks IPs such as Watchdog and cmu_apm clocks ips part of the APM module. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Will McVicker <willmcvicker@google.com> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-9-peter.griffin@linaro.org [krzysztof: drop not needed linux/of_device.h include] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| * | | clk: samsung: clk-pll: Add support for pll_{0516,0517,518}Peter Griffin2023-12-122-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These plls are found in the Tensor gs101 SoC found in the Pixel 6. pll0516x: Integer PLL with high frequency pll0517x: Integer PLL with middle frequency pll0518x: Integer PLL with low frequency PLL0516x FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) PLL0517x and PLL0518x FOUT = (MDIV * FIN)/PDIV*2^SDIV) The PLLs are similar enough to pll_0822x that the same code can handle both. The main difference is the change in the fout formula for the high frequency 0516 pll. Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor. MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x. When defining the PLL the "con" parameter should be set to CON3 register, like this PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Will McVicker <willmcvicker@google.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-8-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| * | | Merge tag 'samsung-dt-bindings-refactoring-and-google-gs101-6.8' into ↵Krzysztof Kozlowski2023-12-1218-56/+667
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/drivers Samsung Devicetree bindings topic branch for v6.8 Topic branch collecting several changes to Samsung SoC Devicetree bindings: 1. Add specific compatibles to all Samsung Exynos and Tesla FSD blocks, because that's what guidelines expect [1] and is generally recommended practice. Existing compatibles are left untouched, thus no driver changes are needed. The work only cleans things up, so any future contributions will use recommended style: specific and fallback compatibles. 2. Add bindings for new devices: Samsung ExynosAutov920 and Google GS101. These bindings are needed for both DTS and drivers, e.g. clock drivers.
| | * | | dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffixPeter Griffin2023-12-121-59/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 166 was skipped by mistake and two clocks: * CLK_MOUT_CMU_HSI0_USBDPDGB * CLK_GOUT_HSI0_USBDPDGB Have an incorrect DGB ending instead of DBG. This is an ABI break, but as the patch was only applied yesterday this header has never been in an actual release so it seems better to fix this early than ignore it. Fixes: 0a910f160638 ("dt-bindings: clock: Add Google gs101 clock management unit bindings") Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: André Draszik <andre.draszik@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-7-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: soc: samsung: usi: add google,gs101-usi compatibleTudor Ambarus2023-12-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add google,gs101-usi dedicated compatible for representing USI of Google GS101 SoC. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-6-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: serial: samsung: Make samsung,uart-fifosize a required propertyPeter Griffin2023-12-121-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Specifying samsung,uart-fifosize in both DT and driver static data is error prone and relies on driver probe order and dt aliases to be correct. Additionally on many Exynos platforms these are (USI) universal serial interfaces which can be uart, spi or i2c, so it can change per board. For google,gs101-uart make samsung,uart-fifosize a required property. For this platform fifosize now *only* comes from DT. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-5-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: serial: samsung: Add google-gs101-uart compatiblePeter Griffin2023-12-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dedicated google-gs101-uart compatible to the dt-schema for representing uart of the Google Tensor gs101 SoC. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-4-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: watchdog: Document Google gs101 watchdog bindingsPeter Griffin2023-12-121-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the "google,gs101-wdt" compatible to the dt-schema documentation. gs101 SoC has two CPU clusters and each cluster has its own dedicated watchdog timer (similar to exynos850 and exynosautov9 SoCs). These WDT instances are controlled using different bits in PMU registers. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231211162331.435900-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enumKrzysztof Kozlowski2023-12-111-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to create a new enum every time we bring-up new SoC. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231210134834.43943-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to ↵Peter Griffin2023-12-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GS101 GS101 has three different SYSREG controllers, add dedicated compatibles for them to the documentation. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231209233106.147416-4-peter.griffin@linaro.org [krzysztof: move Google entries to existing enum] Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: clock: Add Google gs101 clock management unit bindingsPeter Griffin2023-12-102-0/+498
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide dt-schema documentation for Google gs101 SoC clock controller. Currently this adds support for cmu_top, cmu_misc and cmu_apm. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20231209233106.147416-3-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatiblePeter Griffin2023-12-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add gs101-pmu compatible to the bindings documentation. Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org> Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Link: https://lore.kernel.org/r/20231209233106.147416-2-peter.griffin@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: watchdog: samsung: add specific compatible for Tesla FSDKrzysztof Kozlowski2023-12-071-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231205092229.19135-6-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSDKrzysztof Kozlowski2023-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231205092229.19135-5-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: serial: samsung: add specific compatible for Tesla FSDKrzysztof Kozlowski2023-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231205092229.19135-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: pwm: samsung: add specific compatible for Tesla FSDKrzysztof Kozlowski2023-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231205092229.19135-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: i2c: exynos5: add specific compatible for Tesla FSDKrzysztof Kozlowski2023-12-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tesla FSD is a derivative of Samsung Exynos SoC, thus just like the others it reuses several devices from older designs. Historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add Tesla FSD compatible specific to be used with an existing fallback. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231205092229.19135-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: hwinfo: samsung,exynos-chipid: add exynosautov920 compatibleJaewon Kim2023-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add "samsung,exynosautov920-chipid" compatible string to binding document. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231115095609.39883-9-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: arm: samsung: Document exynosautov920 SADK board bindingJaewon Kim2023-11-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add binding for the ExynosAutov920 SADK(Samsung Automotive Development Kit) board. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231115095609.39883-8-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: pwm: samsung: add exynosautov920 compatibleJaewon Kim2023-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add samsung,exynosautov920-pwm compatible string to binding document. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231115095609.39883-6-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: serial: samsung: add exynosautov920-uart compatibleJaewon Kim2023-11-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add samsung,exynosautov9-uart dedicated compatible for representing uart of ExynosAutov920 SoC. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231115095609.39883-5-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: samsung: usi: add exynosautov920-usi compatibleJaewon Kim2023-11-151-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add samsung,exynosautov920-usi dedicated compatible for representing USI of ExynosAutoV920 SoC. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231115095609.39883-4-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: samsung: exynos-pmu: add exynosautov920 compatibleJaewon Kim2023-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add samsung,exynosautov920-pmu compatible for representing pmu of ExynosAutov920 SoC. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231115095609.39883-3-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: samsung: exynos-sysreg: add exynosautov920 sysregJaewon Kim2023-11-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add compatible for ExynosAutov920 sysreg controllers. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Link: https://lore.kernel.org/r/20231115095609.39883-2-jaewon02.kim@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
| | * | | dt-bindings: pwm: samsung: add specific compatibles for existing SoCKrzysztof Kozlowski2023-11-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Samsung Exynos SoC reuses several devices from older designs, thus historically we kept the old (block's) compatible only. This works fine and there is no bug here, however guidelines expressed in Documentation/devicetree/bindings/writing-bindings.rst state that: 1. Compatibles should be specific. 2. We should add new compatibles in case of bugs or features. Add compatibles specific to each SoC in front of all old-SoC-like compatibles. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Link: https://lore.kernel.org/r/20231108104343.24192-13-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 09:18:43 +0000