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path: root/drivers/clk/sprd
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*-. Merge branches 'clk-debugfs', 'clk-spreadtrum', 'clk-sifive', 'clk-counted' a...Stephen Boyd2023-10-303-17/+42
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| | * clk: sprd: Composite driver support offset configZhifeng Tang2023-10-233-17/+42
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* / clk: sprd: Fix thm_parents incorrect configurationZhifeng Tang2023-09-111-1/+1
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* clk: Explicitly include correct DT includesRob Herring2023-07-193-3/+3
* clk: sprd: composite: Simplify determine_rate implementationStephen Boyd2023-06-143-25/+3
* clk: sprd: composite: Switch to determine_rateMaxime Ripard2023-06-081-5/+11
* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2023-04-291-1/+1
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| * clk: Use of_property_present() for testing DT property presenceRob Herring2023-03-141-1/+1
* | clk: sprd: set max_register according to mapping rangeChunyan Zhang2023-03-161-3/+6
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* clk: sprd: Add dependency for SPRD_UMS512_CLKCixi Geng2023-02-101-0/+2
*-. Merge branches 'clk-fixed-rate', 'clk-spreadtrum', 'clk-pxa' and 'clk-ti' int...Stephen Boyd2022-10-043-0/+2209
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| | * clk: sprd: Add clocks support for UMS512Cixi Geng2022-09-303-0/+2209
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* / clk: sprd: Hold reference returned by of_get_parent()Liang He2022-08-191-4/+5
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-06-104-17/+65
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| * clk: sprd: add mipi_csi_xx gate clocksChunyan Zhang2020-05-261-0/+32
| * clk: sprd: check its parent status before reading gate clockChunyan Zhang2020-05-262-0/+16
| * clk: sprd: return correct type of value for _sprd_pll_recalc_rateChunyan Zhang2020-05-261-1/+1
| * clk: sprd: mark the local clock symbols staticChunyan Zhang2020-05-261-16/+16
* | clk: sprd: don't gate uart console clockChunyan Zhang2020-04-131-1/+2
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* clk: sprd: fix to get a correct ibias of pllChunyan Zhang2020-04-021-3/+4
* clk: sprd: add clocks support for SC9863AChunyan Zhang2020-03-243-0/+1781
* clk: sprd: support to get regmap from parent nodeChunyan Zhang2020-03-241-1/+9
* clk: sprd: Add macros for referencing parents without stringsChunyan Zhang2020-03-245-55/+196
* clk: sprd: add gate for pll clocksXiaolong Zhang2020-03-242-2/+36
*-. Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and ...Stephen Boyd2019-11-271-1/+1
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| | * clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_...Baolin Wang2019-11-131-1/+1
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* / clk: sprd: Change to use devm_platform_ioremap_resource()Baolin Wang2019-10-161-3/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-09-202-2/+5
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| *-. Merge branches 'clk-bulk-fix', 'clk-at91' and 'clk-sprd' into clk-nextStephen Boyd2019-09-191-0/+2
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| | | * clk: sprd: add missing kfreeChunyan Zhang2019-09-171-0/+2
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| * / clk: sprd: Don't reference clk_init_data after registrationStephen Boyd2019-08-161-2/+3
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* / clk: sprd: Select REGMAP_MMIO to avoid compile errorsChunyan Zhang2019-07-221-0/+1
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* Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2019-07-172-3/+11
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| * clk: sprd: Add check for return value of sprd_clk_regmap_init()Chunyan Zhang2019-06-271-1/+4
| * clk: sprd: Check error only for devm_regmap_init_mmio()Chunyan Zhang2019-06-261-1/+1
| * clk: sprd: Switch from of_iomap() to devm_ioremap_resource()Chunyan Zhang2019-06-261-1/+6
* | treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner2019-05-212-0/+2
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* clk: sprd: Use the correct style for SPDX License IdentifierNishad Kamdar2019-05-016-6/+6
* clk: sprd: add RTC gate for SC9860Chunyan Zhang2018-03-161-0/+76
* Merge branch 'clk-divider-container' into clk-nextStephen Boyd2018-01-261-1/+2
* clk: sprd: add clocks support for SC9860Chunyan Zhang2017-12-213-0/+1987
* clk: sprd: add adjustable pll supportChunyan Zhang2017-12-213-0/+375
* clk: sprd: add composite clock supportChunyan Zhang2017-12-213-0/+112
* clk: sprd: add divider clock supportChunyan Zhang2017-12-213-0/+166
* clk: sprd: add mux clock supportChunyan Zhang2017-12-213-0/+151
* clk: sprd: add gate clock supportChunyan Zhang2017-12-213-0/+171
* clk: sprd: Add common infrastructureChunyan Zhang2017-12-214-0/+141
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 12:03:33 +0000